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[/] [pcie_ds_dma/] [trunk/] [core/] [adm/] [coregen/] [ctrl_mux8x16r.vhd] - Blame information for rev 2

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--     This file is owned and controlled by Xilinx and must be used           --
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--     solely for design, simulation, implementation and creation of          --
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--     design files limited to Xilinx devices or technologies. Use            --
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--     with non-Xilinx devices or technologies is expressly prohibited        --
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--     and immediately terminates your license.                               --
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--                                                                            --
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--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
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--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
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--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
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--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
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--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
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--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
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--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
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--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
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--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
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--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
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--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
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--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
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--     FOR A PARTICULAR PURPOSE.                                              --
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--                                                                            --
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--     Xilinx products are not intended for use in life support               --
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--     appliances, devices, or systems. Use in such applications are          --
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--     expressly prohibited.                                                  --
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--                                                                            --
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--     (c) Copyright 1995-2003 Xilinx, Inc.                                   --
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--     All rights reserved.                                                   --
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file ctrl_mux8x16r.vhd when simulating
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-- the core, ctrl_mux8x16r. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Guide".
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-- The synopsys directives "translate_off/translate_on" specified
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-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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-- synopsys translate_off
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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Library XilinxCoreLib;
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ENTITY ctrl_mux8x16r IS
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        port (
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        MA: IN std_logic_VECTOR(15 downto 0);
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        MB: IN std_logic_VECTOR(15 downto 0);
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        MC: IN std_logic_VECTOR(15 downto 0);
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        MD: IN std_logic_VECTOR(15 downto 0);
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        ME: IN std_logic_VECTOR(15 downto 0);
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        MF: IN std_logic_VECTOR(15 downto 0);
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        MG: IN std_logic_VECTOR(15 downto 0);
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        MH: IN std_logic_VECTOR(15 downto 0);
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        S: IN std_logic_VECTOR(2 downto 0);
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        Q: OUT std_logic_VECTOR(15 downto 0);
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        CLK: IN std_logic);
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END ctrl_mux8x16r;
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ARCHITECTURE ctrl_mux8x16r_a OF ctrl_mux8x16r IS
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component wrapped_ctrl_mux8x16r
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        port (
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        MA: IN std_logic_VECTOR(15 downto 0);
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        MB: IN std_logic_VECTOR(15 downto 0);
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        MC: IN std_logic_VECTOR(15 downto 0);
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        MD: IN std_logic_VECTOR(15 downto 0);
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        ME: IN std_logic_VECTOR(15 downto 0);
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        MF: IN std_logic_VECTOR(15 downto 0);
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        MG: IN std_logic_VECTOR(15 downto 0);
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        MH: IN std_logic_VECTOR(15 downto 0);
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        S: IN std_logic_VECTOR(2 downto 0);
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        Q: OUT std_logic_VECTOR(15 downto 0);
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        CLK: IN std_logic);
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end component;
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-- Configuration specification 
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        for all : wrapped_ctrl_mux8x16r use entity XilinxCoreLib.C_MUX_BUS_V6_0(behavioral)
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                generic map(
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                        c_has_aset => 0,
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                        c_has_en => 0,
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                        c_sync_priority => 1,
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                        c_has_sclr => 0,
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                        c_width => 16,
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                        c_height => 0,
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                        c_enable_rlocs => 0,
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                        c_sel_width => 3,
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                        c_latency => 1,
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                        c_ainit_val => "0000000000000000",
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                        c_has_ce => 0,
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                        c_mux_type => 0,
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                        c_has_aclr => 0,
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                        c_sync_enable => 0,
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                        c_has_ainit => 0,
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                        c_sinit_val => "0000000000000000",
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                        c_has_sset => 0,
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                        c_has_sinit => 0,
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                        c_has_q => 1,
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                        c_has_o => 0,
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                        c_inputs => 8);
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BEGIN
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U0 : wrapped_ctrl_mux8x16r
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                port map (
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                        MA => MA,
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                        MB => MB,
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                        MC => MC,
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                        MD => MD,
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                        ME => ME,
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                        MF => MF,
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                        MG => MG,
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                        MH => MH,
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                        S => S,
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                        Q => Q,
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                        CLK => CLK);
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END ctrl_mux8x16r_a;
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-- synopsys translate_on
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