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[/] [pcie_ds_dma/] [trunk/] [core/] [adm/] [main/] [cl_chn_v3.vhd] - Blame information for rev 2

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---------------------------------------------------------------------------------------------------
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--
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-- Title       : cl_chn_v3
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-- Author      : Ilya Ivanov
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-- Company     : Instrumental System
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--
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-- Version     : 3.0
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---------------------------------------------------------------------------------------------------
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--
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-- Description : Реализация общих регистров управления,
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--                               формирование прерывания и запроса DMA
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--                               Для дешифрации адреса используются только разряды 3..0.
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--                               Добавлена дешифрация регистров MODE3 и SFLAG
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--
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---------------------------------------------------------------------------------------------------
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--
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--   Version 3.1   05.04.2010
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--                                      Добавлены триггеры на сигналы rst, fifo_rst
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--
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---------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use work.adm2_pkg.all;
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package cl_chn_v3_pkg is
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component cl_chn_v3 is
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        generic (
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          -- 2 - out - для тетрады вывода
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          -- 1 - in  - для тетрады ввода
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          chn_type : integer
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        );
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        port(
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                reset: in std_logic;                            -- 0 - общий сброс
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                clk: in std_logic;                                      -- тактовая частота
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                -- Флаги
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                cmd_rdy         : in std_logic;                 -- 1 - готовность тетрады
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                rdy                     : in std_logic;                 -- 1 - готовность FIFO
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                fifo_flag       : in bl_fifo_flag;              -- флаги FIFO
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                st9                     : in std_logic:='0';     -- Разряды регистры STATUS
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                st10            : in std_logic:='0';
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                st11            : in std_logic:='0';
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                st12            : in std_logic:='0';
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                st13            : in std_logic:='0';
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                st14            : in std_logic:='0';
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                st15            : in std_logic:='0';
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                -- Тетрада      
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                data_in         : in std_logic_vector( 15 downto 0 );    -- шина данных
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                cmd                     : in bl_cmd;                                                    -- команда
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                bx_irq          : out std_logic;                                                -- 1 - прерывание от тетрады
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                bx_drq          : out bl_drq;                                                   -- запрос DMA
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                status          : out std_logic_vector( 15 downto 0 );   -- регистр STATUS
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                -- Управление
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                mode0           : out std_logic_vector( 15 downto 0 );   -- регистры тетрады
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                mode1           : out std_logic_vector( 15 downto 0 );
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                mode2           : out std_logic_vector( 15 downto 0 );
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                mode3           : out std_logic_vector( 15 downto 0 );
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                sflag           : out std_logic_vector( 15 downto 0 );
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                fdiv            : out std_logic_vector( 15 downto 0 );
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                fdiv_we         : out std_logic;                                                -- 1 - в регистре FDIV новое значение
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                fmode           : out std_logic_vector( 15 downto 0 );
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                stmode          : out std_logic_vector( 15 downto 0 );
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                cnt0            : out std_logic_vector( 15 downto 0 );
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                cnt1            : out std_logic_vector( 15 downto 0 );
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                cnt2            : out std_logic_vector( 15 downto 0 );
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                rst                     : out std_logic;                                                -- 0 - сброс тетрады
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                fifo_rst        : out std_logic                                                 -- 0 - сброс FIFO
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        );
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end component;
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end cl_chn_v3_pkg;
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80
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use work.adm2_pkg.all;
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entity cl_chn_v3 is
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        generic (
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          -- 2 - out - для тетрады вывода
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          -- 1 - in  - для тетрады ввода
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          chn_type : integer
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        );
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        port(
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                reset: in std_logic;                            -- 0 - общий сброс
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                clk: in std_logic;                                      -- тактовая частота
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                -- Флаги
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                cmd_rdy         : in std_logic;                 -- 1 - готовность тетрады
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                rdy                     : in std_logic;                 -- 1 - готовность FIFO
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                fifo_flag       : in bl_fifo_flag;              -- флаги FIFO
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                st9                     : in std_logic:='0';     -- Разряды регистры STATUS
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                st10            : in std_logic:='0';
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                st11            : in std_logic:='0';
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                st12            : in std_logic:='0';
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                st13            : in std_logic:='0';
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                st14            : in std_logic:='0';
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                st15            : in std_logic:='0';
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                -- Тетрада      
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                data_in         : in std_logic_vector( 15 downto 0 );    -- шина данных
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                cmd                     : in bl_cmd;                                                    -- команда
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                bx_irq          : out std_logic;                                                -- 1 - прерывание от тетрады
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                bx_drq          : out bl_drq;                                                   -- запрос DMA
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                status          : out std_logic_vector( 15 downto 0 );   -- регистр STATUS
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                -- Управление
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                mode0           : out std_logic_vector( 15 downto 0 );   -- регистры тетрады
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                mode1           : out std_logic_vector( 15 downto 0 );
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                mode2           : out std_logic_vector( 15 downto 0 );
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                mode3           : out std_logic_vector( 15 downto 0 );
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                sflag           : out std_logic_vector( 15 downto 0 );
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                fdiv            : out std_logic_vector( 15 downto 0 );
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                fdiv_we         : out std_logic;                                                -- 1 - в регистре FDIV новое значение
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                fmode           : out std_logic_vector( 15 downto 0 );
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                stmode          : out std_logic_vector( 15 downto 0 );
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                cnt0            : out std_logic_vector( 15 downto 0 );
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                cnt1            : out std_logic_vector( 15 downto 0 );
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                cnt2            : out std_logic_vector( 15 downto 0 );
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                rst                     : out std_logic;                                                -- 0 - сброс тетрады
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                fifo_rst        : out std_logic                                                 -- 0 - сброс FIFO
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        );
132
end cl_chn_v3;
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architecture cl_chn_v3 of cl_chn_v3 is
135
 
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signal  c_mode0, c_mode1, c_mode2, c_mode3              : std_logic_vector( 15 downto 0 );
137
signal  c_mask, c_inv, c_sflag, c_flag, c_irq   : std_logic_vector( 15 downto 0 );
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signal  c_fmode, c_fdiv, c_stmode, c_cnt0, c_cnt1, c_cnt2: std_logic_vector( 15 downto 0 );
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signal  c_status: std_logic_vector( 15 downto 0 );
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signal  c_drq_en: std_logic;
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signal  c_rst: std_logic;       -- 0 - сброс тетрады
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begin
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146
 
147
 
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mode0<=c_mode0;
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mode1<=c_mode1;
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mode2<=c_mode2;
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mode3<=c_mode3;
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sflag<=c_sflag;
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status<=c_status;
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fmode<=c_fmode;
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fdiv<=c_fdiv;
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stmode<=c_stmode;
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cnt0<=c_cnt0;
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cnt1<=c_cnt1;
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cnt2<=c_cnt2;
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pr_mode0: process( reset, clk ) begin
163
        if( reset='0' ) then
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                c_mode0<=(others=>'0');
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        elsif( rising_edge( clk ) ) then
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                if( cmd.cmd_data_we='1' ) then
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                        if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
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                          case cmd.adr( 3 downto 0 ) is
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                                  when "0000" => c_mode0<=data_in;
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                                  when others=>null;
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                          end case;
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                        end if;
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                end if;
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        end if;
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end process;
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pr_reg: process( c_rst, clk )
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 variable v: std_logic;
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begin
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        if( c_rst='0' ) then
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                c_mode1<=(others=>'0');
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                c_mode2<=(others=>'0');
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                c_mode3<=(others=>'0');
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                c_sflag<=(others=>'0');
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                c_mask<=(others=>'0');
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                c_inv<=(others=>'0');
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                c_fmode<=(others=>'0');
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                c_fdiv <=(others=>'0');
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                c_stmode<=(others=>'0');
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                c_cnt0<=(others=>'0');
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                c_cnt1<=(others=>'0');
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                c_cnt2<=(others=>'0');
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                fdiv_we<='0';
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        elsif( rising_edge( clk ) ) then
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                v:='0';
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                if( cmd.cmd_data_we='1' ) then
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                        if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
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                          case cmd.adr( 3 downto 0 ) is
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                                  when x"1" => c_mask<=data_in;
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                                  when x"2" => c_inv<=data_in;
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                                  when x"3" => c_fmode<=data_in;
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                                  when x"4" => c_fdiv<=data_in; v:='1';
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                                  when x"5" => c_stmode<=data_in;
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                                  when x"6" => c_cnt0<=data_in;
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                                  when x"7" => c_cnt1<=data_in;
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                                  when x"8" => c_cnt2<=data_in;
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                                  when x"9" => c_mode1<=data_in;
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                                  when x"a" => c_mode2<=data_in;
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                                  when x"b" => c_mode3<=data_in;
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                                  when x"c" => c_sflag<=data_in;
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                                  when others=>null;
213
                          end case;
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                        end if;
215
                end if;
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                fdiv_we<=v;
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        end if;
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end process;
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pr_status: process( clk ) begin
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        if( rising_edge( clk ) ) then
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                c_status(0)<=cmd_rdy;
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                c_status(1)<=rdy;
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                c_status(2)<=fifo_flag.ef;
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                c_status(3)<=fifo_flag.pae;
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                c_status(4)<=fifo_flag.hf;
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                c_status(5)<=fifo_flag.paf;
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                c_status(6)<=fifo_flag.ff;
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                c_status(7)<=fifo_flag.ovr;
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                c_status(8)<=fifo_flag.und;
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                c_status(9)<=st9;
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                c_status(10)<=st10;
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                c_status(11)<=st11;
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                c_status(12)<=st12;
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                c_status(13)<=st13;
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                c_status(14)<=st14;
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                c_status(15)<=st15;
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        end if;
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end process;
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c_flag<=c_status xor c_inv;
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c_irq<= c_flag and c_mask;
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pr_irq: process( c_irq, clk )
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 variable v: std_logic;
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begin
247
        v:='0';
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        for i in 0 to 15 loop
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                v:=v or c_irq( i );
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        end loop;
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        if( rising_edge( clk ) ) then
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                bx_irq<=v and c_mode0(2);
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        end if;
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end process;
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c_rst<=reset and ( not c_mode0(0) );
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rst <= c_rst  after 1 ns when rising_edge( clk );
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fifo_rst<=reset and ( not c_mode0(0) ) and ( not c_mode0(1) )  after 1 ns when rising_edge( clk );
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c_drq_en<=c_mode0( 3 );
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bx_drq.en<=c_drq_en;
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gen_out: if chn_type=2 generate
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pr_bx_drq: process( c_mode0, fifo_flag, c_drq_en, rdy )
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270
begin
271
        case c_mode0( 13 downto 12 )  is
272
                when "00" => bx_drq.req <= fifo_flag.paf and c_drq_en; -- PAF = 1 
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                when "01" => bx_drq.req <= rdy and c_drq_en;               -- RDY = 1
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                when "10" => bx_drq.req <= fifo_flag.hf and c_drq_en; -- HF  = 1
275
                when others => bx_drq.req<='0';
276
        end case;
277
end process;
278
 
279
        bx_drq.ack <= cmd.data_we and c_drq_en;
280
 
281
end generate;
282
 
283
gen_in: if chn_type=1 generate
284
 
285
pr_bx_drq: process( c_mode0, fifo_flag, c_drq_en, rdy )
286
 
287
begin
288
        case c_mode0( 13 downto 12 ) is
289
                when "00" => bx_drq.req <= fifo_flag.pae and c_drq_en; -- PAE = 1 
290
                when "01" => bx_drq.req <= rdy and c_drq_en;               -- RDY = 1
291
                when "10" => bx_drq.req <= ( not fifo_flag.hf ) and c_drq_en; -- HF  = 0
292
                when others => bx_drq.req<='0';
293
        end case;
294
end process;
295
 
296
        bx_drq.ack <= ( not cmd.data_cs )  and c_drq_en;
297
 
298
end generate;
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300
end cl_chn_v3;
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