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[/] [pcie_ds_dma/] [trunk/] [core/] [adm/] [main/] [cl_chn_v3.vhd] - Blame information for rev 2

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1 2 dsmv 
---------------------------------------------------------------------------------------------------
2 
--
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-- Title       : cl_chn_v3
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-- Author      : Ilya Ivanov
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-- Company     : Instrumental System
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--
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-- Version     : 3.0
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---------------------------------------------------------------------------------------------------
9 
--
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-- Description : Реализация общих регистров управления,
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--                               формирование прерывания и запроса DMA
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--                               Для дешифрации адреса используются только разряды 3..0.
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--                               Добавлена дешифрация регистров MODE3 и SFLAG
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--
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---------------------------------------------------------------------------------------------------
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--
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--   Version 3.1   05.04.2010
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--                                      Добавлены триггеры на сигналы rst, fifo_rst
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--
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---------------------------------------------------------------------------------------------------
21 
 
22 
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
24 
 
25 
use work.adm2_pkg.all;
26 
 
27 
package cl_chn_v3_pkg is
28 
 
29 
component cl_chn_v3 is
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        generic (
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          -- 2 - out - для тетрады вывода
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          -- 1 - in  - для тетрады ввода
33 
          chn_type : integer
34 
        );
35 
 
36 
        port(
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                reset: in std_logic;                            -- 0 - общий сброс
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                clk: in std_logic;                                      -- тактовая частота
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40 
                -- Флаги
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                cmd_rdy         : in std_logic;                 -- 1 - готовность тетрады
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                rdy                     : in std_logic;                 -- 1 - готовность FIFO
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                fifo_flag       : in bl_fifo_flag;              -- флаги FIFO
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                st9                     : in std_logic:='0';     -- Разряды регистры STATUS
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                st10            : in std_logic:='0';
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                st11            : in std_logic:='0';
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                st12            : in std_logic:='0';
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                st13            : in std_logic:='0';
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                st14            : in std_logic:='0';
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                st15            : in std_logic:='0';
51 
 
52 
                -- Тетрада
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                data_in         : in std_logic_vector( 15 downto 0 );    -- шина данных
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                cmd                     : in bl_cmd;                                                    -- команда
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                bx_irq          : out std_logic;                                                -- 1 - прерывание от тетрады
56 
                bx_drq          : out bl_drq;                                                   -- запрос DMA
57 
 
58 
                status          : out std_logic_vector( 15 downto 0 );   -- регистр STATUS
59 
 
60 
                -- Управление
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                mode0           : out std_logic_vector( 15 downto 0 );   -- регистры тетрады
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                mode1           : out std_logic_vector( 15 downto 0 );
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                mode2           : out std_logic_vector( 15 downto 0 );
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                mode3           : out std_logic_vector( 15 downto 0 );
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                sflag           : out std_logic_vector( 15 downto 0 );
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                fdiv            : out std_logic_vector( 15 downto 0 );
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                fdiv_we         : out std_logic;                                                -- 1 - в регистре FDIV новое значение
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                fmode           : out std_logic_vector( 15 downto 0 );
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                stmode          : out std_logic_vector( 15 downto 0 );
70 
                cnt0            : out std_logic_vector( 15 downto 0 );
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                cnt1            : out std_logic_vector( 15 downto 0 );
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                cnt2            : out std_logic_vector( 15 downto 0 );
73 
                rst                     : out std_logic;                                                -- 0 - сброс тетрады
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                fifo_rst        : out std_logic                                                 -- 0 - сброс FIFO
75 
        );
76 
end component;
77 
 
78 
end cl_chn_v3_pkg;
79 
 
80 
library IEEE;
81 
use IEEE.STD_LOGIC_1164.all;
82 
 
83 
use work.adm2_pkg.all;
84 
 
85 
entity cl_chn_v3 is
86 
        generic (
87 
          -- 2 - out - для тетрады вывода
88 
          -- 1 - in  - для тетрады ввода
89 
          chn_type : integer
90 
        );
91 
 
92 
        port(
93 
                reset: in std_logic;                            -- 0 - общий сброс
94 
                clk: in std_logic;                                      -- тактовая частота
95 
 
96 
                -- Флаги
97 
                cmd_rdy         : in std_logic;                 -- 1 - готовность тетрады
98 
                rdy                     : in std_logic;                 -- 1 - готовность FIFO
99 
                fifo_flag       : in bl_fifo_flag;              -- флаги FIFO
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                st9                     : in std_logic:='0';     -- Разряды регистры STATUS
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                st10            : in std_logic:='0';
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                st11            : in std_logic:='0';
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                st12            : in std_logic:='0';
104 
                st13            : in std_logic:='0';
105 
                st14            : in std_logic:='0';
106 
                st15            : in std_logic:='0';
107 
 
108 
                -- Тетрада
109 
                data_in         : in std_logic_vector( 15 downto 0 );    -- шина данных
110 
                cmd                     : in bl_cmd;                                                    -- команда
111 
                bx_irq          : out std_logic;                                                -- 1 - прерывание от тетрады
112 
                bx_drq          : out bl_drq;                                                   -- запрос DMA
113 
 
114 
                status          : out std_logic_vector( 15 downto 0 );   -- регистр STATUS
115 
 
116 
                -- Управление
117 
                mode0           : out std_logic_vector( 15 downto 0 );   -- регистры тетрады
118 
                mode1           : out std_logic_vector( 15 downto 0 );
119 
                mode2           : out std_logic_vector( 15 downto 0 );
120 
                mode3           : out std_logic_vector( 15 downto 0 );
121 
                sflag           : out std_logic_vector( 15 downto 0 );
122 
                fdiv            : out std_logic_vector( 15 downto 0 );
123 
                fdiv_we         : out std_logic;                                                -- 1 - в регистре FDIV новое значение
124 
                fmode           : out std_logic_vector( 15 downto 0 );
125 
                stmode          : out std_logic_vector( 15 downto 0 );
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                cnt0            : out std_logic_vector( 15 downto 0 );
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                cnt1            : out std_logic_vector( 15 downto 0 );
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                cnt2            : out std_logic_vector( 15 downto 0 );
129 
                rst                     : out std_logic;                                                -- 0 - сброс тетрады
130 
                fifo_rst        : out std_logic                                                 -- 0 - сброс FIFO
131 
        );
132 
end cl_chn_v3;
133 
 
134 
architecture cl_chn_v3 of cl_chn_v3 is
135 
 
136 
signal  c_mode0, c_mode1, c_mode2, c_mode3              : std_logic_vector( 15 downto 0 );
137 
signal  c_mask, c_inv, c_sflag, c_flag, c_irq   : std_logic_vector( 15 downto 0 );
138 
signal  c_fmode, c_fdiv, c_stmode, c_cnt0, c_cnt1, c_cnt2: std_logic_vector( 15 downto 0 );
139 
signal  c_status: std_logic_vector( 15 downto 0 );
140 
signal  c_drq_en: std_logic;
141 
signal  c_rst: std_logic;       -- 0 - сброс тетрады
142 
 
143 
 
144 
begin
145 
 
146 
 
147 
 
148 
mode0<=c_mode0;
149 
mode1<=c_mode1;
150 
mode2<=c_mode2;
151 
mode3<=c_mode3;
152 
sflag<=c_sflag;
153 
status<=c_status;
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fmode<=c_fmode;
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fdiv<=c_fdiv;
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stmode<=c_stmode;
157 
cnt0<=c_cnt0;
158 
cnt1<=c_cnt1;
159 
cnt2<=c_cnt2;
160 
 
161 
 
162 
pr_mode0: process( reset, clk ) begin
163 
        if( reset='0' ) then
164 
                c_mode0<=(others=>'0');
165 
        elsif( rising_edge( clk ) ) then
166 
                if( cmd.cmd_data_we='1' ) then
167 
                        if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
168 
                          case cmd.adr( 3 downto 0 ) is
169 
                                  when "0000" => c_mode0<=data_in;
170 
                                  when others=>null;
171 
                          end case;
172 
                        end if;
173 
                end if;
174 
        end if;
175 
end process;
176 
 
177 
 
178 
pr_reg: process( c_rst, clk )
179 
 variable v: std_logic;
180 
begin
181 
        if( c_rst='0' ) then
182 
                c_mode1<=(others=>'0');
183 
                c_mode2<=(others=>'0');
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                c_mode3<=(others=>'0');
185 
                c_sflag<=(others=>'0');
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                c_mask<=(others=>'0');
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                c_inv<=(others=>'0');
188 
                c_fmode<=(others=>'0');
189 
                c_fdiv <=(others=>'0');
190 
                c_stmode<=(others=>'0');
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                c_cnt0<=(others=>'0');
192 
                c_cnt1<=(others=>'0');
193 
                c_cnt2<=(others=>'0');
194 
                fdiv_we<='0';
195 
        elsif( rising_edge( clk ) ) then
196 
                v:='0';
197 
                if( cmd.cmd_data_we='1' ) then
198 
                        if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
199 
                          case cmd.adr( 3 downto 0 ) is
200 
                                  when x"1" => c_mask<=data_in;
201 
                                  when x"2" => c_inv<=data_in;
202 
                                  when x"3" => c_fmode<=data_in;
203 
                                  when x"4" => c_fdiv<=data_in; v:='1';
204 
                                  when x"5" => c_stmode<=data_in;
205 
                                  when x"6" => c_cnt0<=data_in;
206 
                                  when x"7" => c_cnt1<=data_in;
207 
                                  when x"8" => c_cnt2<=data_in;
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                                  when x"9" => c_mode1<=data_in;
209 
                                  when x"a" => c_mode2<=data_in;
210 
                                  when x"b" => c_mode3<=data_in;
211 
                                  when x"c" => c_sflag<=data_in;
212 
                                  when others=>null;
213 
                          end case;
214 
                        end if;
215 
                end if;
216 
                fdiv_we<=v;
217 
        end if;
218 
end process;
219 
 
220 
pr_status: process( clk ) begin
221 
        if( rising_edge( clk ) ) then
222 
                c_status(0)<=cmd_rdy;
223 
                c_status(1)<=rdy;
224 
                c_status(2)<=fifo_flag.ef;
225 
                c_status(3)<=fifo_flag.pae;
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                c_status(4)<=fifo_flag.hf;
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                c_status(5)<=fifo_flag.paf;
228 
                c_status(6)<=fifo_flag.ff;
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                c_status(7)<=fifo_flag.ovr;
230 
                c_status(8)<=fifo_flag.und;
231 
                c_status(9)<=st9;
232 
                c_status(10)<=st10;
233 
                c_status(11)<=st11;
234 
                c_status(12)<=st12;
235 
                c_status(13)<=st13;
236 
                c_status(14)<=st14;
237 
                c_status(15)<=st15;
238 
        end if;
239 
end process;
240 
 
241 
c_flag<=c_status xor c_inv;
242 
c_irq<= c_flag and c_mask;
243 
 
244 
pr_irq: process( c_irq, clk )
245 
 variable v: std_logic;
246 
begin
247 
        v:='0';
248 
        for i in 0 to 15 loop
249 
                v:=v or c_irq( i );
250 
        end loop;
251 
        if( rising_edge( clk ) ) then
252 
                bx_irq<=v and c_mode0(2);
253 
        end if;
254 
end process;
255 
 
256 
 
257 
c_rst<=reset and ( not c_mode0(0) );
258 
rst <= c_rst  after 1 ns when rising_edge( clk );
259 
 
260 
fifo_rst<=reset and ( not c_mode0(0) ) and ( not c_mode0(1) )  after 1 ns when rising_edge( clk );
261 
 
262 
c_drq_en<=c_mode0( 3 );
263 
 
264 
bx_drq.en<=c_drq_en;
265 
 
266 
gen_out: if chn_type=2 generate
267 
 
268 
pr_bx_drq: process( c_mode0, fifo_flag, c_drq_en, rdy )
269 
 
270 
begin
271 
        case c_mode0( 13 downto 12 )  is
272 
                when "00" => bx_drq.req <= fifo_flag.paf and c_drq_en; -- PAF = 1
273 
                when "01" => bx_drq.req <= rdy and c_drq_en;               -- RDY = 1
274 
                when "10" => bx_drq.req <= fifo_flag.hf and c_drq_en; -- HF  = 1
275 
                when others => bx_drq.req<='0';
276 
        end case;
277 
end process;
278 
 
279 
        bx_drq.ack <= cmd.data_we and c_drq_en;
280 
 
281 
end generate;
282 
 
283 
gen_in: if chn_type=1 generate
284 
 
285 
pr_bx_drq: process( c_mode0, fifo_flag, c_drq_en, rdy )
286 
 
287 
begin
288 
        case c_mode0( 13 downto 12 ) is
289 
                when "00" => bx_drq.req <= fifo_flag.pae and c_drq_en; -- PAE = 1
290 
                when "01" => bx_drq.req <= rdy and c_drq_en;               -- RDY = 1
291 
                when "10" => bx_drq.req <= ( not fifo_flag.hf ) and c_drq_en; -- HF  = 0
292 
                when others => bx_drq.req<='0';
293 
        end case;
294 
end process;
295 
 
296 
        bx_drq.ack <= ( not cmd.data_cs )  and c_drq_en;
297 
 
298 
end generate;
299 
 
300 
end cl_chn_v3;
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