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[/] [pcie_ds_dma/] [trunk/] [core/] [adm/] [main/] [cl_chn_v4.vhd] - Blame information for rev 2

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---------------------------------------------------------------------------------------------------
--
-- Title       : cl_chn_v4
-- Author      : Dmitry Smekhov
-- Company     : Instrumental System
--                                                                      
-- Version         : 2.4
--
---------------------------------------------------------------------------------------------------
--
-- Description : ���������� ����� ��������� ����������,
--                               ������������ ���������� � ������� DMA
--                               ����������� 4.
--                               ��� ���������� ������ ������������ ������� 4..0.                                 
--                               ����������� ��������:
--                                      MODE0, MODE1, MODE2, MODE3, SFLAG_PAE, SFLAG_PAF, PRT_MODE
--                                      STMODE, FMODE, CNT0, CNT1, CNT2
--                                      CHAN1, FORMAT
--
---------------------------------------------------------------------------------------------------
--
--   Version 2.4   05.04.2010
--                                      ��������� �������� �� ������� rst, fifo_rst
--
---------------------------------------------------------------------------------------------------
--
-- Version 2.3  14.04.2006
--              �������� ����� �������� TL_MODE (�������)       
--
-- Version 2.2  29.10.2004
--                              ���������� ������ � ������� mode3
--                                      
-- Version 2.1  25.09.2004
--                              ���������� ������� DMA ����������� �������� prt_wr_start
--
-- Version 2.0  03.08.2004
--                              ��������� ������ SFLAG_PAE, SFLAG_PAF
--
---------------------------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.adm2_pkg.all;
 
package cl_chn_v4_pkg is
 
component cl_chn_v4 is
        generic (
          -- 2 - out - ��� ������� ������
          -- 1 - in  - ��� ������� �����
          chn_type : integer
        );
 
        port(
                reset           : in std_logic;                 -- 0 - ����� �����
                clk                     : in std_logic;                 -- �������� �������
 
                -- �����
                cmd_rdy         : in std_logic;                 -- 1 - ���������� �������
                rdy                     : in std_logic;                 -- 1 - ���������� FIFO
                fifo_flag       : in bl_fifo_flag;              -- ����� FIFO
                st9                     : in std_logic:='0';     -- ������� �������� STATUS
                st10            : in std_logic:='0';
                st11            : in std_logic:='0';
                st12            : in std_logic:='0';
                st13            : in std_logic:='0';
                st14            : in std_logic:='0';
                st15            : in std_logic:='0';
 
                -- �������      
                data_in         : in std_logic_vector( 15 downto 0 );    -- ���� ������
                cmd                     : in bl_cmd;                                                    -- �������
                bx_irq          : out std_logic;                                                -- 1 - ���������� �� �������
                bx_drq          : out bl_drq;                                                   -- ������ DMA
 
                status          : out std_logic_vector( 15 downto 0 );   -- ������� STATUS
 
                -- ����������
                mode0           : out std_logic_vector( 15 downto 0 );   -- �������� �������
                fdiv            : out std_logic_vector( 15 downto 0 );
                fdiv_we         : out std_logic;                                                -- 1 - � �������� FDIV ����� ��������
                fmode           : out std_logic_vector( 15 downto 0 );
                stmode          : out std_logic_vector( 15 downto 0 );
                cnt0            : out std_logic_vector( 15 downto 0 );
                cnt1            : out std_logic_vector( 15 downto 0 );
                cnt2            : out std_logic_vector( 15 downto 0 );
                mode1           : out std_logic_vector( 15 downto 0 );
                mode2           : out std_logic_vector( 15 downto 0 );
                mode3           : out std_logic_vector( 15 downto 0 );
                sflag_pae       : out std_logic_vector( 15 downto 0 );
                sflag_paf       : out std_logic_vector( 15 downto 0 );
                prt_mode        : out std_logic_vector( 15 downto 0 );
                tl_mode         : out std_logic_vector( 15 downto 0 );
 
                chan1           : out std_logic_vector( 1 downto 0 );
                format          : out std_logic;
 
                rst                     : out std_logic;                                                -- 0 - ����� �������
                fifo_rst        : out std_logic;                                                -- 0 - ����� FIFO
                prt_wr_start: in  std_logic:='1'                                        -- 1 - ��������� ������� ������ � ������ �����������
        );
end component;
 
end package cl_chn_v4_pkg;
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.adm2_pkg.all;
 
entity cl_chn_v4 is
        generic (
          -- 2 - out - ��� ������� ������
          -- 1 - in  - ��� ������� �����
          chn_type : integer
        );
 
        port(
                reset           : in std_logic;                 -- 0 - ����� �����
                clk                     : in std_logic;                 -- �������� �������
 
                -- �����
                cmd_rdy         : in std_logic;                 -- 1 - ���������� �������
                rdy                     : in std_logic;                 -- 1 - ���������� FIFO
                fifo_flag       : in bl_fifo_flag;              -- ����� FIFO
                st9                     : in std_logic:='0';     -- ������� �������� STATUS
                st10            : in std_logic:='0';
                st11            : in std_logic:='0';
                st12            : in std_logic:='0';
                st13            : in std_logic:='0';
                st14            : in std_logic:='0';
                st15            : in std_logic:='0';
 
                -- �������      
                data_in         : in std_logic_vector( 15 downto 0 );    -- ���� ������
                cmd                     : in bl_cmd;                                                    -- �������
                bx_irq          : out std_logic;                                                -- 1 - ���������� �� �������
                bx_drq          : out bl_drq;                                                   -- ������ DMA
 
                status          : out std_logic_vector( 15 downto 0 );   -- ������� STATUS
 
                -- ����������
                mode0           : out std_logic_vector( 15 downto 0 );   -- �������� �������
                fdiv            : out std_logic_vector( 15 downto 0 );
                fdiv_we         : out std_logic;                                                -- 1 - � �������� FDIV ����� ��������
                fmode           : out std_logic_vector( 15 downto 0 );
                stmode          : out std_logic_vector( 15 downto 0 );
                cnt0            : out std_logic_vector( 15 downto 0 );
                cnt1            : out std_logic_vector( 15 downto 0 );
                cnt2            : out std_logic_vector( 15 downto 0 );
                mode1           : out std_logic_vector( 15 downto 0 );
                mode2           : out std_logic_vector( 15 downto 0 );
                mode3           : out std_logic_vector( 15 downto 0 );
                sflag_pae       : out std_logic_vector( 15 downto 0 );
                sflag_paf       : out std_logic_vector( 15 downto 0 );
                prt_mode        : out std_logic_vector( 15 downto 0 );
                tl_mode         : out std_logic_vector( 15 downto 0 );
 
                chan1           : out std_logic_vector( 1 downto 0 );
                format          : out std_logic;
 
                rst                     : out std_logic;                                                -- 0 - ����� �������
                fifo_rst        : out std_logic;                                                -- 0 - ����� FIFO
                prt_wr_start: in  std_logic:='1'                                        -- 1 - ��������� ������� ������ � ������ �����������
        );
end cl_chn_v4;
 
architecture cl_chn_v4 of cl_chn_v4 is
 
signal  c_mode0, c_mask, c_inv, c_mode1, c_mode2, c_flag, c_irq : std_logic_vector( 15 downto 0 );
signal  c_fmode, c_fdiv, c_stmode, c_cnt0, c_cnt1, c_cnt2: std_logic_vector( 15 downto 0 );
signal  c_mode3, c_sflag        : std_logic_vector( 15 downto 0 );
signal  c_sflag_pae, c_sflag_paf, c_prt_mode,c_tl_mode  : std_logic_vector( 15 downto 0 );
signal  c_status        : std_logic_vector( 15 downto 0 );
signal  c_drq_en        : std_logic;
signal  c_rst           : std_logic;    -- 0 - ����� �������
signal  drq_req         : std_logic;
 
 
begin
 
 
 
mode0<=c_mode0;
mode1<=c_mode1;
mode2<=c_mode2;
mode3<=c_mode3;
status<=c_status;
fmode<=c_fmode;
fdiv<=c_fdiv;
stmode<=c_stmode;
cnt0<=c_cnt0;
cnt1<=c_cnt1;
cnt2<=c_cnt2;
sflag_pae <= c_sflag_pae;
sflag_paf <= c_sflag_paf;
prt_mode <= c_prt_mode;
tl_mode <= c_tl_mode;
 
pr_mode0: process( reset, clk ) begin
        if( reset='0' ) then
                c_mode0<=(others=>'0');
        elsif( rising_edge( clk ) ) then
                if( cmd.cmd_data_we='1' ) then
                        if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
                          case cmd.adr( 4 downto 0 ) is
                                  when "00000" => c_mode0<=data_in;
                                  when others=>null;
                          end case;
                        end if;
                end if;
        end if;
end process;
 
 
pr_reg: process( c_rst, clk )
 variable v: std_logic;
begin
        if( c_rst='0' ) then
                c_mode1<=(others=>'0');
                c_mode2<=(others=>'0');
                c_mode3<=(others=>'0');
                c_sflag_pae<=(others=>'0');
                c_sflag_paf<=(others=>'0');
                c_prt_mode<=(others=>'0');
                c_tl_mode<=(others=>'0');
                c_mask<=(others=>'0');
                c_inv<=(others=>'0');
                c_fmode<=(others=>'0');
                c_fdiv <=(others=>'0');
                c_stmode<=(others=>'0');
                c_cnt0<=(others=>'0');
                c_cnt1<=(others=>'0');
                c_cnt2<=(others=>'0');
                chan1<=(others=>'0');
                fdiv_we<='0';
                format  <='0';
        elsif( rising_edge( clk ) ) then
                v:='0';
                if( cmd.cmd_data_we='1' ) then
                        if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
                          case cmd.adr( 4 downto 0 ) is
                                  when "00001" => c_mask<=data_in;
                                  when "00010" => c_inv<=data_in;
                                  when "00011" => c_fmode<=data_in;
                                  when "00100" => c_fdiv<=data_in; v:='1';
                                  when "00101" => c_stmode<=data_in;
                                  when "00110" => c_cnt0<=data_in;
                                  when "00111" => c_cnt1<=data_in;
                                  when "01000" => c_cnt2<=data_in;
                                  when "01001" => c_mode1<=data_in;
                                  when "01010" => c_mode2<=data_in;
                                  when "01011" => c_mode3<=data_in;
                                  when "01100" => c_sflag_pae<=data_in;
                                  when "01101" => c_sflag_paf<=data_in;
                                  when "01110" => c_prt_mode<=data_in;
                                  when "01111" => c_tl_mode<=data_in;
                                  when "10000" => chan1 <= data_in( 1 downto 0 );
                                  when "10010" => format <= data_in( 0 );
                                  when others=>null;
                          end case;
                        end if;
                end if;
                fdiv_we<=v;
        end if;
end process;
 
pr_status: process( clk ) begin
        if( rising_edge( clk ) ) then
                c_status(0)<=cmd_rdy;
                c_status(1)<=rdy and prt_wr_start;
                c_status(2)<=fifo_flag.ef;
                c_status(3)<=fifo_flag.pae;
                c_status(4)<=fifo_flag.hf;
                c_status(5)<=fifo_flag.paf;
                c_status(6)<=fifo_flag.ff;
                c_status(7)<=fifo_flag.ovr;
                c_status(8)<=fifo_flag.und;
                c_status(9)<=st9;
                c_status(10)<=st10;
                c_status(11)<=st11;
                c_status(12)<=st12;
                c_status(13)<=st13;
                c_status(14)<=st14;
                c_status(15)<=st15;
        end if;
end process;
 
c_flag<=c_status xor c_inv;
c_irq<= c_flag and c_mask;
 
pr_irq: process( c_irq, clk )
 variable v: std_logic;
begin
        v:='0';
        for i in 0 to 15 loop
                v:=v or c_irq( i );
        end loop;
        if( rising_edge( clk ) ) then
                bx_irq<=v and c_mode0(2);
        end if;
end process;
 
 
c_rst<=reset and ( not c_mode0(0) );
rst <= c_rst  after 1 ns when rising_edge( clk );
 
fifo_rst<=reset and ( not c_mode0(0) ) and ( not c_mode0(1) )  after 1 ns when rising_edge( clk );
 
c_drq_en<=c_mode0( 3 ) and prt_wr_start;
 
bx_drq.en<=c_drq_en;
 
gen_out: if chn_type=2 generate
 
pr_bx_drq: process( c_mode0, fifo_flag, c_drq_en, rdy )
 
begin
        case c_mode0( 13 downto 12 )  is
                when "00" => drq_req <= fifo_flag.paf and c_drq_en; -- PAF = 1 
                when "01" => drq_req <= rdy and c_drq_en;                  -- RDY = 1
                when "10" => drq_req <= fifo_flag.hf and c_drq_en; -- HF  = 1
                when others => drq_req<='0';
        end case;
end process;
 
        bx_drq.ack <= cmd.data_we and c_drq_en;
 
end generate;
 
gen_in: if chn_type=1 generate
 
pr_bx_drq: process( c_mode0, fifo_flag, c_drq_en, rdy )
 
begin
        case c_mode0( 13 downto 12 ) is
                when "00" => drq_req <= fifo_flag.pae and c_drq_en;     -- PAE = 1 
                when "01" => drq_req <= rdy and c_drq_en;                       -- RDY = 1
                when "10" => drq_req <= ( not fifo_flag.hf ) and c_drq_en; -- HF  = 0
                when others => drq_req<='0';
        end case;
end process;
 
        bx_drq.ack <= ( not cmd.data_cs )  and c_drq_en;
 
end generate;
 
bx_drq.req <= drq_req when c_prt_mode(0)='0' or c_prt_mode(1)='1'
                                          else drq_req and prt_wr_start;
 
 
end cl_chn_v4;

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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [adm/] [main/] [cl_chn_v4.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dsmv	`---------------------------------------------------------------------------------------------------`
2			`--`
3			`-- Title : cl_chn_v4`
4			`-- Author : Dmitry Smekhov`
5			`-- Company : Instrumental System`
6			`--`
7			`-- Version : 2.4`
8			`--`
9			`---------------------------------------------------------------------------------------------------`
10			`--`
11			`-- Description : �� ,`
12			`-- �� DMA`
13			`-- �� 4.`
14			`-- �� 4..0.`
15			`-- �� :`
16			`-- MODE0, MODE1, MODE2, MODE3, SFLAG_PAE, SFLAG_PAF, PRT_MODE`
17			`-- STMODE, FMODE, CNT0, CNT1, CNT2`
18			`-- CHAN1, FORMAT`
19			`--`
20			`---------------------------------------------------------------------------------------------------`
21			`--`
22			`-- Version 2.4 05.04.2010`
23			`-- �� rst, fifo_rst`
24			`--`
25			`---------------------------------------------------------------------------------------------------`
26			`--`
27			`-- Version 2.3 14.04.2006`
28			`-- �� TL_MODE (��)`
29			`--`
30			`-- Version 2.2 29.10.2004`
31			`-- �� mode3`
32			`--`
33			`-- Version 2.1 25.09.2004`
34			`-- �� DMA �� prt_wr_start`
35			`--`
36			`-- Version 2.0 03.08.2004`
37			`-- �� SFLAG_PAE, SFLAG_PAF`
38			`--`
39			`---------------------------------------------------------------------------------------------------`
40
41
42			`library ieee;`
43			`use ieee.std_logic_1164.all;`
44
45			`use work.adm2_pkg.all;`
46
47			`package cl_chn_v4_pkg is`
48
49			`component cl_chn_v4 is`
50			`generic (`
51			`-- 2 - out - �� `
52			`-- 1 - in - �� `
53			`chn_type : integer`
54			`);`
55
56			`port(`
57			`reset : in std_logic; -- 0 - �� `
58			`clk : in std_logic; -- �� `
59
60			`-- ��`
61			`cmd_rdy : in std_logic; -- 1 - �� `
62			`rdy : in std_logic; -- 1 - �� FIFO`
63			`fifo_flag : in bl_fifo_flag; -- �� FIFO`
64			`st9 : in std_logic:='0'; -- �� STATUS`
65			`st10 : in std_logic:='0';`
66			`st11 : in std_logic:='0';`
67			`st12 : in std_logic:='0';`
68			`st13 : in std_logic:='0';`
69			`st14 : in std_logic:='0';`
70			`st15 : in std_logic:='0';`
71
72			`-- ��`
73			`data_in : in std_logic_vector( 15 downto 0 ); -- �� `
74			`cmd : in bl_cmd; -- ��`
75			`bx_irq : out std_logic; -- 1 - �� `
76			`bx_drq : out bl_drq; -- �� DMA`
77
78			`status : out std_logic_vector( 15 downto 0 ); -- �� STATUS`
79
80			`-- ��`
81			`mode0 : out std_logic_vector( 15 downto 0 ); -- �� `
82			`fdiv : out std_logic_vector( 15 downto 0 );`
83			`fdiv_we : out std_logic; -- 1 - � �� FDIV �� `
84			`fmode : out std_logic_vector( 15 downto 0 );`
85			`stmode : out std_logic_vector( 15 downto 0 );`
86			`cnt0 : out std_logic_vector( 15 downto 0 );`
87			`cnt1 : out std_logic_vector( 15 downto 0 );`
88			`cnt2 : out std_logic_vector( 15 downto 0 );`
89			`mode1 : out std_logic_vector( 15 downto 0 );`
90			`mode2 : out std_logic_vector( 15 downto 0 );`
91			`mode3 : out std_logic_vector( 15 downto 0 );`
92			`sflag_pae : out std_logic_vector( 15 downto 0 );`
93			`sflag_paf : out std_logic_vector( 15 downto 0 );`
94			`prt_mode : out std_logic_vector( 15 downto 0 );`
95			`tl_mode : out std_logic_vector( 15 downto 0 );`
96
97			`chan1 : out std_logic_vector( 1 downto 0 );`
98			`format : out std_logic;`
99
100			`rst : out std_logic; -- 0 - �� `
101			`fifo_rst : out std_logic; -- 0 - �� FIFO`
102			`prt_wr_start: in std_logic:='1' -- 1 - �� `
103			`);`
104			`end component;`
105
106			`end package cl_chn_v4_pkg;`
107
108			`library ieee;`
109			`use ieee.std_logic_1164.all;`
110
111			`use work.adm2_pkg.all;`
112
113			`entity cl_chn_v4 is`
114			`generic (`
115			`-- 2 - out - �� `
116			`-- 1 - in - �� `
117			`chn_type : integer`
118			`);`
119
120			`port(`
121			`reset : in std_logic; -- 0 - �� `
122			`clk : in std_logic; -- �� `
123
124			`-- ��`
125			`cmd_rdy : in std_logic; -- 1 - �� `
126			`rdy : in std_logic; -- 1 - �� FIFO`
127			`fifo_flag : in bl_fifo_flag; -- �� FIFO`
128			`st9 : in std_logic:='0'; -- �� STATUS`
129			`st10 : in std_logic:='0';`
130			`st11 : in std_logic:='0';`
131			`st12 : in std_logic:='0';`
132			`st13 : in std_logic:='0';`
133			`st14 : in std_logic:='0';`
134			`st15 : in std_logic:='0';`
135
136			`-- ��`
137			`data_in : in std_logic_vector( 15 downto 0 ); -- �� `
138			`cmd : in bl_cmd; -- ��`
139			`bx_irq : out std_logic; -- 1 - �� `
140			`bx_drq : out bl_drq; -- �� DMA`
141
142			`status : out std_logic_vector( 15 downto 0 ); -- �� STATUS`
143
144			`-- ��`
145			`mode0 : out std_logic_vector( 15 downto 0 ); -- �� `
146			`fdiv : out std_logic_vector( 15 downto 0 );`
147			`fdiv_we : out std_logic; -- 1 - � �� FDIV �� `
148			`fmode : out std_logic_vector( 15 downto 0 );`
149			`stmode : out std_logic_vector( 15 downto 0 );`
150			`cnt0 : out std_logic_vector( 15 downto 0 );`
151			`cnt1 : out std_logic_vector( 15 downto 0 );`
152			`cnt2 : out std_logic_vector( 15 downto 0 );`
153			`mode1 : out std_logic_vector( 15 downto 0 );`
154			`mode2 : out std_logic_vector( 15 downto 0 );`
155			`mode3 : out std_logic_vector( 15 downto 0 );`
156			`sflag_pae : out std_logic_vector( 15 downto 0 );`
157			`sflag_paf : out std_logic_vector( 15 downto 0 );`
158			`prt_mode : out std_logic_vector( 15 downto 0 );`
159			`tl_mode : out std_logic_vector( 15 downto 0 );`
160
161			`chan1 : out std_logic_vector( 1 downto 0 );`
162			`format : out std_logic;`
163
164			`rst : out std_logic; -- 0 - �� `
165			`fifo_rst : out std_logic; -- 0 - �� FIFO`
166			`prt_wr_start: in std_logic:='1' -- 1 - �� `
167			`);`
168			`end cl_chn_v4;`
169
170			`architecture cl_chn_v4 of cl_chn_v4 is`
171
172			`signal c_mode0, c_mask, c_inv, c_mode1, c_mode2, c_flag, c_irq : std_logic_vector( 15 downto 0 );`
173			`signal c_fmode, c_fdiv, c_stmode, c_cnt0, c_cnt1, c_cnt2: std_logic_vector( 15 downto 0 );`
174			`signal c_mode3, c_sflag : std_logic_vector( 15 downto 0 );`
175			`signal c_sflag_pae, c_sflag_paf, c_prt_mode,c_tl_mode : std_logic_vector( 15 downto 0 );`
176			`signal c_status : std_logic_vector( 15 downto 0 );`
177			`signal c_drq_en : std_logic;`
178			`signal c_rst : std_logic; -- 0 - �� `
179			`signal drq_req : std_logic;`
180
181
182			`begin`
183
184
185
186			`mode0<=c_mode0;`
187			`mode1<=c_mode1;`
188			`mode2<=c_mode2;`
189			`mode3<=c_mode3;`
190			`status<=c_status;`
191			`fmode<=c_fmode;`
192			`fdiv<=c_fdiv;`
193			`stmode<=c_stmode;`
194			`cnt0<=c_cnt0;`
195			`cnt1<=c_cnt1;`
196			`cnt2<=c_cnt2;`
197			`sflag_pae <= c_sflag_pae;`
198			`sflag_paf <= c_sflag_paf;`
199			`prt_mode <= c_prt_mode;`
200			`tl_mode <= c_tl_mode;`
201
202			`pr_mode0: process( reset, clk ) begin`
203			`if( reset='0' ) then`
204			`c_mode0<=(others=>'0');`
205			`elsif( rising_edge( clk ) ) then`
206			`if( cmd.cmd_data_we='1' ) then`
207			`if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then`
208			`case cmd.adr( 4 downto 0 ) is`
209			`when "00000" => c_mode0<=data_in;`
210			`when others=>null;`
211			`end case;`
212			`end if;`
213			`end if;`
214			`end if;`
215			`end process;`
216
217
218			`pr_reg: process( c_rst, clk )`
219			`variable v: std_logic;`
220			`begin`
221			`if( c_rst='0' ) then`
222			`c_mode1<=(others=>'0');`
223			`c_mode2<=(others=>'0');`
224			`c_mode3<=(others=>'0');`
225			`c_sflag_pae<=(others=>'0');`
226			`c_sflag_paf<=(others=>'0');`
227			`c_prt_mode<=(others=>'0');`
228			`c_tl_mode<=(others=>'0');`
229			`c_mask<=(others=>'0');`
230			`c_inv<=(others=>'0');`
231			`c_fmode<=(others=>'0');`
232			`c_fdiv <=(others=>'0');`
233			`c_stmode<=(others=>'0');`
234			`c_cnt0<=(others=>'0');`
235			`c_cnt1<=(others=>'0');`
236			`c_cnt2<=(others=>'0');`
237			`chan1<=(others=>'0');`
238			`fdiv_we<='0';`
239			`format <='0';`
240			`elsif( rising_edge( clk ) ) then`
241			`v:='0';`
242			`if( cmd.cmd_data_we='1' ) then`
243			`if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then`
244			`case cmd.adr( 4 downto 0 ) is`
245			`when "00001" => c_mask<=data_in;`
246			`when "00010" => c_inv<=data_in;`
247			`when "00011" => c_fmode<=data_in;`
248			`when "00100" => c_fdiv<=data_in; v:='1';`
249			`when "00101" => c_stmode<=data_in;`
250			`when "00110" => c_cnt0<=data_in;`
251			`when "00111" => c_cnt1<=data_in;`
252			`when "01000" => c_cnt2<=data_in;`
253			`when "01001" => c_mode1<=data_in;`
254			`when "01010" => c_mode2<=data_in;`
255			`when "01011" => c_mode3<=data_in;`
256			`when "01100" => c_sflag_pae<=data_in;`
257			`when "01101" => c_sflag_paf<=data_in;`
258			`when "01110" => c_prt_mode<=data_in;`
259			`when "01111" => c_tl_mode<=data_in;`
260			`when "10000" => chan1 <= data_in( 1 downto 0 );`
261			`when "10010" => format <= data_in( 0 );`
262			`when others=>null;`
263			`end case;`
264			`end if;`
265			`end if;`
266			`fdiv_we<=v;`
267			`end if;`
268			`end process;`
269
270			`pr_status: process( clk ) begin`
271			`if( rising_edge( clk ) ) then`
272			`c_status(0)<=cmd_rdy;`
273			`c_status(1)<=rdy and prt_wr_start;`
274			`c_status(2)<=fifo_flag.ef;`
275			`c_status(3)<=fifo_flag.pae;`
276			`c_status(4)<=fifo_flag.hf;`
277			`c_status(5)<=fifo_flag.paf;`
278			`c_status(6)<=fifo_flag.ff;`
279			`c_status(7)<=fifo_flag.ovr;`
280			`c_status(8)<=fifo_flag.und;`
281			`c_status(9)<=st9;`
282			`c_status(10)<=st10;`
283			`c_status(11)<=st11;`
284			`c_status(12)<=st12;`
285			`c_status(13)<=st13;`
286			`c_status(14)<=st14;`
287			`c_status(15)<=st15;`
288			`end if;`
289			`end process;`
290
291			`c_flag<=c_status xor c_inv;`
292			`c_irq<= c_flag and c_mask;`
293
294			`pr_irq: process( c_irq, clk )`
295			`variable v: std_logic;`
296			`begin`
297			`v:='0';`
298			`for i in 0 to 15 loop`
299			`v:=v or c_irq( i );`
300			`end loop;`
301			`if( rising_edge( clk ) ) then`
302			`bx_irq<=v and c_mode0(2);`
303			`end if;`
304			`end process;`
305
306
307			`c_rst<=reset and ( not c_mode0(0) );`
308			`rst <= c_rst after 1 ns when rising_edge( clk );`
309
310			`fifo_rst<=reset and ( not c_mode0(0) ) and ( not c_mode0(1) ) after 1 ns when rising_edge( clk );`
311
312			`c_drq_en<=c_mode0( 3 ) and prt_wr_start;`
313
314			`bx_drq.en<=c_drq_en;`
315
316			`gen_out: if chn_type=2 generate`
317
318			`pr_bx_drq: process( c_mode0, fifo_flag, c_drq_en, rdy )`
319
320			`begin`
321			`case c_mode0( 13 downto 12 ) is`
322			`when "00" => drq_req <= fifo_flag.paf and c_drq_en; -- PAF = 1`
323			`when "01" => drq_req <= rdy and c_drq_en; -- RDY = 1`
324			`when "10" => drq_req <= fifo_flag.hf and c_drq_en; -- HF = 1`
325			`when others => drq_req<='0';`
326			`end case;`
327			`end process;`
328
329			`bx_drq.ack <= cmd.data_we and c_drq_en;`
330
331			`end generate;`
332
333			`gen_in: if chn_type=1 generate`
334
335			`pr_bx_drq: process( c_mode0, fifo_flag, c_drq_en, rdy )`
336
337			`begin`
338			`case c_mode0( 13 downto 12 ) is`
339			`when "00" => drq_req <= fifo_flag.pae and c_drq_en; -- PAE = 1`
340			`when "01" => drq_req <= rdy and c_drq_en; -- RDY = 1`
341			`when "10" => drq_req <= ( not fifo_flag.hf ) and c_drq_en; -- HF = 0`
342			`when others => drq_req<='0';`
343			`end case;`
344			`end process;`
345
346			`bx_drq.ack <= ( not cmd.data_cs ) and c_drq_en;`
347
348			`end generate;`
349
350			`bx_drq.req <= drq_req when c_prt_mode(0)='0' or c_prt_mode(1)='1'`
351			`else drq_req and prt_wr_start;`
352
353
354			`end cl_chn_v4;`