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--
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-- Title : cl_chn_v4
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-- Author : Dmitry Smekhov
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-- Company : Instrumental System
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--
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-- Version : 2.4
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Description : Ðåàëèçàöèÿ îáùèõ ðåãèñòðîâ óïðàâëåíèÿ,
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-- ôîðìèðîâàíèå ïðåðûâàíèÿ è çàïðîñà DMA
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-- Ìîäèôèêàöèÿ 4.
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-- Äëÿ äåøèôðàöèè àäðåñà èñïîëüçóþòñÿ ðàçðÿäû 4..0.
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-- Ôîðìèðóþòñÿ ðåãèñòðû:
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-- MODE0, MODE1, MODE2, MODE3, SFLAG_PAE, SFLAG_PAF, PRT_MODE
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-- STMODE, FMODE, CNT0, CNT1, CNT2
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-- CHAN1, FORMAT
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Version 2.4 05.04.2010
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-- Äîáàâëåíû òðèããåðû íà ñèãíàëû rst, fifo_rst
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Version 2.3 14.04.2006
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-- äîáàâëåí âûõîä ðåãèñòðà TL_MODE (Ñîêîëîâ)
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--
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-- Version 2.2 29.10.2004
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-- Èñïðàâëåíà çàïèñü â ðåãèñòð mode3
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--
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-- Version 2.1 25.09.2004
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-- Ðàçðåøåíèå çàïðîñà DMA ìàñêèðóåòñÿ ñèãíàëîì prt_wr_start
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--
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-- Version 2.0 03.08.2004
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-- Äîáàâëåíû âûõîäû SFLAG_PAE, SFLAG_PAF
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--
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---------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.adm2_pkg.all;
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package cl_chn_v4_pkg is
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component cl_chn_v4 is
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generic (
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-- 2 - out - äëÿ òåòðàäû âûâîäà
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-- 1 - in - äëÿ òåòðàäû ââîäà
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chn_type : integer
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);
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port(
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reset : in std_logic; -- 0 - îáùèé ñáðîñ
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clk : in std_logic; -- òàêòîâàÿ ÷àñòîòà
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-- Ôëàãè
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cmd_rdy : in std_logic; -- 1 - ãîòîâíîñòü òåòðàäû
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rdy : in std_logic; -- 1 - ãîòîâíîñòü FIFO
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fifo_flag : in bl_fifo_flag; -- ôëàãè FIFO
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st9 : in std_logic:='0'; -- Ðàçðÿäû ðåãèñòðà STATUS
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st10 : in std_logic:='0';
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st11 : in std_logic:='0';
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st12 : in std_logic:='0';
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st13 : in std_logic:='0';
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st14 : in std_logic:='0';
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st15 : in std_logic:='0';
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-- Òåòðàäà
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data_in : in std_logic_vector( 15 downto 0 ); -- øèíà äàííûõ
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cmd : in bl_cmd; -- êîìàíäà
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bx_irq : out std_logic; -- 1 - ïðåðûâàíèå îò òåòðàäû
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bx_drq : out bl_drq; -- çàïðîñ DMA
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status : out std_logic_vector( 15 downto 0 ); -- ðåãèñòð STATUS
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-- Óïðàâëåíèå
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mode0 : out std_logic_vector( 15 downto 0 ); -- ðåãèñòðû òåòðàäû
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fdiv : out std_logic_vector( 15 downto 0 );
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fdiv_we : out std_logic; -- 1 - â ðåãèñòðå FDIV íîâîå çíà÷åíèå
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fmode : out std_logic_vector( 15 downto 0 );
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stmode : out std_logic_vector( 15 downto 0 );
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cnt0 : out std_logic_vector( 15 downto 0 );
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cnt1 : out std_logic_vector( 15 downto 0 );
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cnt2 : out std_logic_vector( 15 downto 0 );
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mode1 : out std_logic_vector( 15 downto 0 );
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mode2 : out std_logic_vector( 15 downto 0 );
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mode3 : out std_logic_vector( 15 downto 0 );
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sflag_pae : out std_logic_vector( 15 downto 0 );
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sflag_paf : out std_logic_vector( 15 downto 0 );
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prt_mode : out std_logic_vector( 15 downto 0 );
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tl_mode : out std_logic_vector( 15 downto 0 );
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chan1 : out std_logic_vector( 1 downto 0 );
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format : out std_logic;
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rst : out std_logic; -- 0 - ñáðîñ òåòðàäû
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fifo_rst : out std_logic; -- 0 - ñáðîñ FIFO
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prt_wr_start: in std_logic:='1' -- 1 - íàñòóïèëî ñîáûòèå ñòàðòà â ðåæèìå ïðåòðèããåðà
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);
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end component;
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end package cl_chn_v4_pkg;
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library ieee;
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use ieee.std_logic_1164.all;
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use work.adm2_pkg.all;
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entity cl_chn_v4 is
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generic (
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-- 2 - out - äëÿ òåòðàäû âûâîäà
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-- 1 - in - äëÿ òåòðàäû ââîäà
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chn_type : integer
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);
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port(
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reset : in std_logic; -- 0 - îáùèé ñáðîñ
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clk : in std_logic; -- òàêòîâàÿ ÷àñòîòà
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-- Ôëàãè
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cmd_rdy : in std_logic; -- 1 - ãîòîâíîñòü òåòðàäû
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rdy : in std_logic; -- 1 - ãîòîâíîñòü FIFO
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fifo_flag : in bl_fifo_flag; -- ôëàãè FIFO
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st9 : in std_logic:='0'; -- Ðàçðÿäû ðåãèñòðà STATUS
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st10 : in std_logic:='0';
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st11 : in std_logic:='0';
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st12 : in std_logic:='0';
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st13 : in std_logic:='0';
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st14 : in std_logic:='0';
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st15 : in std_logic:='0';
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-- Òåòðàäà
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data_in : in std_logic_vector( 15 downto 0 ); -- øèíà äàííûõ
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cmd : in bl_cmd; -- êîìàíäà
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bx_irq : out std_logic; -- 1 - ïðåðûâàíèå îò òåòðàäû
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bx_drq : out bl_drq; -- çàïðîñ DMA
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status : out std_logic_vector( 15 downto 0 ); -- ðåãèñòð STATUS
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-- Óïðàâëåíèå
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mode0 : out std_logic_vector( 15 downto 0 ); -- ðåãèñòðû òåòðàäû
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fdiv : out std_logic_vector( 15 downto 0 );
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fdiv_we : out std_logic; -- 1 - â ðåãèñòðå FDIV íîâîå çíà÷åíèå
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fmode : out std_logic_vector( 15 downto 0 );
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stmode : out std_logic_vector( 15 downto 0 );
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cnt0 : out std_logic_vector( 15 downto 0 );
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cnt1 : out std_logic_vector( 15 downto 0 );
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cnt2 : out std_logic_vector( 15 downto 0 );
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mode1 : out std_logic_vector( 15 downto 0 );
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mode2 : out std_logic_vector( 15 downto 0 );
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mode3 : out std_logic_vector( 15 downto 0 );
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sflag_pae : out std_logic_vector( 15 downto 0 );
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sflag_paf : out std_logic_vector( 15 downto 0 );
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prt_mode : out std_logic_vector( 15 downto 0 );
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tl_mode : out std_logic_vector( 15 downto 0 );
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chan1 : out std_logic_vector( 1 downto 0 );
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format : out std_logic;
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rst : out std_logic; -- 0 - ñáðîñ òåòðàäû
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fifo_rst : out std_logic; -- 0 - ñáðîñ FIFO
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prt_wr_start: in std_logic:='1' -- 1 - íàñòóïèëî ñîáûòèå ñòàðòà â ðåæèìå ïðåòðèããåðà
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);
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end cl_chn_v4;
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architecture cl_chn_v4 of cl_chn_v4 is
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signal c_mode0, c_mask, c_inv, c_mode1, c_mode2, c_flag, c_irq : std_logic_vector( 15 downto 0 );
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signal c_fmode, c_fdiv, c_stmode, c_cnt0, c_cnt1, c_cnt2: std_logic_vector( 15 downto 0 );
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signal c_mode3, c_sflag : std_logic_vector( 15 downto 0 );
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signal c_sflag_pae, c_sflag_paf, c_prt_mode,c_tl_mode : std_logic_vector( 15 downto 0 );
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signal c_status : std_logic_vector( 15 downto 0 );
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signal c_drq_en : std_logic;
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signal c_rst : std_logic; -- 0 - ñáðîñ òåòðàäû
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signal drq_req : std_logic;
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begin
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mode0<=c_mode0;
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mode1<=c_mode1;
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mode2<=c_mode2;
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mode3<=c_mode3;
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status<=c_status;
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fmode<=c_fmode;
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fdiv<=c_fdiv;
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stmode<=c_stmode;
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cnt0<=c_cnt0;
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cnt1<=c_cnt1;
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cnt2<=c_cnt2;
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sflag_pae <= c_sflag_pae;
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sflag_paf <= c_sflag_paf;
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prt_mode <= c_prt_mode;
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tl_mode <= c_tl_mode;
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pr_mode0: process( reset, clk ) begin
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if( reset='0' ) then
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c_mode0<=(others=>'0');
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elsif( rising_edge( clk ) ) then
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if( cmd.cmd_data_we='1' ) then
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if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
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case cmd.adr( 4 downto 0 ) is
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when "00000" => c_mode0<=data_in;
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when others=>null;
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end case;
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end if;
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end if;
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end if;
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end process;
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pr_reg: process( c_rst, clk )
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variable v: std_logic;
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begin
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if( c_rst='0' ) then
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c_mode1<=(others=>'0');
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c_mode2<=(others=>'0');
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c_mode3<=(others=>'0');
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c_sflag_pae<=(others=>'0');
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c_sflag_paf<=(others=>'0');
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c_prt_mode<=(others=>'0');
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c_tl_mode<=(others=>'0');
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c_mask<=(others=>'0');
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c_inv<=(others=>'0');
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c_fmode<=(others=>'0');
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c_fdiv <=(others=>'0');
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c_stmode<=(others=>'0');
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c_cnt0<=(others=>'0');
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c_cnt1<=(others=>'0');
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c_cnt2<=(others=>'0');
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chan1<=(others=>'0');
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fdiv_we<='0';
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format <='0';
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elsif( rising_edge( clk ) ) then
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v:='0';
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if( cmd.cmd_data_we='1' ) then
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if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
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case cmd.adr( 4 downto 0 ) is
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when "00001" => c_mask<=data_in;
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when "00010" => c_inv<=data_in;
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when "00011" => c_fmode<=data_in;
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when "00100" => c_fdiv<=data_in; v:='1';
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when "00101" => c_stmode<=data_in;
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when "00110" => c_cnt0<=data_in;
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when "00111" => c_cnt1<=data_in;
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when "01000" => c_cnt2<=data_in;
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when "01001" => c_mode1<=data_in;
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when "01010" => c_mode2<=data_in;
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when "01011" => c_mode3<=data_in;
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when "01100" => c_sflag_pae<=data_in;
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when "01101" => c_sflag_paf<=data_in;
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when "01110" => c_prt_mode<=data_in;
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when "01111" => c_tl_mode<=data_in;
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when "10000" => chan1 <= data_in( 1 downto 0 );
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when "10010" => format <= data_in( 0 );
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when others=>null;
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end case;
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end if;
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end if;
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fdiv_we<=v;
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end if;
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end process;
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pr_status: process( clk ) begin
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if( rising_edge( clk ) ) then
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c_status(0)<=cmd_rdy;
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c_status(1)<=rdy and prt_wr_start;
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c_status(2)<=fifo_flag.ef;
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c_status(3)<=fifo_flag.pae;
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c_status(4)<=fifo_flag.hf;
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c_status(5)<=fifo_flag.paf;
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c_status(6)<=fifo_flag.ff;
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c_status(7)<=fifo_flag.ovr;
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c_status(8)<=fifo_flag.und;
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c_status(9)<=st9;
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c_status(10)<=st10;
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c_status(11)<=st11;
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c_status(12)<=st12;
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c_status(13)<=st13;
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c_status(14)<=st14;
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c_status(15)<=st15;
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end if;
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end process;
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c_flag<=c_status xor c_inv;
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c_irq<= c_flag and c_mask;
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pr_irq: process( c_irq, clk )
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variable v: std_logic;
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begin
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v:='0';
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for i in 0 to 15 loop
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v:=v or c_irq( i );
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end loop;
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if( rising_edge( clk ) ) then
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bx_irq<=v and c_mode0(2);
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end if;
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end process;
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c_rst<=reset and ( not c_mode0(0) );
|
308 |
|
|
rst <= c_rst after 1 ns when rising_edge( clk );
|
309 |
|
|
|
310 |
|
|
fifo_rst<=reset and ( not c_mode0(0) ) and ( not c_mode0(1) ) after 1 ns when rising_edge( clk );
|
311 |
|
|
|
312 |
|
|
c_drq_en<=c_mode0( 3 ) and prt_wr_start;
|
313 |
|
|
|
314 |
|
|
bx_drq.en<=c_drq_en;
|
315 |
|
|
|
316 |
|
|
gen_out: if chn_type=2 generate
|
317 |
|
|
|
318 |
|
|
pr_bx_drq: process( c_mode0, fifo_flag, c_drq_en, rdy )
|
319 |
|
|
|
320 |
|
|
begin
|
321 |
|
|
case c_mode0( 13 downto 12 ) is
|
322 |
|
|
when "00" => drq_req <= fifo_flag.paf and c_drq_en; -- PAF = 1
|
323 |
|
|
when "01" => drq_req <= rdy and c_drq_en; -- RDY = 1
|
324 |
|
|
when "10" => drq_req <= fifo_flag.hf and c_drq_en; -- HF = 1
|
325 |
|
|
when others => drq_req<='0';
|
326 |
|
|
end case;
|
327 |
|
|
end process;
|
328 |
|
|
|
329 |
|
|
bx_drq.ack <= cmd.data_we and c_drq_en;
|
330 |
|
|
|
331 |
|
|
end generate;
|
332 |
|
|
|
333 |
|
|
gen_in: if chn_type=1 generate
|
334 |
|
|
|
335 |
|
|
pr_bx_drq: process( c_mode0, fifo_flag, c_drq_en, rdy )
|
336 |
|
|
|
337 |
|
|
begin
|
338 |
|
|
case c_mode0( 13 downto 12 ) is
|
339 |
|
|
when "00" => drq_req <= fifo_flag.pae and c_drq_en; -- PAE = 1
|
340 |
|
|
when "01" => drq_req <= rdy and c_drq_en; -- RDY = 1
|
341 |
|
|
when "10" => drq_req <= ( not fifo_flag.hf ) and c_drq_en; -- HF = 0
|
342 |
|
|
when others => drq_req<='0';
|
343 |
|
|
end case;
|
344 |
|
|
end process;
|
345 |
|
|
|
346 |
|
|
bx_drq.ack <= ( not cmd.data_cs ) and c_drq_en;
|
347 |
|
|
|
348 |
|
|
end generate;
|
349 |
|
|
|
350 |
|
|
bx_drq.req <= drq_req when c_prt_mode(0)='0' or c_prt_mode(1)='1'
|
351 |
|
|
else drq_req and prt_wr_start;
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
end cl_chn_v4;
|