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[/] [pcie_ds_dma/] [trunk/] [core/] [adm/] [main/] [cl_test_check.vhd] - Blame information for rev 2

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1 2 dsmv
-------------------------------------------------------------------------------
2
--
3
-- Title       : cl_test_check
4
-- Author      : Dmitry Smekhov
5
-- Company     : Instrumental Systems
6
-- E-mail      : dsmv@insys.ru
7
--
8
-- Version     : 1.0
9
--
10
-------------------------------------------------------------------------------
11
--
12
-- Description :        Óçåë ïðîâåðêè âõîäíîãî ïîòîêà
13
--                              
14
--              Òåñòîâàÿ ïîñëåäîâàòåëüíîñòü ïðåäñòàâëÿåò ñîáîé íàáîð áëîêîâ. 
15
--              Ðàçìåð áëîêà çàäà¸òñÿ êðàòíûì ñòðàíèöû ðàçìåðîì 4 êèëîáàéòà 
16
--              (512 ñëîâ ïî 64 áèòà)
17
--              Ïåðâîå 64-õ ðàçðÿäíîå ñëîâî â áëîêå ñîäåðæèò ñèãíàòóðó è ïîðÿäêîâûé íîìåð.       
18
--                  31..0  - ñèãíàòóðà 0xA5A50123
19
--                      63..32 - ïîðÿäêîâûé íîìåð áëîêà
20
--
21
--              Ñîäåðæèìîå áëîêà çàâèñèò îò åãî ïîðÿäêîâîãî íîìåðà â ïîñëåäîâàòåëüíîñòè.  
22
--
23
--              Ñîäåðæèìîå áëîêà:
24
--              0 - Áåãóùàÿ åäèíèöà ïî 64-ì ðàçðÿäàì
25
--              1 - Áåãóùèé íîëü ïî 64-ì ðàçðÿäàì
26
--              2 - Áåãóùàÿ åäèíèöà ñ èíâåðñèåé ïî 64-ì ðàçðÿäàì
27
---                     ׸òíûå íîìåðà ñëîâ - áåãóùàÿ åäèíèöà ïî 64-ì ðàçðÿäàì
28
--                      Íå÷¸òíûå íîìåðà - èíâåðñèÿ ïðåäûäóùåãî ñëîâà             
29
--              3 - Áåãóùàÿ åäèíèöà â áëîêå
30
--                      Íîìåð ñëîâà ñðàâíèâàåòñÿ ñ íîìåðîì áëîêà (ñðàâíèâàþòñÿ âîñåìü ìëàäøèé ðàçðÿäîâ)
31
--                      Ïðè ñîâïàäåíèè - â ñëîâî çàïèñûâàåòñÿ áåãóùàÿ 1.
32
--                      Îñòàëüíûå ñëîâà - çíà÷åíèå íîëü.
33
--              4 - Áåãóùèé íîëü ñ èíâåðñèåé ïî 64-ì ðàçðÿäàì
34
--                      ׸òíûå íîìåðà - áåãóùèé íîëü ïî 64-ì ðàçðÿäàì
35
--                      Íå÷¸òíûå íîìåðà - èíâåðñèÿ ïðåäûäóùåãî ñëîâà             
36
--              5 - Áåãóùèé íîëü à â áëîêå
37
--                      Íîìåð ñëîâà ñðàâíèâàåòñÿ ñ íîìåðîì áëîêà (ñðàâíèâàþòñÿ âîñåìü ìëàäøèé ðàçðÿäîâ)
38
--                      Ïðè ñîâïàäåíèè - â ñëîâî çàïèñûâàåòñÿ áåãóùèé 0.
39
--                      Îñòàëüíûå ñëîâà - çíà÷åíèå 0xFFFFFFFFFFFFFFFF.
40
--              6,7 - Ñ÷¸ò÷èê ïî 64-ì ðàçðÿäàì
41
--                      ׸òíûå íîìåðà - çíà÷åíèå ñ÷¸ò÷èêà
42
--                      Íå÷¸òíûå íîìåðà - èíâåðñèÿ ïðåäûäóùåãî ñëîâà
43
--              8,9 - Ïñåâäîñëó÷àéíàÿ ïîñëåäîâàòåëüíîñòü
44
--                      Ôîðìèðóåòñÿ Ì-ïîñëåäîâàòåëüíîñòü ïî 64 ðàçðÿäàì.
45
--                      Íà÷àëüíîå çíà÷åíèå - 1
46
--                      Ñëîâî ôîðìèðóåòñÿ ñäâèãîì íà îäèí ðàçðÿä âïðàâî.
47
--                       ìëàäøèé ðàçðÿä ñëîâà çàïèñûâàåòñÿ çíà÷åíèå x[63] xor x[62]
48
--                                                                                                                              
49
--
50
--              Äëÿ ðåæèìà ñ÷¸ò÷èêà è ïñåâäîñëó÷àéíîé ïîñëåäîâàòåëüíîñòè íà÷àëüíîå çíà÷åíèå
51
--              ôîðìèðóåòñÿ ïðè èíèöèàëèçàöèè òåñòîâîé ïîñëåäîâàòåëüíîñòè.
52
--              Äëÿ îñòàëüíûõ ðåæèìîâ - ïðè èíèöèàëèçàöèè ïðîâåðêè áëîêà
53
--
54
--
55
--              Ðåãèñòð test_check_ctrl
56
--                         
57
--                              0 - 1 ñáðîñ óçëà
58
--                              5 - 1 ñòàðò ïðè¸ìà äàííûõ
59
--                              7 - 1 ôèêñèðîâàííûé òèï áëîêà
60
--                              11..8 - íîìåð áëîêà ïðè test_check_ctrl[7]=1
61
--                              
62
 
63
-------------------------------------------------------------------------------
64
--
65
-- Version     1.0  
66
--
67
-------------------------------------------------------------------------------
68
 
69
 
70
 
71
 
72
library ieee;
73
use ieee.std_logic_1164.all;
74
 
75
package cl_test_check_pkg is
76
 
77
component cl_test_check is
78
        port(
79
 
80
                ---- Global ----
81
                reset           : in std_logic;         -- 0 - ñáðîñ
82
                clk                     : in std_logic;         -- òàêòîâàÿ ÷àñòîòà
83
 
84
                ---- DIO_OUT ----
85
                do_clk          : in  std_logic;        -- òàêòîâàÿ ÷àñòîòà ÷òåíèÿ èç FIFO
86
                do_data         : in  std_logic_vector( 63 downto 0 );
87
                do_data_en      : in  std_logic;        -- 1 - ïåðåäà÷à äàííûõ èç dio_out
88
 
89
 
90
                ---- Óïðàâëåíèå ----
91
                test_check_ctrl : in  std_logic_vector( 15 downto 0 );
92
                test_check_size : in  std_logic_vector( 15 downto 0 );    -- ðàçìåð â áëîêàõ ïî 512x64 (4096 áàéò)
93
                test_check_bl_rd        : out std_logic_vector( 31 downto 0 );
94
                test_check_bl_ok        : out std_logic_vector( 31 downto 0 );
95
                test_check_bl_err       : out std_logic_vector( 31 downto 0 );
96
                test_check_error        : out std_logic_vector( 31 downto 0 );
97
                test_check_err_adr      : in  std_logic_vector( 15 downto 0 );
98
                test_check_err_data: out std_logic_vector( 15 downto 0 )
99
 
100
        );
101
end component;
102
 
103
end package;
104
 
105
 
106
library ieee;
107
use ieee.std_logic_1164.all;
108
use ieee.std_logic_arith.all;
109
use ieee.std_logic_unsigned.all;
110
 
111
library unisim;
112
use unisim.vcomponents.all;
113
 
114
library work;
115
use work.adm2_pkg.all;
116
 
117
entity cl_test_check is
118
        port(
119
 
120
                ---- Global ----
121
                reset           : in std_logic;         -- 0 - ñáðîñ
122
                clk                     : in std_logic;         -- òàêòîâàÿ ÷àñòîòà
123
 
124
                ---- DIO_OUT ----
125
                do_clk          : in  std_logic;        -- òàêòîâàÿ ÷àñòîòà ÷òåíèÿ èç FIFO
126
                do_data         : in  std_logic_vector( 63 downto 0 );
127
                do_data_en      : in  std_logic;        -- 1 - ïåðåäà÷à äàííûõ èç dio_out
128
 
129
 
130
                ---- Óïðàâëåíèå ----
131
                test_check_ctrl : in  std_logic_vector( 15 downto 0 );
132
                test_check_size : in  std_logic_vector( 15 downto 0 );    -- ðàçìåð â áëîêàõ ïî 512x64 (4096 áàéò)
133
                test_check_bl_rd        : out std_logic_vector( 31 downto 0 );
134
                test_check_bl_ok        : out std_logic_vector( 31 downto 0 );
135
                test_check_bl_err       : out std_logic_vector( 31 downto 0 );
136
                test_check_error        : out std_logic_vector( 31 downto 0 );
137
                test_check_err_adr      : in  std_logic_vector( 15 downto 0 );
138
                test_check_err_data: out std_logic_vector( 15 downto 0 )
139
 
140
        );
141
end cl_test_check;
142
 
143
 
144
architecture cl_test_check of cl_test_check is
145
 
146
signal  block_rd                : std_logic_vector( 31 downto 0 );
147
signal  block_ok                : std_logic_vector( 31 downto 0 );
148
signal  block_err               : std_logic_vector( 31 downto 0 );
149
signal  total_err               : std_logic_vector( 31 downto 0 );
150
 
151
signal  data_expect             : std_logic_vector( 63 downto 0 );
152
 
153
signal  cnt1                    : std_logic_vector( 24 downto 0 );
154
signal  cnt1_z                  : std_logic;
155
signal  cnt1_eq                 : std_logic;
156
 
157
signal  rst                             : std_logic;
158
signal  data_en                 : std_logic;    -- 1 - ïðè¸ì ñëîâà äàííûõ  
159
signal  data_en_z               : std_logic;
160
signal  do_data_z               : std_logic_vector( 63 downto 0 );
161
 
162
signal  data_ex0                : std_logic_vector( 63 downto 0 );
163
signal  data_ex1                : std_logic_vector( 63 downto 0 );
164
signal  data_ex2                : std_logic_vector( 63 downto 0 );
165
signal  data_ex3                : std_logic_vector( 63 downto 0 );
166
signal  data_ex4                : std_logic_vector( 63 downto 0 );
167
signal  data_ex5                : std_logic_vector( 63 downto 0 );
168
 
169
 
170
signal  block_mode              : std_logic_vector( 3 downto 0 );
171
signal  word_error              : std_logic;
172
signal  flag_error              : std_logic;    -- 1 - ïðèçíàê îøèáêè ïðè ïðè¸ìà áëîêà
173
signal  flag_error_clr  : std_logic;    -- 1 - ñáðîñ flag_error
174
 
175
signal  data_error              : std_logic_vector( 191 downto 0 );
176
signal  data_error_wr   : std_logic;
177
signal  data_error_wr1  : std_logic;
178
signal  data_error_ovr  : std_logic;
179
signal  data_error_out  : std_logic_vector( 191 downto 0 );
180
signal  err_data                : std_logic_vector( 15 downto 0 );
181
 
182
signal  block_ok_en             : std_logic;
183
 
184
begin
185
 
186
pr_cnt1: process( do_clk ) begin
187
        if( rising_edge( do_clk ) ) then
188
                if( rst='0' or (cnt1_eq='1' and data_en='1') ) then
189
                        cnt1( 24 downto 0 )   <= (others=>'0') after 1 ns;
190
                elsif( data_en='1' ) then
191
                        cnt1 <= cnt1 + 1 after 1 ns;
192
                end if;
193
        end if;
194
end process;
195
 
196
pr_cnt1_z: process( do_clk ) begin
197
        if( rising_edge( do_clk ) ) then
198
 
199
                if( rst='0' ) then
200
                        cnt1_z <= '1' after 1 ns;
201
                        cnt1_eq <= '0' after 1 ns;
202
                elsif( data_en='1' ) then
203
 
204
                        if( cnt1_eq='1' ) then
205
                                cnt1_z <= '1' after 1 ns;
206
                        else
207
                                cnt1_z <= '0' after 1 ns;
208
                        end if;
209
 
210
                        if( cnt1( 24 downto 9 )=test_check_size-1 and cnt1( 8 downto 0 )="111111110" ) then
211
                                cnt1_eq <= '1' after 1 ns;
212
                        else
213
                                cnt1_eq <= '0' after 1 ns;
214
                        end if;
215
                end if;
216
 
217
        end if;
218
end process;
219
 
220
 
221
 
222
data_en <= do_data_en;
223
 
224
rst <= reset and not test_check_ctrl(0);
225
 
226
pr_block_mode: process( do_clk ) begin
227
        if( rising_edge( do_clk ) ) then
228
                if( rst='0' ) then
229
                        block_mode <= "0000" after 1 ns;
230
                elsif( test_check_ctrl(7)='1' ) then
231
                        block_mode <= test_check_ctrl( 11 downto 8 ) after 1 ns;
232
                elsif( data_en='1' and cnt1_eq='1' ) then
233
                                if( block_mode="1001" ) then
234
                                        block_mode <= "0000" after 1 ns;
235
                                else
236
                                        block_mode <= block_mode + 1 after 1 ns;
237
                                end if;
238
                end if;
239
        end if;
240
end process;
241
 
242
pr_block_rd: process( do_clk ) begin
243
        if( rising_edge( do_clk ) ) then
244
                if( rst='0' ) then
245
                        block_rd <= (others=>'0') after 1 ns;
246
                elsif( data_en='1' and cnt1_eq='1' ) then
247
                        block_rd <= block_rd + 1 after 1 ns;
248
                end if;
249
        end if;
250
end process;
251
 
252
 
253
pr_data_expect: process( do_clk ) begin
254
        if( rising_edge( do_clk ) ) then
255
          if( rst='0' ) then
256
                  data_ex4 <= (others=>'0') after 1 ns;
257
                  data_ex5 <= (0=>'1', others=>'0') after 1 ns;
258
                  data_ex0 <= x"0000000000000001" after 1 ns;
259
          elsif( data_en='1' ) then
260
                if( cnt1_z='1' ) then
261
                        data_expect( 31 downto 0 ) <= x"A5A50123" after 1 ns;
262
                        data_expect( 63 downto 32 ) <= block_rd after 1 ns;
263
                        case( block_mode( 3 downto 0 ) ) is
264
                          when "0000" => -- Áåãóùàÿ 1 ïî 64-ì ðàçðÿäàì
265
                                data_ex0 <= x"0000000000000001" after 1 ns;
266
                          when "0001" => -- Áåãóùèé 0 ïî 64-ì ðàçðÿäàì
267
                                data_ex0 <= not x"0000000000000001" after 1 ns;
268
                          when "0010" => -- Áåãóùàÿ 1 ñ èíâåðñèåé  ïî 64-ì ðàçðÿäàì
269
                                data_ex1 <= x"0000000000000001" after 1 ns;
270
                          when "0011" => -- Áåãóùèé 0 ñ èíâåðñèåé  ïî 64-ì ðàçðÿäàì
271
                                data_ex1 <= not x"0000000000000001" after 1 ns;
272
                          when "0100" => -- Áåãóùàÿ 1 â áëîêå 0
273
                                data_ex2 <= x"0000000000000001" after 1 ns;
274
                                data_ex3 <= (others=>'0');
275
                          when "0101" => -- Áåãóùèé 0 â áëîêå 1
276
                                data_ex2 <= not x"0000000000000001" after 1 ns;
277
                                data_ex3 <= (others=>'1') after 1 ns;
278
 
279
                          when others=> null;
280
                        end case;
281
                else
282
                        case( block_mode( 3 downto 0 ) )is
283
                          when "0000" | "0001" =>
284
                                data_expect <= data_ex0 after 1 ns;
285
                                data_ex0( 63 downto 1 ) <= data_ex0( 62 downto 0 ) after  1 ns;
286
                                data_ex0( 0 ) <= data_ex0( 63 ) after 1 ns;
287
 
288
                          when "0010" | "0011" => -- Áåãóùèé 0 ñ èíâåðñèåé  ïî 32-ì ðàçðÿäàì
289
--                        when "0011" => -- Áåãóùèé 0 ñ èíâåðñèåé  ïî 64-ì ðàçðÿäàì
290
                                if( cnt1(0)='0' ) then
291
                                        data_expect <= data_ex1 after 1 ns;
292
                                else
293
                                        data_expect <= not data_ex1 after 1 ns;
294
                                        data_ex1( 63 downto 1 ) <= data_ex1( 62 downto 0 ) after  1 ns;
295
                                        data_ex1( 0 ) <= data_ex1( 63 ) after 1 ns;
296
                                end if;
297
                          when "0100" | "0101" => -- Áåãóùèé 0 â áëîêå 1
298
--                        when "0111" => -- Áåãóùèé 1 â áëîêå 0
299
                                if( cnt1( 7 downto 0 )=block_rd( 7 downto 0 ) )then
300
                                        data_expect <= data_ex2 after 1 ns;
301
                                        data_ex2( 63 downto 1 ) <= data_ex2( 62 downto 0 ) after  1 ns;
302
                                        data_ex2( 0 ) <= data_ex2( 63 ) after 1 ns;
303
                                else
304
                                        data_expect <= data_ex3 after 1 ns;
305
                                end if;
306
 
307
                          when "0110" | "0111" => -- Ñ÷¸ò÷èê 
308
                            if( cnt1(0)='0' ) then
309
                                        data_expect <= data_ex4 after 1 ns;
310
                                else
311
                                        data_expect <= not data_ex4 after 1 ns;
312
--                                      data_ex4 <= data_ex4 + x"0000000000000001";
313
                                        data_ex4(31 downto 0) <= data_ex4(31 downto 0) + 1;
314
                                        if (data_ex4(31 downto 0)=x"FFFFFFFF") then
315
                                                data_ex4(63 downto 32) <= data_ex4(63 downto 32) + 1;
316
                                        end if;
317
                                end if;
318
 
319
                          when "1000" | "1001" => -- Ïñåâäîñëó÷àéíàÿ ïîñëåäîâàòåëüíîñòü          
320
                                        data_expect <= data_ex5 after 1 ns;
321
                                        data_ex5( 63 downto 1 ) <= data_ex5( 62 downto 0 ) after 1 ns;
322
                                        --data_ex5( 0 ) <= data_ex5( 63 ) xor data_ex5(62) after 1 ns;
323
                                        data_ex5( 0 ) <= data_ex5( 63 ) xor data_ex5(62) xor data_ex5(60) xor data_ex5(59) after 1 ns;
324
                          when others=> null;
325
                        end case;
326
                end if;
327
          end if;
328
        end if;
329
end process;
330
 
331
 
332
 
333
do_data_z <= do_data after 1 ns when rising_edge( do_clk );
334
data_en_z <= data_en after 1 ns when rising_edge( do_clk );
335
 
336
word_error <= '1' when do_data_z /= data_expect else '0';
337
 
338
pr_total_err: process( do_clk ) begin
339
        if( rising_edge( do_clk ) ) then
340
                if( rst='0' ) then
341
                        total_err <= (others=>'0') after 1 ns;
342
                elsif( data_en_z='1' and word_error='1' and total_err/=x"FFFFFFFF" ) then
343
                        total_err <= total_err + 1 after 1 ns;
344
                end if;
345
        end if;
346
end process;
347
 
348
pr_flag_error_clr: process( do_clk ) begin
349
        if( rising_edge( do_clk ) ) then
350
                if( rst='0' ) then
351
                        flag_error_clr <= '0' after 1 ns;
352
                elsif(  cnt1_z='1' and data_en='1' ) then
353
                        flag_error_clr <= '1' after 1 ns;
354
                else
355
                        flag_error_clr <= '0' after 1 ns;
356
                end if;
357
        end if;
358
end process;
359
 
360
 
361
pr_flag_error: process( do_clk ) begin
362
        if( rising_edge( do_clk ) ) then
363
                if( rst='0' ) then
364
                        flag_error <= '0' after 1 ns;
365
                elsif( data_en_z='1' and word_error='1' ) then
366
                        flag_error <= '1' after 1 ns;
367
                elsif( flag_error_clr='1' ) then
368
                        flag_error <= '0' after 1 ns;
369
                end if;
370
        end if;
371
end process;
372
 
373
 
374
data_error_wr <= data_en_z and word_error;
375
 
376
data_error( 63 downto 0 ) <= do_data_z;
377
data_error( 127 downto 64 ) <= data_expect;
378
data_error( 152 downto 128 ) <= cnt1 after 1 ns when rising_edge( do_clk );
379
data_error( 159 downto 153 ) <= (others=>'0');
380
data_error( 191 downto 160 ) <= block_rd after 1 ns when rising_edge( do_clk );
381
 
382
pr_data_error_ovr: process( do_clk ) begin
383
        if( rising_edge( do_clk ) ) then
384
                if( rst='0' ) then
385
                        data_error_ovr <= '0' after 1 ns;
386
                elsif( data_error_wr='1' and total_err( 3 downto 0 )="1111" ) then
387
                        data_error_ovr <= '1' after 1 ns;
388
                end if;
389
        end if;
390
end process;
391
 
392
data_error_wr1 <= data_error_wr and not data_error_ovr;
393
 
394
pr_block_ok: process( do_clk ) begin
395
        if( rising_edge( do_clk ) ) then
396
                if( rst='0' ) then
397
                        block_ok <= (others=>'0') after 1 ns;
398
                        block_err <= (others=>'0' ) after 1 ns;
399
                elsif( block_ok_en='1' ) then
400
                        if( flag_error_clr='1' and flag_error='0' ) then
401
                                block_ok <= block_ok + 1 after 1 ns;
402
                        end if;
403
                        if( flag_error_clr='1' and flag_error='1' ) then
404
                                block_err <= block_err + 1 after 1 ns;
405
                        end if;
406
                end if;
407
        end if;
408
end process;
409
 
410
pr_block_ok_en: process( clk ) begin
411
        if( rising_edge( clk ) ) then
412
                if( rst='0' ) then
413
                        block_ok_en <= '0' after 1 ns;
414
                elsif( cnt1_eq='1' ) then
415
                        block_ok_en <= '1' after 1 ns;
416
                end if;
417
        end if;
418
end process;
419
 
420
 
421
gen_data_error: for ii in 0 to 191 generate
422
 
423
ram0:   ram16x1d
424
                port map(
425
                        we      => data_error_wr1,
426
                        d       => data_error( ii ),
427
                        wclk => do_clk,
428
                        a0      => total_err( 0 ),
429
                        a1      => total_err( 1 ),
430
                        a2      => total_err( 2 ),
431
                        a3      => total_err( 3 ),
432
                        --spo   => data_out( 0 ),
433
                        dpra0 => test_check_err_adr( 4 ),
434
                        dpra1 => test_check_err_adr( 5 ),
435
                        dpra2 => test_check_err_adr( 6 ),
436
                        dpra3 => test_check_err_adr( 7 ),
437
                        dpo       => data_error_out( ii )
438
                );
439
 
440
end generate;
441
 
442
err_data <=                     data_error_out( 15 downto 0 )   when test_check_err_adr( 3 downto 0 )="0000" else
443
                                                data_error_out( 31 downto 16 )   when test_check_err_adr( 3 downto 0 )="0001" else
444
                                                data_error_out( 47 downto 32 )   when test_check_err_adr( 3 downto 0 )="0010" else
445
                                                data_error_out( 63 downto 48 )   when test_check_err_adr( 3 downto 0 )="0011" else
446
                                                data_error_out( 79 downto 64 )   when test_check_err_adr( 3 downto 0 )="0100" else
447
                                                data_error_out( 95 downto 80 )   when test_check_err_adr( 3 downto 0 )="0101" else
448
                                                data_error_out( 111 downto 96 )  when test_check_err_adr( 3 downto 0 )="0110" else
449
                                                data_error_out( 127 downto 112 ) when test_check_err_adr( 3 downto 0 )="0111" else
450
                                                data_error_out( 143 downto 128 ) when test_check_err_adr( 3 downto 0 )="1000" else
451
                                                data_error_out( 159 downto 144 ) when test_check_err_adr( 3 downto 0 )="1001" else
452
                                                data_error_out( 175 downto 160 ) when test_check_err_adr( 3 downto 0 )="1010" else
453
                                                data_error_out( 191 downto 176 ) when test_check_err_adr( 3 downto 0 )="1011" else
454
                                                (others=>'-');
455
 
456
 
457
test_check_err_data <= err_data after 1 ns when rising_edge( clk );
458
 
459
 
460
test_check_bl_rd        <= block_rd;
461
test_check_bl_ok        <= block_ok;
462
test_check_bl_err       <= block_err;
463
test_check_error        <= total_err;
464
 
465
 
466
end cl_test_check;
467
 
468
 

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