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[/] [pcie_ds_dma/] [trunk/] [core/] [adm/] [main/] [ctrl_thdac.vhd] - Blame information for rev 2

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1 2 dsmv 
---------------------------------------------------------------------------------------------------
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--
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-- Title       : ctrl_thdac
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-- Design      : ADM2
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-- Author      : Ilya Ivanov
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-- Company     : Instrumental System
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--
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-- Version     : 1.0
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---------------------------------------------------------------------------------------------------
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--
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-- Description :  Σοπΰβλενθε ΘΟΝ
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--
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---------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.std_logic_unsigned.all ;
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entity ctrl_thdac is
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         port(
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                 reset : in STD_LOGIC;
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                 clk : in STD_LOGIC;
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                 start : in STD_LOGIC;
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                 data_dac : in STD_LOGIC_VECTOR(11 downto 0);
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                 clkDAC_out : out STD_LOGIC;
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                 ld : out STD_LOGIC;
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                 ready : out STD_LOGIC;
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                 thrs  : out STD_LOGIC;
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                 sdo_dac : out STD_LOGIC
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             );
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end ctrl_thdac;
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architecture ctrl_thdac of ctrl_thdac is
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signal counter : std_logic_vector(5 downto 0) ;          -- counter for reset
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signal counter2 : std_logic_vector(7 downto 0) ;         -- counter for reset
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signal counter_data : std_logic_vector(5 downto 0) ;             -- counter for reset
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signal l_ready,l_ready2,l_clk:std_logic;
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signal l_data_dac : STD_LOGIC_VECTOR(11 downto 0);
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begin
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thrs<=reset;
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pr_start: process( clk,reset )
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begin
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        if(reset='0') then
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                l_ready<='0';
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        elsif( rising_edge( clk ) ) then
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                if(start='1')then
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                        l_ready<='1';
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                        l_data_dac<=data_dac;
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                elsif(counter_data = "11000")then
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                        l_ready<='0';
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                end if;
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        end if;
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end process;
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pr_count: process( clk,reset )
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begin
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        if(reset='0') then
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                counter <= (others => '0') ;
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                counter_data <= (others => '0') ;
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        elsif( rising_edge( clk ) ) then
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                if(l_ready='1')then
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                        counter <= counter + 1 ;
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                        if (counter = "01010") then
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                                counter <= (others => '0') ;
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                                counter_data <= counter_data + 1 ;
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                        end if;
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                else
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                        counter <= (others => '0') ;
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                        counter_data <= (others => '0') ;
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                end if;
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        end if;
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end process;
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pr_clk_out: process( clk,reset )
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begin
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        if(reset='0') then
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                l_clk<='0';
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        clkDAC_out<='0';
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        elsif( rising_edge( clk ) ) then
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                if(counter = "101")then
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                        l_clk<=not l_clk;
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                end if;
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                clkDAC_out<=l_clk;
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        end if;
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end process;
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--clkDAC_out<=clk;
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pr_data_out: process( clk,reset )
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begin
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        if(reset='0') then
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                sdo_dac<='0';
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        elsif( rising_edge( clk ) ) then
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                if(counter = "00010" )then
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                        if( counter_data="00000")then
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                                sdo_dac<=l_data_dac(11);
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                        elsif( counter_data="00010")then
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                                sdo_dac<=l_data_dac(10);
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                        elsif( counter_data="00100")then
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                                sdo_dac<=l_data_dac(9);
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                        elsif( counter_data="00110")then
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                                sdo_dac<=l_data_dac(8);
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                        elsif( counter_data="01000")then
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                                sdo_dac<=l_data_dac(7);
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                        elsif( counter_data="01010")then
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                                sdo_dac<=l_data_dac(6);
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                        elsif( counter_data="01100")then
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                                sdo_dac<=l_data_dac(5);
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                        elsif( counter_data="01110")then
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                                sdo_dac<=l_data_dac(4);
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                        elsif( counter_data="10000")then
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                                sdo_dac<=l_data_dac(3);
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                        elsif( counter_data="10010")then
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                                sdo_dac<=l_data_dac(2);
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                        elsif( counter_data="10100")then
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                                sdo_dac<=l_data_dac(1);
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                        elsif( counter_data="10110")then
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                                sdo_dac<=l_data_dac(0);
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                        end if;
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                 end if;
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        end if;
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end process;
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pr_count2: process( clk,reset )
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begin
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        if(reset='0') then
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                counter2 <= (others => '0') ;
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        elsif( rising_edge( clk ) ) then
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                if(l_ready2='1')then
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                        counter2 <= counter2 + 1 ;
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                else
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                        counter2 <= (others => '0') ;
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                end if;
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        end if;
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end process;
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pr_ready2: process( clk,reset )
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begin
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        if(reset='0') then
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                l_ready2<='0';
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                ld<='0';
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        elsif( rising_edge( clk ) ) then
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                if(counter_data = "10111")then
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                        l_ready2<='1';
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                elsif(counter2 = "1010")then
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                        ld<='1';
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                elsif(counter2 = "11111")then
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                        ld<='0';
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                elsif(counter2 = "110110")then
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                        l_ready2<='0';
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                end if;
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        end if;
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end process;
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pr_redy: process( clk,reset )
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begin
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        if(reset='0') then
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                ready<='1';
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        elsif( rising_edge( clk ) ) then
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                ready<=not (l_ready or l_ready2);
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        end if;
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end process;
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end ctrl_thdac;

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