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[/] [pcie_ds_dma/] [trunk/] [core/] [adm/] [main/] [trd_main_v8.vhd] - Blame information for rev 2

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1 2 dsmv 
---------------------------------------------------------------------------------------------------
2 
--
3 
-- Title       : trd_main_v8
4 
-- Author      : Dmitry Smekhov
5 
-- Company     : Instrumental System
6 
--
7 
--  Version        : 1.4
8 
--
9 
---------------------------------------------------------------------------------------------------
10 
--
11 
-- Description : Ðåàëèçàöèÿ òåòðàäû MAIN
12 
--
13 
--                              Ìîäèôèêàöèÿ 8 - íå èñïîëüçóþòñÿ ñ÷¸ò÷èêè CNT0, CNT1, CNT2
14 
--                                              Âûõîä cmd_data_out ðåàëèçîâàí íà ìóëüòèïëåêñîðå
15 
--                                              Óçåë íà÷àëüíîãî òåñòèðîâàíèÿ ñáðàñûâàåòñÿ ÷åðåç ñèãíàë ñáðîñà FIFO
16 
--                                              Ïîääåðæèâàåòñÿ òåñòîâûé ðåæèì ðàáîòû SYNX
17 
--
18 
---------------------------------------------------------------------------------------------------
19 
--
20 
--       Ðåãèñòð SYNX
21 
--                      0 - RDY0_OUT
22 
--                      1 - RDY1_OUT
23 
--                      4 - RDY0_OE
24 
--                      5 - RDY1_OE
25 
--                      12 - START_EN_OUT
26 
--                      13 - SYNC0_OUT
27 
--                      14 - ENCODE_OUT
28 
--                      15 - SYNX_TEST_MODE
29 
--
30 
--       Ðåãèñòð SYNX_IN        - àäðåñ 0x202
31 
--                      9  - SN_RDY0
32 
--                      10 - SN_RDY1
33 
--                      11 - SN_START
34 
--                      12 - SN_START_EN
35 
--                      13 - SN_SYNC0
36 
--                      14 - SN_ENCODE          - âõîä òàêòîâîé ÷àñòîû
37 
--                      15 - SYNX_TEST_MODE - çíà÷åíèå óñòàíîâëåííîå â SYNX_TEST_MODE
38 
--
39 
---------------------------------------------------------------------------------------------------
40 
--
41 
--  Version      1.4  10.06.2010
42 
--                       Äîáàâëåíû âõîäû irq è drq äëÿ òåòðàä 8..15
43 
--                       Âõîäû íà÷èíàþò äåéñòâîâàòü ïðè óñòàíîâêå ïàðàìåòðà ext_drq=1
44 
--
45 
--                       Äîáàâëåí ðåãèñòð TEST_MODE - óïðàâëåíèå ðåæèìîì ôîðìèðîâàíèÿ
46 
--                       òåñòîâîé ïîñëåäîâàòåëüíîñòè
47 
--
48 
--
49 
---------------------------------------------------------------------------------------------------
50 
--
51 
--  Version      1.3  26.03.2009
52 
--                       Äîáàâëåí âûõîä çàïðîñà DMA
53 
--
54 
--                       11.05.2010 Äîáàâëåíû òðèããåðû íà âûõîäû reset_out, fifo_rst_out
55 
--
56 
---------------------------------------------------------------------------------------------------
57 
--
58 
--  Version      1.2  06.12.2006
59 
--                       Èñïðàâëåíî ôîðìèðîâàíèå çàïðîñà DMA - çàïðîñ ðàçðåøàåòñÿ ïðè óñòàíîâêå MODE0[3]=1
60 
--                       Èñïðàâëåí ñáðîñ òåñòîâîãî ðåãèñòðà - ñáðîñ ìîæåò ïðîèçâîäèòüñÿ ÷åðåç êîìàíäó ñáðîñà FIFO
61 
--
62 
---------------------------------------------------------------------------------------------------
63 
--
64 
--  Version      1.1  12.12.2005
65 
--                         Óáðàí áóôåð ñ 3-ñîñòîÿíèåì
66 
--
67 
---------------------------------------------------------------------------------------------------
68 
--
69 
--  Version      1.0  25.08.2005
70 
--                         Ñîçäàí èç trd_main_v1  âåðñèè 1.2
71 
--
72 
---------------------------------------------------------------------------------------------------
73 
 
74 
 
75 
library IEEE;
76 
use IEEE.STD_LOGIC_1164.all;
77 
 
78 
use work.adm2_pkg.all;
79 
 
80 
package trd_main_v8_pkg is
81 
 
82 
constant  ID_MAIN               : std_logic_vector( 15 downto 0 ):=x"0001"; -- èäåíòèôèêàòîð òåòðàäû
83 
constant  ID_MODE_MAIN  : std_logic_vector( 15 downto 0 ):=x"0008"; -- ìîäèôèêàòîð òåòðàäû
84 
constant  VER_MAIN              : std_logic_vector( 15 downto 0 ):=x"0104";      -- âåðñèÿ òåòðàäû
85 
constant  RES_MAIN              : std_logic_vector( 15 downto 0 ):=x"0010";      -- ðåñóðñû òåòðàäû
86 
constant  FIFO_MAIN             : std_logic_vector( 15 downto 0 ):=x"0100"; -- ðàçìåð FIFO
87 
constant  FTYPE_MAIN    : std_logic_vector( 15 downto 0 ):=x"0040"; -- øèðèíà FIFO
88 
 
89 
component trd_main_v8 is
90 
        generic(
91 
                sync0_mode      : in integer:=0; -- ðåæèì óïðàâëåíèÿ sync0_out
92 
                                                                                --  0 - ÷åðåç SYNX(13)
93 
                                                                                --  1 - ïðè SYNX(15)='0' - âõîä sn_sync0_in
94 
                                                                                --          ïðè SYNX(15)='1' - ÷åðåç SYNX(13)
95 
 
96 
                ext_drq         : in integer:=0          -- 0 - èñïîëüçóþòñÿ òîëüêî âõîäû b1_drq - b7_drq
97 
                                                                                -- 1 - èñïîëüçóþòñÿ âñå âõîäû b_drq
98 
        );
99 
        port (
100 
 
101 
                -- GLOBAL
102 
                reset           : in std_logic;
103 
                clk                     : in std_logic;
104 
 
105 
                -- T0
106 
                adr_in          : in std_logic_vector( 6 downto 0 );     -- øèíà àäðåñà
107 
                data_in         : in std_logic_vector( 63 downto 0 );    -- øèíà äàííûõ äëÿ DATA
108 
                cmd_data_in     : in std_logic_vector( 15 downto 0 );    -- øèíà äàííûõ äëÿ CMD_DATA
109 
 
110 
                cmd                     : in bl_cmd;                                                    -- êîìàíäà äëÿ òåðàäû
111 
 
112 
                data_out        : out std_logic_vector( 63 downto 0 );   -- âûõîä DATA
113 
                cmd_data_out: out std_logic_vector( 15 downto 0 );       -- âûõîä ðåãèñòðîâ
114 
 
115 
                bx_drq          : out bl_drq;           -- óïðàâëåíèå DMA
116 
 
117 
                test_mode       : out std_logic;                                                -- 1 - òåñòîâûé ðåæèì ðàáîòû
118 
                test_mode_init: in std_logic:='1';                                      -- íà÷àëüíîå ñîñòîÿíèå test_mode
119 
                fifo_rst_out: out std_logic; -- 0 - ñáðîñ FIFO
120 
 
121 
                -- Âõîä ïðåðûâàíèé
122 
                b1_irq          : in std_logic:='0';
123 
                b2_irq          : in std_logic:='0';
124 
                b3_irq          : in std_logic:='0';
125 
                b4_irq          : in std_logic:='0';
126 
                b5_irq          : in std_logic:='0';
127 
                b6_irq          : in std_logic:='0';
128 
                b7_irq          : in std_logic:='0';
129 
                b8_irq          : in std_logic:='0';
130 
                b9_irq          : in std_logic:='0';
131 
                b10_irq         : in std_logic:='0';
132 
                b11_irq         : in std_logic:='0';
133 
                b12_irq         : in std_logic:='0';
134 
                b13_irq         : in std_logic:='0';
135 
                b14_irq         : in std_logic:='0';
136 
                b15_irq         : in std_logic:='0';
137 
 
138 
 
139 
                -- Âõîä çàïðîñîâ DMA
140 
                b1_drq          : in bl_drq:=( '0', '0', '0' );
141 
                b2_drq          : in bl_drq:=( '0', '0', '0' );
142 
                b3_drq          : in bl_drq:=( '0', '0', '0' );
143 
                b4_drq          : in bl_drq:=( '0', '0', '0' );
144 
                b5_drq          : in bl_drq:=( '0', '0', '0' );
145 
                b6_drq          : in bl_drq:=( '0', '0', '0' );
146 
                b7_drq          : in bl_drq:=( '0', '0', '0' );
147 
                b8_drq          : in bl_drq:=( '0', '0', '0' );
148 
                b9_drq          : in bl_drq:=( '0', '0', '0' );
149 
                b10_drq         : in bl_drq:=( '0', '0', '0' );
150 
                b11_drq         : in bl_drq:=( '0', '0', '0' );
151 
                b12_drq         : in bl_drq:=( '0', '0', '0' );
152 
                b13_drq         : in bl_drq:=( '0', '0', '0' );
153 
                b14_drq         : in bl_drq:=( '0', '0', '0' );
154 
                b15_drq         : in bl_drq:=( '0', '0', '0' );
155 
 
156 
                -- Âûõîä DRQ è IRQ
157 
                int1            : out std_logic;
158 
                int2            : out std_logic;
159 
                int3            : out std_logic;
160 
 
161 
                drq0            : out bl_drq;
162 
                drq1            : out bl_drq;
163 
                drq2            : out bl_drq;
164 
                drq3            : out bl_drq;
165 
 
166 
 
167 
                reset_out       : out std_logic; -- ïðîãðàììíûé ñáðîñ
168 
 
169 
 
170 
                -- Óïðàâëåíèå ìóëüòïëåêñîðîì
171 
                cp0                     : out std_logic;
172 
                cp1                     : out std_logic;
173 
 
174 
                -- Óïðàâëåíèå ãåíåðàòîðàìè
175 
                goe0            : out std_logic;
176 
                goe1            : out std_logic;
177 
 
178 
                -- THDAC
179 
                thclk           : out std_logic;        -- òàêòîâàÿ ÷àñòîòà çàãðóçêè ÈÏÍ
180 
                thdin           : out std_logic;        -- äàííûå ÈÏÍ
181 
                thrs            : out std_logic;        -- ñáðîñ ÈÏÍ
182 
                thld            : out std_logic;        -- çàãðóçêà äàííûõ â ÈÏÍ
183 
 
184 
 
185 
 
186 
                mode0           : out std_logic_vector( 15 downto 0 );   -- ðåãèñòð MODE0
187 
                mode1           : out std_logic_vector( 15 downto 0 );  -- ðåãèñòð MODE1
188 
                synx            : out std_logic_vector( 15 downto 0 );  -- ðåãèñòð SYNX
189 
 
190 
                -- Âûõîä ðåãèñòðîâ âûáîðà êàíàëà DMA
191 
                sel_drq0        : out std_logic_vector( 6 downto 0 );
192 
                sel_drq1        : out std_logic_vector( 6 downto 0 );
193 
                sel_drq2        : out std_logic_vector( 6 downto 0 );
194 
                sel_drq3        : out std_logic_vector( 6 downto 0 );
195 
 
196 
                -- Òàêòîâàÿ ÷àñòîòà
197 
                b_clk           : in std_logic_vector( 15 downto 0 );    -- âõîä
198 
                bx_clk          : out std_logic;                -- âûáðàííàÿ òàêòîâàÿ ÷àñòîòà òåòðàäû
199 
 
200 
                -- Ñòàðò
201 
                b_start         : in std_logic_vector( 15 downto 0 ); -- âõîä
202 
                bx_start        : out std_logic;                -- ñèãíàë ðàçðåøåíèÿ ñáîðà
203 
                bx_start_a      : out std_logic;                -- àñèíõðîííûé ñèãíàë ðàçðåøåíèÿ ñáîðà
204 
                bx_start_sync: out std_logic;           -- èìïóëüñ ñèíõðîíèçàöèè
205 
 
206 
                -- SYNX
207 
                sn_rdy0         : in std_logic;                 -- ãîòîâíîñòü 0
208 
                sn_rdy1         : in std_logic;                 -- ãîòîâíîñòü 1
209 
                sn_start_en     : in std_logic;                 -- 0 - ðàçðåøåíèå ñáîðà
210 
                sn_sync0        : in std_logic;                 -- âõîä ñèãíàëà sync
211 
 
212 
                sn_rdy0_out     : out std_logic;                -- âûõîä sn_rdy0
213 
                sn_rdy1_out     : out std_logic;                -- âûõîä sn_rdy1
214 
                sn_start_en_out: out std_logic;         -- âûõîä sn_start_en
215 
                sn_sync0_out: out std_logic;            -- âûõîä sn_sync0
216 
                sn_sync0_in : in  std_logic:='0';        -- óïðàâëåíèå ñèãíàëîì sn_syn0_out â ðåáî÷åì ðåæèìå
217 
 
218 
                sn_rdy0_oe      : out std_logic;                -- 1 - ðàçðåøåíèå âûõîäà sn_rdy0
219 
                sn_rdy1_oe      : out std_logic;                -- 1 - ðàçðåøåíèå âûõîäà sn_rdy1
220 
                sn_master       : out std_logic                 -- 1 - ðàçðåøåíèå âûõîäà start_en, start, encode
221 
 
222 
 
223 
 
224 
        );
225 
end component;
226 
 
227 
end trd_main_v8_pkg;
228 
 
229 
 
230 
 
231 
library ieee;
232 
use ieee.std_logic_1164.all;
233 
 
234 
library work;
235 
use work.adm2_pkg.all;
236 
use     work.ctrl_start_v2_pkg.all;
237 
use work.cl_test0_v4_pkg.all;
238 
 
239 
entity trd_main_v8 is
240 
        generic(
241 
                sync0_mode      : in integer:=0; -- ðåæèì óïðàâëåíèÿ sync0_out
242 
                                                                                --  0 - ÷åðåç SYNX(13)
243 
                                                                                --  1 - ïðè SYNX(15)='0' - âõîä sn_sync0_in
244 
                                                                                --          ïðè SYNX(15)='1' - ÷åðåç SYNX(13)
245 
 
246 
                ext_drq         : in integer:=0          -- 0 - èñïîëüçóþòñÿ òîëüêî âõîäû b1_drq - b7_drq
247 
                                                                                -- 1 - èñïîëüçóþòñÿ âñå âõîäû b_drq
248 
 
249 
        );
250 
        port (
251 
                -- GLOBAL
252 
                reset           : in std_logic;
253 
                clk                     : in std_logic;
254 
 
255 
                -- T0
256 
                adr_in          : in std_logic_vector( 6 downto 0 );     -- øèíà àäðåñà
257 
                data_in         : in std_logic_vector( 63 downto 0 );    -- øèíà äàííûõ äëÿ DATA
258 
                cmd_data_in     : in std_logic_vector( 15 downto 0 );    -- øèíà äàííûõ äëÿ CMD_DATA
259 
 
260 
                cmd                     : in bl_cmd;                                                    -- êîìàíäà äëÿ òåðàäû
261 
 
262 
                data_out        : out std_logic_vector( 63 downto 0 );   -- âûõîä DATA
263 
                cmd_data_out: out std_logic_vector( 15 downto 0 );       -- âûõîä ðåãèñòðîâ
264 
 
265 
                bx_drq          : out bl_drq;           -- óïðàâëåíèå DMA
266 
 
267 
                test_mode       : out std_logic;                                                -- 1 - òåñòîâûé ðåæèì ðàáîòû
268 
                test_mode_init: in std_logic:='1';                                      -- íà÷àëüíîå ñîñòîÿíèå test_mode
269 
                fifo_rst_out: out std_logic; -- 0 - ñáðîñ FIFO
270 
 
271 
                -- Âõîä ïðåðûâàíèé
272 
                b1_irq          : in std_logic:='0';
273 
                b2_irq          : in std_logic:='0';
274 
                b3_irq          : in std_logic:='0';
275 
                b4_irq          : in std_logic:='0';
276 
                b5_irq          : in std_logic:='0';
277 
                b6_irq          : in std_logic:='0';
278 
                b7_irq          : in std_logic:='0';
279 
                b8_irq          : in std_logic:='0';
280 
                b9_irq          : in std_logic:='0';
281 
                b10_irq         : in std_logic:='0';
282 
                b11_irq         : in std_logic:='0';
283 
                b12_irq         : in std_logic:='0';
284 
                b13_irq         : in std_logic:='0';
285 
                b14_irq         : in std_logic:='0';
286 
                b15_irq         : in std_logic:='0';
287 
 
288 
                -- Âõîä çàïðîñîâ DMA
289 
                b1_drq          : in bl_drq:=( '0', '0', '0' );
290 
                b2_drq          : in bl_drq:=( '0', '0', '0' );
291 
                b3_drq          : in bl_drq:=( '0', '0', '0' );
292 
                b4_drq          : in bl_drq:=( '0', '0', '0' );
293 
                b5_drq          : in bl_drq:=( '0', '0', '0' );
294 
                b6_drq          : in bl_drq:=( '0', '0', '0' );
295 
                b7_drq          : in bl_drq:=( '0', '0', '0' );
296 
                b8_drq          : in bl_drq:=( '0', '0', '0' );
297 
                b9_drq          : in bl_drq:=( '0', '0', '0' );
298 
                b10_drq         : in bl_drq:=( '0', '0', '0' );
299 
                b11_drq         : in bl_drq:=( '0', '0', '0' );
300 
                b12_drq         : in bl_drq:=( '0', '0', '0' );
301 
                b13_drq         : in bl_drq:=( '0', '0', '0' );
302 
                b14_drq         : in bl_drq:=( '0', '0', '0' );
303 
                b15_drq         : in bl_drq:=( '0', '0', '0' );
304 
 
305 
                -- Âûõîä DRQ è IRQ
306 
                int1            : out std_logic;
307 
                int2            : out std_logic;
308 
                int3            : out std_logic;
309 
 
310 
                drq0            : out bl_drq;
311 
                drq1            : out bl_drq;
312 
                drq2            : out bl_drq;
313 
                drq3            : out bl_drq;
314 
 
315 
 
316 
                reset_out       : out std_logic; -- ïðîãðàììíûé ñáðîñ
317 
 
318 
 
319 
                -- Óïðàâëåíèå ìóëüòïëåêñîðîì
320 
                cp0                     : out std_logic;
321 
                cp1                     : out std_logic;
322 
 
323 
                -- Óïðàâëåíèå ãåíåðàòîðàìè
324 
                goe0            : out std_logic;
325 
                goe1            : out std_logic;
326 
 
327 
                -- THDAC
328 
                thclk           : out std_logic;        -- òàêòîâàÿ ÷àñòîòà çàãðóçêè ÈÏÍ
329 
                thdin           : out std_logic;        -- äàííûå ÈÏÍ
330 
                thrs            : out std_logic;        -- ñáðîñ ÈÏÍ
331 
                thld            : out std_logic;        -- çàãðóçêà äàííûõ â ÈÏÍ
332 
 
333 
 
334 
 
335 
                mode0           : out std_logic_vector( 15 downto 0 );   -- ðåãèñòð MODE0
336 
                mode1           : out std_logic_vector( 15 downto 0 );  -- ðåãèñòð MODE1
337 
                synx            : out std_logic_vector( 15 downto 0 );  -- ðåãèñòð SYNX
338 
 
339 
                -- Âûõîä ðåãèñòðîâ âûáîðà êàíàëà DMA
340 
                sel_drq0        : out std_logic_vector( 6 downto 0 );
341 
                sel_drq1        : out std_logic_vector( 6 downto 0 );
342 
                sel_drq2        : out std_logic_vector( 6 downto 0 );
343 
                sel_drq3        : out std_logic_vector( 6 downto 0 );
344 
 
345 
                -- Òàêòîâàÿ ÷àñòîòà
346 
                b_clk           : in std_logic_vector( 15 downto 0 );    -- âõîä
347 
                bx_clk          : out std_logic;                -- âûáðàííàÿ òàêòîâàÿ ÷àñòîòà òåòðàäû
348 
 
349 
                -- Ñòàðò
350 
                b_start         : in std_logic_vector( 15 downto 0 ); -- âõîä
351 
                bx_start        : out std_logic;                -- ñèãíàë ðàçðåøåíèÿ ñáîðà
352 
                bx_start_a      : out std_logic;                -- àñèíõðîííûé ñèãíàë ðàçðåøåíèÿ ñáîðà
353 
                bx_start_sync: out std_logic;           -- èìïóëüñ ñèíõðîíèçàöèè
354 
 
355 
                -- SYNX
356 
                sn_rdy0         : in std_logic;                 -- ãîòîâíîñòü 0
357 
                sn_rdy1         : in std_logic;                 -- ãîòîâíîñòü 1
358 
                sn_start_en     : in std_logic;                 -- 0 - ðàçðåøåíèå ñáîðà
359 
                sn_sync0        : in std_logic;                 -- âõîä ñèãíàëà sync
360 
 
361 
                sn_rdy0_out     : out std_logic;                -- âûõîä sn_rdy0
362 
                sn_rdy1_out     : out std_logic;                -- âûõîä sn_rdy1
363 
                sn_start_en_out: out std_logic;         -- âûõîä sn_start_en
364 
                sn_sync0_out: out std_logic;            -- âûõîä sn_sync0
365 
                sn_sync0_in : in  std_logic:='0';        -- óïðàâëåíèå ñèãíàëîì sn_syn0_out â ðåáî÷åì ðåæèìå
366 
 
367 
                sn_rdy0_oe      : out std_logic;                -- 1 - ðàçðåøåíèå âûõîäà sn_rdy0
368 
                sn_rdy1_oe      : out std_logic;                -- 1 - ðàçðåøåíèå âûõîäà sn_rdy1
369 
                sn_master       : out std_logic                 -- 1 - ðàçðåøåíèå âûõîäà start_en, start, encode
370 
 
371 
 
372 
 
373 
        );
374 
 
375 
 
376 
end trd_main_v8;
377 
 
378 
 
379 
architecture trd_main_v8 of trd_main_v8 is
380 
 
381 
component cl_test0_v1 is
382 
        port(
383 
                reset: in std_logic;
384 
                clk: in std_logic;
385 
 
386 
                adr_in: in std_logic_vector( 6 downto 0 );
387 
                data_in: in std_logic_vector( 63 downto 0 );
388 
                data_en: in std_logic;
389 
                data_cs: in std_logic;
390 
 
391 
                data_out: out std_logic_vector( 63 downto 0 );
392 
                test_mode_init: in std_logic;
393 
                test_mode: out std_logic
394 
        );
395 
 
396 
end component;
397 
 
398 
component ctrl_thdac is
399 
         port(
400 
                 reset          : in std_logic;         -- 0 - ñáðîñ
401 
                 clk            : in std_logic;         -- òàêòîâàÿ ÷àñòîòà 100mhz
402 
                 start          : in std_logic;         -- 1 - ñòðàò
403 
                 data_dac       : in std_logic_vector(11 downto 0);      -- äàííûå äëÿ èïí
404 
                 clkdac_out : out std_logic;    -- âûõîäíàÿ òàêòîâàÿ ÷àñòîòà
405 
                 ld             : out std_logic;        -- ñèãíàë çàãðóçêè èïí
406 
                 ready          : out std_logic;        -- 1 - ïåðåñûëêà çàâåðøåíà
407 
                 thrs           : out std_logic;        -- 0 - ñáðîñ èïí
408 
                 sdo_dac        : out std_logic         -- ïîñëåäîâàòåëüíûé ïîðòà èïí
409 
             );
410 
end component;
411 
 
412 
 
413 
signal c_mode0                  : std_logic_vector( 15 downto 0 );       -- MODE0
414 
signal c_mask, c_inv    : std_logic_vector( 15 downto 0 );       -- IRQ_MAK, IRQ_INV
415 
signal c_thdac                  : std_logic_vector( 11 downto 0 );       -- THDAC
416 
signal thdac_start              : std_logic;                                            -- 1 - çàïóñê âûäà÷è â ÈÏÍ
417 
signal c_mux                    : std_logic_vector( 1 downto 0 );        -- MUX
418 
signal do                               : std_logic_vector( 63 downto 0 );       -- âûõîä øèíû äàííûõ ìîäóëÿ òåñòèðîâàíèÿ
419 
signal c_synx                   : std_logic_vector( 15 downto 0 );       -- SYNX
420 
signal c_fmode                  : std_logic_vector( 5 downto 0 );        -- FMODE
421 
signal c_fdiv                   : std_logic_vector( 15 downto 0 );       -- FDIV
422 
signal fdiv_we                  : std_logic;                                            -- 1 - çàïèñü â FDIV
423 
signal c_stmode                 : std_logic_vector( 15 downto 0 );       -- STMODE
424 
signal irq_en                   : std_logic_vector( 15 downto 0 );       -- IRQ_EN
425 
signal c_test_mode              : std_logic;                                            -- TEST_MODE
426 
 
427 
--      âûáîð êàíàëà ïðåðûâàíèÿ
428 
signal c_sel0, c_sel1, c_sel2, c_sel3, c_sel4, c_sel5, c_sel6, c_sel7: std_logic_vector( 1 downto 0 );
429 
 
430 
-- âûáîð êàíàëà çàïðîñà DMA
431 
signal c_sel_drq0, c_sel_drq1, c_sel_drq2, c_sel_drq3: std_logic_vector( 6 downto 0 );
432 
signal b0_irq                   : std_logic;            -- çàïðîñ ïðåðûâàíèå
433 
signal b0_drq                   : bl_drq;                       -- çàïðîñ DMA
434 
signal rst                              : std_logic;            -- 0 - ñáðîñ
435 
 
436 
-- ðàñïðåäåëåíèå ïðåðûâàíèé
437 
signal i0_1, i1_1, i2_1, i3_1, i4_1, i5_1, i6_1, i7_1 : std_logic;
438 
signal i0_2, i1_2, i2_2, i3_2, i4_2, i5_2, i6_2, i7_2 : std_logic;
439 
signal i0_3, i1_3, i2_3, i3_3, i4_3, i5_3, i6_3, i7_3 : std_logic;
440 
signal i8_1, i9_1, i10_1, i11_1, i12_1, i13_1, i14_1, i15_1 : std_logic;
441 
signal i8_2, i9_2, i10_2, i11_2, i12_2, i13_2, i14_2, i15_2 : std_logic;
442 
signal i8_3, i9_3, i10_3, i11_3, i12_3, i13_3, i14_3, i15_3 : std_logic;
443 
 
444 
signal status                   : std_logic_vector( 15 downto 0 );       -- ðåãèñòð ñîñòîÿíèÿ
445 
signal th_rdy                   : std_logic;                                            -- 1 - ãîòîâíîñòü ÈÏÍ
446 
signal data_csp                 : std_logic;                                            -- 1 - ÷òåíèå ðåãèñòðà DATA
447 
signal drq0i, drq1i, drq2i, drq3i: bl_drq;                                      -- âíóòðåííèå ñèãíàëû DMA
448 
 
449 
signal  fifo_rst                : std_logic;    -- 0 - ñáðîñ óçëà òåñòèðîâàíèÿ
450 
signal  synx_test_mode  : std_logic;    -- 1 - ðåæèì òåñòèðîâàíèÿ ðàçú¸ìà SYNX
451 
signal  reg_synx_in             : std_logic_vector( 15 downto 0 );       -- ðåãèñòð SYNX_IN
452 
signal  bx_clki                 : std_logic;
453 
 
454 
begin
455 
 
456 
 
457 
data_csp <= not cmd.data_cs;
458 
 
459 
d_test0: cl_test0_v4
460 
        port map (
461 
                reset => reset,
462 
                reset_reg => fifo_rst,
463 
                clk => clk,
464 
                reg_test_mode   => c_test_mode, -- 1 - ôîðìèðîâàíèå ïñåâäîñëó÷àéíîé ïîñëåäîâàòåëüíîñòè
465 
 
466 
                adr_in => adr_in,
467 
                data_in => data_in,
468 
                data_en => cmd.data_we,
469 
                --data_en => '0',
470 
                data_cs => data_csp,
471 
 
472 
                data_out => do,
473 
                test_mode_init => test_mode_init,
474 
                test_mode => test_mode  );
475 
 
476 
 
477 
--xstatus: ctrl_buft16 port map(
478 
--      t => cmd.status_cs,
479 
--      i =>  status,
480 
--      o => cmd_data_out );
481 
--
482 
--xirq: ctrl_buft16 port map(
483 
--      t => cmd.cmd_data_cs,
484 
--      i =>  irq_en,
485 
--      o => cmd_data_out );
486 
 
487 
 
488 
cmd_data_out <=  status when cmd.status_cs='0' else
489 
                                 irq_en when cmd.adr(1)='0' else
490 
                                 reg_synx_in;
491 
 
492 
 
493 
 
494 
data_out<=do;
495 
 
496 
 
497 
irq_en(0)<='0';
498 
irq_en( 15 downto 4 )<=(others=>'0');
499 
 
500 
 
501 
pr_mode0: process( reset, clk )
502 
 variable vthdac_start: std_logic;
503 
 variable vfdiv_we: std_logic;
504 
begin
505 
        if( reset='0' ) then
506 
                c_mode0<=(others=>'0');
507 
        elsif( rising_edge( clk ) ) then
508 
                vthdac_start:='0';
509 
                vfdiv_we:='0';
510 
                if( cmd.cmd_data_we='1' ) then
511 
 
512 
                        if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
513 
                          case cmd.adr( 4 downto 0 ) is
514 
                                  when "00000" =>  -- MODE0
515 
                                    c_mode0<=cmd_data_in( 15 downto 0 );
516 
                                  when others=>null;
517 
                          end case;
518 
                        end if;
519 
                end if;
520 
        end if;
521 
end process;
522 
 
523 
 
524 
pr_reg: process( rst, clk )
525 
 variable vthdac_start: std_logic;
526 
 variable vfdiv_we: std_logic;
527 
begin
528 
        if( rst='0' ) then
529 
                vthdac_start:='0';
530 
                vfdiv_we:='0';
531 
                irq_en( 3 downto 1 ) <= (others=>'0');
532 
                c_mask<=(others=>'0');
533 
                c_inv<=(others=>'0');
534 
                c_fmode<=(others=>'0');
535 
                c_fdiv<=(others=>'0');
536 
                c_stmode<=(others=>'0');
537 
                c_sel0<=(others=>'0');
538 
                c_sel1<=(others=>'0');
539 
                c_sel2<=(others=>'0');
540 
                c_sel3<=(others=>'0');
541 
                c_sel4<=(others=>'0');
542 
                c_sel5<=(others=>'0');
543 
                c_sel6<=(others=>'0');
544 
                c_sel7<=(others=>'0');
545 
                c_sel_drq0<=(others=>'0');
546 
                c_sel_drq1<=(others=>'0');
547 
                c_sel_drq2<=(others=>'0');
548 
                c_sel_drq3<=(others=>'0');
549 
                mode1<=(others=>'0');
550 
                c_synx<=(others=>'0');
551 
                c_mux<=(others=>'0');
552 
                c_thdac<=(others=>'0');
553 
                c_test_mode <= '0';
554 
        elsif( rising_edge( clk ) ) then
555 
                vthdac_start:='0';
556 
                vfdiv_we:='0';
557 
                if( cmd.cmd_data_we='1' ) then
558 
                        if( cmd.adr(9)='1' and cmd.adr(8)='0' ) then
559 
                            if( cmd.adr(0)='0' ) then -- IRQENST
560 
                                  irq_en( 3 downto 1 ) <= irq_en( 3 downto 1 ) or cmd_data_in( 3 downto 1 );
561 
                            else
562 
                                  irq_en( 3 downto 1 ) <= irq_en( 3 downto 1 ) and not cmd_data_in( 3 downto 1 );
563 
                                end if;
564 
                                --irq_en( 3 downto 1 ) <=  irq_en( 3 downto 1 ) or data_in( 3 downto 1 );
565 
                        end if;
566 
 
567 
                        if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
568 
                          case cmd.adr( 4 downto 0 ) is
569 
                                  when "00001" =>  -- C_MASK
570 
                                    c_mask<=cmd_data_in( 15 downto 0 );
571 
                                  when "00010" =>  -- C_INV
572 
                                    c_inv<=cmd_data_in( 15 downto 0 );
573 
--                                when "0001" => -- IRQ_ACK
574 
--                                  irq_ack<=data_in( 2 downto 0 );
575 
                                  when "00011" =>       -- FMODE
576 
                                    c_fmode<=cmd_data_in( 5 downto 0 );
577 
                                  when "00100" =>       -- FDIV
578 
                                    c_fdiv<=cmd_data_in( 15 downto 0 );
579 
                                        vfdiv_we:='1';
580 
                                  when "00101" =>       -- STMODE
581 
                                    c_stmode<=cmd_data_in( 15 downto 0 );
582 
 
583 
                                  when "01001" =>       -- MODE1
584 
                                    mode1 <= cmd_data_in( 15 downto 0 );
585 
 
586 
                                  when "01100" =>       -- TEST_MODE
587 
                                    c_test_mode <= cmd_data_in(0);
588 
 
589 
                                  when "01101" =>       -- SYNX
590 
                                    c_synx( 15 downto 0 ) <=cmd_data_in( 15 downto 0 );
591 
                                  when "01110" =>       -- THDAC
592 
                                        c_thdac<=cmd_data_in( 11 downto 0 );
593 
                                        vthdac_start:='1';
594 
                                  when "01111" =>       -- MUX
595 
                                   c_mux<=cmd_data_in( 1 downto 0 );
596 
                                  when "10000" => -- c_sel0
597 
                                   c_sel0( 1 downto 0 ) <=cmd_data_in( 1 downto 0 );
598 
                                   c_sel_drq0( 6 downto 0 ) <= cmd_data_in( 14 downto 8 );
599 
                                  when "10001" => -- c_sel1
600 
                                   c_sel1( 1 downto 0 ) <=cmd_data_in( 1 downto 0 );
601 
                                   c_sel_drq1( 6 downto 0 ) <= cmd_data_in( 14 downto 8 );
602 
                                  when "10010" => -- c_sel2
603 
                                   c_sel2( 1 downto 0 ) <=cmd_data_in( 1 downto 0 );
604 
                                   c_sel_drq2( 6 downto 0 ) <= cmd_data_in( 14 downto 8 );
605 
                                  when "10011" => -- c_sel3
606 
                                   c_sel3( 1 downto 0 ) <=cmd_data_in( 1 downto 0 );
607 
                                   c_sel_drq3( 6 downto 0 ) <= cmd_data_in( 14 downto 8 );
608 
                                  when "10100" => -- c_sel4
609 
                                   c_sel4( 1 downto 0 ) <=cmd_data_in( 1 downto 0 );
610 
                                  when "10101" => -- c_sel5
611 
                                   c_sel5( 1 downto 0 ) <=cmd_data_in( 1 downto 0 );
612 
                                  when "10110" => -- c_sel6
613 
                                   c_sel6( 1 downto 0 ) <=cmd_data_in( 1 downto 0 );
614 
                                  when "10111" => -- c_sel7
615 
                                   c_sel7( 1 downto 0 ) <=cmd_data_in( 1 downto 0 );
616 
 
617 
 
618 
                                  when others=>null;
619 
                          end case;
620 
                        end if;
621 
                end if;
622 
                thdac_start <= vthdac_start;
623 
                fdiv_we <= vfdiv_we;
624 
        end if;
625 
end process;
626 
 
627 
rst<='0' when reset='0' or c_mode0(0)='1' else '1';
628 
reset_out<=rst after 1 ns when rising_edge( clk );
629 
 
630 
fifo_rst <= '0' when rst='0' or c_mode0(1)='1' else '1';
631 
fifo_rst_out <= fifo_rst  after 1 ns when rising_edge( clk );
632 
 
633 
cp0<=c_mux(0);
634 
cp1<=c_mux(1);
635 
 
636 
-- Ôîðìèðîâàíèå ïðåðûâàíèé
637 
i0_1<='1' when c_sel0(1 downto 0)="01" and b0_irq='1' else '0';
638 
i1_1<='1' when c_sel1(1 downto 0)="01" and b1_irq='1' else '0';
639 
i2_1<='1' when c_sel2(1 downto 0)="01" and b2_irq='1' else '0';
640 
i3_1<='1' when c_sel3(1 downto 0)="01" and b3_irq='1' else '0';
641 
i4_1<='1' when c_sel4(1 downto 0)="01" and b4_irq='1' else '0';
642 
i5_1<='1' when c_sel5(1 downto 0)="01" and b5_irq='1' else '0';
643 
i6_1<='1' when c_sel6(1 downto 0)="01" and b6_irq='1' else '0';
644 
i7_1<='1' when c_sel7(1 downto 0)="01" and b7_irq='1' else '0';
645 
i8_1<='1' when c_sel0(1 downto 0)="01" and b8_irq='1' else '0';
646 
i9_1<='1' when c_sel1(1 downto 0)="01" and b9_irq='1' else '0';
647 
i10_1<='1' when c_sel2(1 downto 0)="01" and b10_irq='1' else '0';
648 
i11_1<='1' when c_sel3(1 downto 0)="01" and b11_irq='1' else '0';
649 
i12_1<='1' when c_sel4(1 downto 0)="01" and b12_irq='1' else '0';
650 
i13_1<='1' when c_sel5(1 downto 0)="01" and b13_irq='1' else '0';
651 
i14_1<='1' when c_sel6(1 downto 0)="01" and b14_irq='1' else '0';
652 
i15_1<='1' when c_sel7(1 downto 0)="01" and b15_irq='1' else '0';
653 
 
654 
i0_2<='1' when c_sel0(1 downto 0)="10" and b0_irq='1' else '0';
655 
i1_2<='1' when c_sel1(1 downto 0)="10" and b1_irq='1' else '0';
656 
i2_2<='1' when c_sel2(1 downto 0)="10" and b2_irq='1' else '0';
657 
i3_2<='1' when c_sel3(1 downto 0)="10" and b3_irq='1' else '0';
658 
i4_2<='1' when c_sel4(1 downto 0)="10" and b4_irq='1' else '0';
659 
i5_2<='1' when c_sel5(1 downto 0)="10" and b5_irq='1' else '0';
660 
i6_2<='1' when c_sel6(1 downto 0)="10" and b6_irq='1' else '0';
661 
i7_2<='1' when c_sel7(1 downto 0)="10" and b7_irq='1' else '0';
662 
i8_2<='1' when c_sel0(1 downto 0)="10" and b8_irq='1' else '0';
663 
i9_2<='1' when c_sel1(1 downto 0)="10" and b9_irq='1' else '0';
664 
i10_2<='1' when c_sel2(1 downto 0)="10" and b10_irq='1' else '0';
665 
i11_2<='1' when c_sel3(1 downto 0)="10" and b11_irq='1' else '0';
666 
i12_2<='1' when c_sel4(1 downto 0)="10" and b12_irq='1' else '0';
667 
i13_2<='1' when c_sel5(1 downto 0)="10" and b13_irq='1' else '0';
668 
i14_2<='1' when c_sel6(1 downto 0)="10" and b14_irq='1' else '0';
669 
i15_2<='1' when c_sel7(1 downto 0)="10" and b15_irq='1' else '0';
670 
 
671 
i0_3<='1' when c_sel0(1 downto 0)="11" and b0_irq='1' else '0';
672 
i1_3<='1' when c_sel1(1 downto 0)="11" and b1_irq='1' else '0';
673 
i2_3<='1' when c_sel2(1 downto 0)="11" and b2_irq='1' else '0';
674 
i3_3<='1' when c_sel3(1 downto 0)="11" and b3_irq='1' else '0';
675 
i4_3<='1' when c_sel4(1 downto 0)="11" and b4_irq='1' else '0';
676 
i5_3<='1' when c_sel5(1 downto 0)="11" and b5_irq='1' else '0';
677 
i6_3<='1' when c_sel6(1 downto 0)="11" and b6_irq='1' else '0';
678 
i7_3<='1' when c_sel7(1 downto 0)="11" and b7_irq='1' else '0';
679 
i8_3<='1' when c_sel0(1 downto 0)="11" and b8_irq='1' else '0';
680 
i9_3<='1' when c_sel1(1 downto 0)="11" and b9_irq='1' else '0';
681 
i10_3<='1' when c_sel2(1 downto 0)="11" and b10_irq='1' else '0';
682 
i11_3<='1' when c_sel3(1 downto 0)="11" and b11_irq='1' else '0';
683 
i12_3<='1' when c_sel4(1 downto 0)="11" and b12_irq='1' else '0';
684 
i13_3<='1' when c_sel5(1 downto 0)="11" and b13_irq='1' else '0';
685 
i14_3<='1' when c_sel6(1 downto 0)="11" and b14_irq='1' else '0';
686 
i15_3<='1' when c_sel7(1 downto 0)="11" and b15_irq='1' else '0';
687 
 
688 
int1<=( i0_1 or i1_1 or i2_1 or i3_1 or i4_1 or i5_1 or i6_1 or i7_1 or
689 
                i8_1 or i9_1 or i10_1 or i11_1 or       i12_1 or i13_1 or i14_1 or i15_1
690 
                ) and ( irq_en(1) );
691 
 
692 
int2<=( i0_2 or i1_2 or i2_2 or i3_2 or i4_2 or i5_2 or i6_2 or i7_2 or
693 
                i8_2 or i9_2 or i10_2 or i11_2 or i12_2 or i13_2 or i14_2 or i15_2
694 
                ) and ( irq_en(2) );
695 
 
696 
int3<=( i0_3 or i1_3 or i2_3 or i3_3 or i4_3 or i5_3 or i6_3 or i7_3 or
697 
                i8_3 or i9_3 or i10_3 or i11_3 or i12_3 or i13_3 or i14_3 or i15_3
698 
                ) and ( irq_en(3) );
699 
 
700 
 
701 
gen_trd0: if( ext_drq=0 ) generate
702 
 
703 
pr_drq0: process( c_sel_drq0, b0_drq, b1_drq, b2_drq, b3_drq,
704 
                                        b4_drq, b5_drq, b6_drq, b7_drq ) is
705 
begin
706 
        case c_sel_drq0( 2 downto 0 ) is
707 
                when "000" => drq0i<=b0_drq;
708 
                when "001" => drq0i<=b1_drq;
709 
                when "010" => drq0i<=b2_drq;
710 
                when "011" => drq0i<=b3_drq;
711 
                when "100" => drq0i<=b4_drq;
712 
                when "101" => drq0i<=b5_drq;
713 
                when "110" => drq0i<=b6_drq;
714 
                when "111" => drq0i<=b7_drq;
715 
                when others => null;
716 
        end case;
717 
end process;
718 
 
719 
drq0.en<=drq0i.en and c_sel_drq0(4);
720 
drq0.req<=drq0i.req;
721 
drq0.ack<=drq0i.ack;
722 
 
723 
pr_drq1: process( c_sel_drq1, b0_drq, b1_drq, b2_drq, b3_drq,
724 
                                        b4_drq, b5_drq, b6_drq, b7_drq ) is
725 
begin
726 
        case c_sel_drq1( 2 downto 0 ) is
727 
                when "000" => drq1i<=b0_drq;
728 
                when "001" => drq1i<=b1_drq;
729 
                when "010" => drq1i<=b2_drq;
730 
                when "011" => drq1i<=b3_drq;
731 
                when "100" => drq1i<=b4_drq;
732 
                when "101" => drq1i<=b5_drq;
733 
                when "110" => drq1i<=b6_drq;
734 
                when "111" => drq1i<=b7_drq;
735 
                when others => null;
736 
        end case;
737 
end process;
738 
 
739 
drq1.en<=drq1i.en and c_sel_drq1(4);
740 
drq1.req<=drq1i.req;
741 
drq1.ack<=drq1i.ack;
742 
 
743 
pr_drq2: process( c_sel_drq2, b0_drq, b1_drq, b2_drq, b3_drq,
744 
                                        b4_drq, b5_drq, b6_drq, b7_drq ) is
745 
begin
746 
        case c_sel_drq2( 2 downto 0 ) is
747 
                when "000" => drq2i<=b0_drq;
748 
                when "001" => drq2i<=b1_drq;
749 
                when "010" => drq2i<=b2_drq;
750 
                when "011" => drq2i<=b3_drq;
751 
                when "100" => drq2i<=b4_drq;
752 
                when "101" => drq2i<=b5_drq;
753 
                when "110" => drq2i<=b6_drq;
754 
                when "111" => drq2i<=b7_drq;
755 
                when others => null;
756 
        end case;
757 
end process;
758 
 
759 
drq2.en<=drq2i.en and c_sel_drq2(4);
760 
drq2.req<=drq2i.req;
761 
drq2.ack<=drq2i.ack;
762 
 
763 
 
764 
 
765 
 
766 
 
767 
pr_drq3: process( c_sel_drq3, b0_drq, b1_drq, b2_drq, b3_drq,
768 
                                        b4_drq, b5_drq, b6_drq, b7_drq ) is
769 
begin
770 
        case c_sel_drq3( 2 downto 0 ) is
771 
                when "000" => drq3i<=b0_drq;
772 
                when "001" => drq3i<=b1_drq;
773 
                when "010" => drq3i<=b2_drq;
774 
                when "011" => drq3i<=b3_drq;
775 
                when "100" => drq3i<=b4_drq;
776 
                when "101" => drq3i<=b5_drq;
777 
                when "110" => drq3i<=b6_drq;
778 
                when "111" => drq3i<=b7_drq;
779 
                when others => null;
780 
        end case;
781 
end process;
782 
 
783 
drq3.en<=drq3i.en and c_sel_drq3(4);
784 
drq3.req<=drq3i.req;
785 
drq3.ack<=drq3i.ack;
786 
 
787 
end generate;
788 
 
789 
 
790 
 
791 
gen_trd8: if( ext_drq=1 ) generate
792 
 
793 
drq0i <= b0_drq when c_sel_drq0( 3 downto 0 )="0000" else
794 
                 b1_drq when c_sel_drq0( 3 downto 0 )="0001" else
795 
                 b2_drq when c_sel_drq0( 3 downto 0 )="0010" else
796 
                 b3_drq when c_sel_drq0( 3 downto 0 )="0011" else
797 
                 b4_drq when c_sel_drq0( 3 downto 0 )="0100" else
798 
                 b5_drq when c_sel_drq0( 3 downto 0 )="0101" else
799 
                 b6_drq when c_sel_drq0( 3 downto 0 )="0110" else
800 
                 b7_drq when c_sel_drq0( 3 downto 0 )="0111" else
801 
                 b8_drq when c_sel_drq0( 3 downto 0 )="1000" else
802 
                 b9_drq when c_sel_drq0( 3 downto 0 )="1001" else
803 
                 b10_drq when c_sel_drq0( 3 downto 0 )="1010" else
804 
                 b11_drq when c_sel_drq0( 3 downto 0 )="1011" else
805 
                 b12_drq when c_sel_drq0( 3 downto 0 )="1100" else
806 
                 b13_drq when c_sel_drq0( 3 downto 0 )="1101" else
807 
                 b14_drq when c_sel_drq0( 3 downto 0 )="1110" else
808 
                 b15_drq when c_sel_drq0( 3 downto 0 )="1111";
809 
 
810 
 
811 
drq0.en<=drq0i.en and c_sel_drq0(4);
812 
drq0.req<=drq0i.req;
813 
drq0.ack<=drq0i.ack;
814 
 
815 
drq1i <= b0_drq when c_sel_drq1( 3 downto 0 )="0000" else
816 
                 b1_drq when c_sel_drq1( 3 downto 0 )="0001" else
817 
                 b2_drq when c_sel_drq1( 3 downto 0 )="0010" else
818 
                 b3_drq when c_sel_drq1( 3 downto 0 )="0011" else
819 
                 b4_drq when c_sel_drq1( 3 downto 0 )="0100" else
820 
                 b5_drq when c_sel_drq1( 3 downto 0 )="0101" else
821 
                 b6_drq when c_sel_drq1( 3 downto 0 )="0110" else
822 
                 b7_drq when c_sel_drq1( 3 downto 0 )="0111" else
823 
                 b8_drq when c_sel_drq1( 3 downto 0 )="1000" else
824 
                 b9_drq when c_sel_drq1( 3 downto 0 )="1001" else
825 
                 b10_drq when c_sel_drq1( 3 downto 0 )="1010" else
826 
                 b11_drq when c_sel_drq1( 3 downto 0 )="1011" else
827 
                 b12_drq when c_sel_drq1( 3 downto 0 )="1100" else
828 
                 b13_drq when c_sel_drq1( 3 downto 0 )="1101" else
829 
                 b14_drq when c_sel_drq1( 3 downto 0 )="1110" else
830 
                 b15_drq when c_sel_drq1( 3 downto 0 )="1111";
831 
 
832 
drq1.en<=drq1i.en and c_sel_drq1(4);
833 
drq1.req<=drq1i.req;
834 
drq1.ack<=drq1i.ack;
835 
 
836 
drq2i <= b0_drq when c_sel_drq2( 3 downto 0 )="0000" else
837 
                 b1_drq when c_sel_drq2( 3 downto 0 )="0001" else
838 
                 b2_drq when c_sel_drq2( 3 downto 0 )="0010" else
839 
                 b3_drq when c_sel_drq2( 3 downto 0 )="0011" else
840 
                 b4_drq when c_sel_drq2( 3 downto 0 )="0100" else
841 
                 b5_drq when c_sel_drq2( 3 downto 0 )="0101" else
842 
                 b6_drq when c_sel_drq2( 3 downto 0 )="0110" else
843 
                 b7_drq when c_sel_drq2( 3 downto 0 )="0111" else
844 
                 b8_drq when c_sel_drq2( 3 downto 0 )="1000" else
845 
                 b9_drq when c_sel_drq2( 3 downto 0 )="1001" else
846 
                 b10_drq when c_sel_drq2( 3 downto 0 )="1010" else
847 
                 b11_drq when c_sel_drq2( 3 downto 0 )="1011" else
848 
                 b12_drq when c_sel_drq2( 3 downto 0 )="1100" else
849 
                 b13_drq when c_sel_drq2( 3 downto 0 )="1101" else
850 
                 b14_drq when c_sel_drq2( 3 downto 0 )="1110" else
851 
                 b15_drq when c_sel_drq2( 3 downto 0 )="1111";
852 
 
853 
drq2.en<=drq2i.en and c_sel_drq2(4);
854 
drq2.req<=drq2i.req;
855 
drq2.ack<=drq2i.ack;
856 
 
857 
 
858 
 
859 
 
860 
 
861 
drq3i <= b0_drq when c_sel_drq3( 3 downto 0 )="0000" else
862 
                 b1_drq when c_sel_drq3( 3 downto 0 )="0001" else
863 
                 b2_drq when c_sel_drq3( 3 downto 0 )="0010" else
864 
                 b3_drq when c_sel_drq3( 3 downto 0 )="0011" else
865 
                 b4_drq when c_sel_drq3( 3 downto 0 )="0100" else
866 
                 b5_drq when c_sel_drq3( 3 downto 0 )="0101" else
867 
                 b6_drq when c_sel_drq3( 3 downto 0 )="0110" else
868 
                 b7_drq when c_sel_drq3( 3 downto 0 )="0111" else
869 
                 b8_drq when c_sel_drq3( 3 downto 0 )="1000" else
870 
                 b9_drq when c_sel_drq3( 3 downto 0 )="1001" else
871 
                 b10_drq when c_sel_drq3( 3 downto 0 )="1010" else
872 
                 b11_drq when c_sel_drq3( 3 downto 0 )="1011" else
873 
                 b12_drq when c_sel_drq3( 3 downto 0 )="1100" else
874 
                 b13_drq when c_sel_drq3( 3 downto 0 )="1101" else
875 
                 b14_drq when c_sel_drq3( 3 downto 0 )="1110" else
876 
                 b15_drq when c_sel_drq3( 3 downto 0 )="1111";
877 
 
878 
drq3.en<=drq3i.en and c_sel_drq3(4);
879 
drq3.req<=drq3i.req;
880 
drq3.ack<=drq3i.ack;
881 
 
882 
end generate;
883 
 
884 
 
885 
sel_drq0 <= c_sel_drq0;
886 
sel_drq1 <= c_sel_drq1;
887 
sel_drq2 <= c_sel_drq2;
888 
sel_drq3 <= c_sel_drq3;
889 
 
890 
mode0 <= c_mode0;
891 
 
892 
 
893 
 
894 
 
895 
 
896 
b0_drq.en<=c_mode0(3);
897 
b0_drq.req<= c_mode0(3);
898 
b0_drq.ack<=data_csp;
899 
 
900 
bx_drq <= b0_drq;
901 
 
902 
start: ctrl_start_v2 port map (
903 
 
904 
                reset   => rst,
905 
                mode0   => c_mode0,
906 
                stmode  => c_stmode,
907 
                fmode   => c_fmode,
908 
                fdiv    => c_fdiv,
909 
                fdiv_we => fdiv_we,
910 
 
911 
                b_clk   => b_clk,
912 
                b_start => b_start,
913 
 
914 
                bx_clk          => bx_clki,
915 
                bx_start        => bx_start,
916 
                bx_start_a      => bx_start_a,
917 
                bx_start_sync => bx_start_sync,
918 
                goe0    => goe0,
919 
                goe1    => goe1
920 
                );
921 
 
922 
 
923 
thdac: ctrl_thdac port map (
924 
                 reset  => rst,
925 
                 clk    => clk,
926 
                 start  => thdac_start,
927 
                 data_dac => c_thdac,
928 
                 clkDAC_out => thclk,
929 
                 ld             => thld,
930 
                 ready          => th_rdy,
931 
                 thrs           => thrs,
932 
                 sdo_dac        => thdin   );
933 
 
934 
-- STATUS
935 
status(0) <= th_rdy;     -- CMD_RDY
936 
status(1) <= '1';               -- RDY
937 
status(2) <= '1';               -- EF
938 
status(3) <= '1';               -- PAE
939 
status(4) <= '0';                -- HF
940 
status(5) <= '1';               -- PAF
941 
status(6) <= '1';               -- FF
942 
status(7) <= '0';                -- OVR
943 
status(8) <= '0';                -- UND
944 
status(9) <= sn_rdy0;   -- SN_RDY0
945 
status(10) <= sn_rdy1;  -- SN_RDY1
946 
status(11) <= b_start(4);       -- SN_START
947 
status(12) <= sn_start_en;  -- SN_START_EN
948 
status(13) <= sn_sync0;         -- SN_SYNC0
949 
status(14) <= b_start(1);       -- COMP0
950 
status(15) <= b_start(2);       -- COMP1
951 
 
952 
 
953 
pr_b0_irq: process( status, c_mask, c_inv, c_mode0 )
954 
 variable v: std_logic;
955 
begin
956 
        v:='0';
957 
        if( c_mode0(2)='1' ) then
958 
                for i in 0 to 15 loop
959 
                        if( ((status(i) xor c_inv(i)) and c_mask(i))='1' ) then
960 
                                v:='1';
961 
                        end if;
962 
                end loop;
963 
        end if;
964 
        b0_irq<=v;
965 
end process;
966 
 
967 
 
968 
sn_rdy0_out     <= c_synx(0);
969 
sn_rdy1_out     <= c_synx(1);
970 
sn_rdy0_oe              <= c_synx(4);
971 
sn_rdy1_oe              <= c_synx(5);
972 
sn_start_en_out <= c_synx(12);
973 
--sn_sync0_out  <= c_synx(13);
974 
 
975 
synx_test_mode  <= c_synx(15);
976 
 
977 
gen_syn0_0: if( sync0_mode=0 ) generate
978 
 
979 
        sn_sync0_out    <=  c_synx(13);
980 
 
981 
end generate;
982 
 
983 
gen_syn0_1: if( sync0_mode=1 ) generate
984 
 
985 
        sn_sync0_out    <= sn_sync0_in when synx_test_mode='0' else c_synx(13);
986 
 
987 
end generate;
988 
 
989 
 
990 
bx_clk <= bx_clki when  synx_test_mode='0' else c_synx(14);
991 
 
992 
sn_master <= c_mode0(4);
993 
 
994 
reg_synx_in( 8 downto 0 ) <= (others=>'0');
995 
 
996 
reg_synx_in(9)  <= sn_rdy0;                     -- SN_RDY0
997 
reg_synx_in(10) <= sn_rdy1;             -- SN_RDY1
998 
reg_synx_in(11) <= b_start(4);          -- SN_START
999 
reg_synx_in(12) <= sn_start_en;         -- SN_START_EN
1000 
reg_synx_in(13) <= sn_sync0;            -- SN_SYNC0
1001 
reg_synx_in(14) <= b_clk(4);            -- SN_ENCODE
1002 
reg_synx_in(15) <= synx_test_mode;      -- SYNX_TEST_MODE
1003 
 
1004 
synx <= c_synx;
1005 
 
1006 
end trd_main_v8;

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