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--
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-- Title : trd_pio_std_v4
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-- Design : adp101v7_v20_admddc4x16_s
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-- Author : ILYA Ivanov
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-- Company : Instrumental System
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Description : Модуль управления портом PIOX
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Version : 1.3
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---------------------------------------------------------------------------------------------------
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--
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-- Version 1.3 18.12.2009
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-- Исправлено формирование сигнала PIO_RD во время сброса
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Version 1.2 21.02.2006
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-- Добавлено использование сигналов TTL в режиме LVDS
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Version 1.1 12.12.2005
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-- Убраны буфера с 3 состоянием
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--
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---------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.adm2_pkg.all;
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package trd_pio_std_v4_pkg is
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constant ID_PIO_STD : std_logic_vector( 15 downto 0 ):=x"0003"; -- идентификатор тетрады
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constant ID_MODE_PIO_STD : std_logic_vector( 15 downto 0 ):=x"0004"; -- модификатор тетрады
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constant VER_PIO_STD : std_logic_vector( 15 downto 0 ):=x"0103"; -- версия тетрады
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constant RES_PIO_STD : std_logic_vector( 15 downto 0 ):=x"0000"; -- ресурсы тетрады
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constant FIFO_PIO_STD : std_logic_vector( 15 downto 0 ):=x"0000"; -- размер FIFO
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constant FTYPE_PIO_STD : std_logic_vector( 15 downto 0 ):=x"0000"; -- ширина FIFO
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component trd_pio_std_v4 is
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generic (
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-- 1 - бит MODE1[ENABLE] не используется
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-- 2 - бит MODE1[ENABLE] используется
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use_enable : integer:=1
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);
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port(
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-- GLOBAL
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reset : in std_logic;
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clk : in std_logic;
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-- Управление тетрадой
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data_in : in std_logic_vector( 15 downto 0 ); -- шина данных DATA
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cmd_data_in : in std_logic_vector( 15 downto 0 ); -- шина данных CMD_DATA
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cmd : in bl_cmd; -- сигналы управления
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data_out : out std_logic_vector( 15 downto 0 ); -- выход данных с третьим состоянием (через buft)
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data_out2 : out std_logic_vector( 15 downto 0 ); -- выход данных напрямую
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cmd_data_out: out std_logic_vector( 15 downto 0 ); -- выходы регистров с третьим состоянием (через buft)
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cmd_data_out2 : out std_logic_vector( 15 downto 0 ); -- выходы регистров напрямую
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bx_irq : out std_logic; -- 1 - прерывание от тетрады
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--- сигналы управления PIOX ------------
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pio_enable : out std_logic; -- '0' - разрешение выхода pio_wr, pio_rd
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pen0 : out std_logic;
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pen1_in : in std_logic:='0';
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pen1 : out std_logic;
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pen1_oe : out std_logic;
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pio_oe0 : out std_logic; -- '0' - разрешение выхода pio(7..0)
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pio_oe1 : out std_logic; -- '0' - разрешение выхода pio(15..8)
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pio_in : in std_logic_vector( 15 downto 0 ); -- вход данных
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pio_out : out std_logic_vector( 15 downto 0 ); -- выход данных
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-- только для режима TTL
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pio_wr : out std_logic; -- строб записи
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pio_rd : out std_logic; -- строб чтения
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ack_wr : in std_logic; -- подтверждение записи
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ack_rd : in std_logic; -- подтверждение чтения
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lvds : out std_logic -- 0-режим LVDS разрешает выход pio(15,13,11,9)
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----------------------------------------
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);
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end component;
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end trd_pio_std_v4_pkg;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use work.adm2_pkg.all;
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entity trd_pio_std_v4 is
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generic (
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-- 1 - бит MODE1[ENABLE] не используется
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-- 2 - бит MODE1[ENABLE] используется
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use_enable : integer:=1
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);
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port(
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-- GLOBAL
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reset : in std_logic;
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clk : in std_logic;
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-- Управление тетрадой
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data_in : in std_logic_vector( 15 downto 0 ); -- шина данных DATA
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cmd_data_in : in std_logic_vector( 15 downto 0 ); -- шина данных CMD_DATA
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cmd : in bl_cmd; -- сигналы управления
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data_out : out std_logic_vector( 15 downto 0 ); -- выход данных с третьим состоянием (через buft)
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data_out2 : out std_logic_vector( 15 downto 0 ); -- выход данных напрямую
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cmd_data_out: out std_logic_vector( 15 downto 0 ); -- выходы регистров с третьим состоянием (через buft)
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cmd_data_out2 : out std_logic_vector( 15 downto 0 ); -- выходы регистров напрямую
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bx_irq : out std_logic; -- 1 - прерывание от тетрады
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--- сигналы управления PIOX ------------
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pio_enable : out std_logic; -- '0' - разрешение выхода pio_wr, pio_rd
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pen0 : out std_logic;
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pen1_in : in std_logic:='0';
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pen1 : out std_logic;
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pen1_oe : out std_logic;
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pio_oe0 : out std_logic; -- '0' - разрешение выхода pio(7..0)
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pio_oe1 : out std_logic; -- '0' - разрешение выхода pio(15..8)
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pio_in : in std_logic_vector( 15 downto 0 ); -- вход данных
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pio_out : out std_logic_vector( 15 downto 0 ); -- выход данных
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-- только для режима TTL
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pio_wr : out std_logic; -- строб записи
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pio_rd : out std_logic; -- строб чтения
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ack_wr : in std_logic; -- подтверждение записи
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ack_rd : in std_logic; -- подтверждение чтения
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lvds : out std_logic -- 0-режим LVDS разрешает выход pio(15,13,11,9)
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----------------------------------------
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);
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end trd_pio_std_v4;
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architecture trd_pio_std_v4 of trd_pio_std_v4 is
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signal c_status : std_logic_vector( 15 downto 0 );
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signal c_pio : std_logic_vector( 15 downto 0 ); -- защёлкнутые данные с разъёма
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signal c_flag, c_irq : std_logic_vector( 12 downto 9 );
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signal c_mask, c_inv : std_logic_vector( 12 downto 9 );
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signal c_mode0 : std_logic_vector( 15 downto 0 );
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signal c_mode1 : std_logic_vector( 15 downto 0 );
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signal c_mode2 : std_logic_vector( 15 downto 0 );
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signal cnt_wr : std_logic_vector( 7 downto 0 ); -- счётчик строба записи
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signal cnt_rd : std_logic_vector( 7 downto 0 ):=(others=>'0'); -- счётчик строба чтения
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signal cnt_wr_z : std_logic; -- 1 - cnt_wr="0000"
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signal cnt_rd_z : std_logic; -- 1 - cnt_rd="0000"
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signal fack_wr : std_logic; -- 1 - фронт ack_wr
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signal fack_rd : std_logic; -- 1 - фронт ack_rd
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signal fack_wr_clr : std_logic; -- 1 - сброс fack_wr
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signal fack_rd_clr : std_logic; -- 1 - сброс fack_rd
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signal pio_read : std_logic; -- строб записи в c_pio
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signal start_rd : std_logic; -- 1 - запуск счётчика cnt_rd
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signal c_rst : std_logic; -- 0 - сброс тетрады
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signal cmd_rdy : std_logic; -- 1 - готовность тетрады к выполнению команды
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--
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signal s_pio_in : std_logic_vector(15 downto 0);
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signal s_pio_out : std_logic_vector(15 downto 0);
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signal lvds_pio_in : std_logic_vector(15 downto 0);
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signal lvds_pio_out : std_logic_vector(15 downto 0);
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signal s_pio_wr : std_logic; -- строб записи
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signal s_pio_rd : std_logic; -- строб чтения
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signal s_ack_wr : std_logic; -- подтверждение записи
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signal s_ack_rd : std_logic; -- подтверждение чтения
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signal ack_wr_lvds : std_logic;
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signal ack_rd_lvds : std_logic;
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signal pcout : std_logic;
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signal pio_en : std_logic;
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signal s_pio_wr_lvds : std_logic;
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begin
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xstatus: ctrl_buft16 port map(
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t => cmd.status_cs,
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i => c_status,
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o => cmd_data_out );
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cmd_data_out2<=c_status;
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xdata: ctrl_buft16 port map(
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t => cmd.data_cs,
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i => c_pio,
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o => data_out );
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data_out2<=c_pio;
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data_out2 <= c_pio;
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cmd_data_out2 <= c_status;
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data_out2<=c_pio;
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pr_mode0: process( reset, clk ) begin
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if( reset='0' ) then
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c_mode0<=(others=>'0');
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elsif( rising_edge( clk ) ) then
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if( cmd.cmd_data_we='1' ) then
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if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
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case cmd.adr( 3 downto 0 ) is
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when "0000" => c_mode0<=cmd_data_in;
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when others=>null;
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end case;
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end if;
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end if;
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end if;
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end process;
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c_rst <= reset and ( not c_mode0(0) );
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pr_reg: process( c_rst, clk )
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begin
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if( c_rst='0' ) then
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c_mode1 <=(others=>'0');
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c_mode2 <=(others=>'0');
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c_mask <=(others=>'0');
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c_inv <=(others=>'0');
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elsif( rising_edge( clk ) ) then
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if( cmd.cmd_data_we='1' ) then
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if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then
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case cmd.adr( 3 downto 0 ) is
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when "0001" => c_mask( 12 downto 9 )<=cmd_data_in( 12 downto 9 );
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when "0010" => c_inv( 12 downto 9 )<=cmd_data_in( 12 downto 9 );
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when "1001" => c_mode1<=cmd_data_in;
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when "1010" => c_mode2<=cmd_data_in;
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when others=>null;
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end case;
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end if;
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end if;
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end if;
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end process;
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c_status(1)<='0';
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c_status(2)<='0';
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c_status(3)<='0';
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c_status(4)<='0';
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c_status(5)<='0';
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c_status(6)<='0';
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c_status(7)<='0';
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c_status(8)<='0';
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c_status(13)<='0';
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c_status(14)<='0';
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c_status(15)<='0';
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c_status(11)<=fack_wr;
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c_status(12)<=fack_rd;
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pr_status: process( clk ) begin
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if( rising_edge( clk ) ) then
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c_status(0)<=cmd_rdy;
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c_status(9)<=s_ack_wr;
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c_status(10)<=s_ack_rd;
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end if;
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end process;
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c_flag<=c_status( 12 downto 9 ) xor c_inv;
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c_irq<= c_flag and c_mask;
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pr_irq: process( c_irq, clk )
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variable v: std_logic;
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begin
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v:='0';
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for i in 9 to 12 loop
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v:=v or c_irq( i );
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end loop;
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if( rising_edge( clk ) ) then
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bx_irq<=v and c_mode0(2);
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end if;
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end process;
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pr_s_pio_wr: process( c_rst, clk ) begin
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if( c_rst='0' ) then
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cnt_wr<=(others=>'0');
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elsif( rising_edge( clk ) ) then
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if( cmd.data_we='1' ) then
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cnt_wr<=c_mode2( 7 downto 0 );
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elsif( cnt_wr_z='0' ) then
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cnt_wr<=cnt_wr-1;
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end if;
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end if;
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end process;
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cnt_wr_z<='1' when cnt_wr=x"00" else '0';
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s_pio_wr<=cnt_wr_z or not c_rst;
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--pr_s_pio_rd: process( c_rst, clk ) begin
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-- if( c_rst='0' ) then
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-- cnt_rd<=(others=>'0');
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-- elsif( rising_edge( clk ) ) then
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326 |
|
|
-- if( start_rd='1' ) then
|
327 |
|
|
-- cnt_rd<=c_mode2( 15 downto 8 );
|
328 |
|
|
-- elsif( cnt_rd_z='0' ) then
|
329 |
|
|
-- cnt_rd<=cnt_rd-1;
|
330 |
|
|
-- end if;
|
331 |
|
|
-- end if;
|
332 |
|
|
--end process;
|
333 |
|
|
|
334 |
|
|
pr_s_pio_rd: process( start_rd, c_rst, clk )
|
335 |
|
|
begin
|
336 |
|
|
if( c_rst='0' ) then
|
337 |
|
|
cnt_rd<=(others=>'0');
|
338 |
|
|
elsif( start_rd='1' ) then
|
339 |
|
|
cnt_rd<=c_mode2( 15 downto 8 );
|
340 |
|
|
elsif( rising_edge( clk ) ) then
|
341 |
|
|
if( cnt_rd_z='0' ) then
|
342 |
|
|
cnt_rd<=cnt_rd-1;
|
343 |
|
|
end if;
|
344 |
|
|
end if;
|
345 |
|
|
end process;
|
346 |
|
|
|
347 |
|
|
cnt_rd_z<='1' when cnt_rd=x"00" else '0';
|
348 |
|
|
|
349 |
|
|
s_pio_rd<=cnt_rd_z or not c_rst;
|
350 |
|
|
|
351 |
|
|
pr_fack_wr: process( c_rst, s_ack_wr, fack_wr_clr ) begin
|
352 |
|
|
if( c_rst='0' or fack_wr_clr='1' ) then
|
353 |
|
|
fack_wr<='0';
|
354 |
|
|
elsif( rising_edge( s_ack_wr ) ) then
|
355 |
|
|
fack_wr<='1';
|
356 |
|
|
end if;
|
357 |
|
|
end process;
|
358 |
|
|
|
359 |
|
|
pr_fack_rd: process( c_rst, s_ack_rd, fack_rd_clr ) begin
|
360 |
|
|
if( c_rst='0' or fack_rd_clr='1' ) then
|
361 |
|
|
fack_rd<='0';
|
362 |
|
|
elsif( rising_edge( s_ack_rd ) ) then
|
363 |
|
|
fack_rd<='1';
|
364 |
|
|
end if;
|
365 |
|
|
end process;
|
366 |
|
|
|
367 |
|
|
--------------------------------------------------------------------
|
368 |
|
|
|
369 |
|
|
pr_start_rd: process( c_rst, clk ) begin
|
370 |
|
|
if( c_rst='0' ) then
|
371 |
|
|
start_rd<='0';
|
372 |
|
|
elsif( rising_edge( clk ) ) then
|
373 |
|
|
if( c_mode1(2)='0' ) then -- внутренняя синхронизация
|
374 |
|
|
if( cmd.cmd_data_we='1' and cmd.adr(9)='1' and cmd.adr(8)='0'
|
375 |
|
|
and cmd.adr(0)='1' ) then
|
376 |
|
|
start_rd<='1';
|
377 |
|
|
else
|
378 |
|
|
start_rd<='0';
|
379 |
|
|
end if;
|
380 |
|
|
else -- внешняя синхронизация
|
381 |
|
|
start_rd<=not cmd.data_cs;
|
382 |
|
|
end if;
|
383 |
|
|
end if;
|
384 |
|
|
end process;
|
385 |
|
|
|
386 |
|
|
pr_fack_clr: process( c_rst, clk )
|
387 |
|
|
variable v0, v1: std_logic;
|
388 |
|
|
begin
|
389 |
|
|
if( c_rst='0' ) then
|
390 |
|
|
fack_wr_clr<='0';
|
391 |
|
|
fack_rd_clr<='0';
|
392 |
|
|
elsif( rising_edge( clk ) ) then
|
393 |
|
|
v0:='0'; v1:='0';
|
394 |
|
|
|
395 |
|
|
if( c_mode1(2)='0' ) then
|
396 |
|
|
if( cmd.cmd_data_we='1' ) then
|
397 |
|
|
if( cmd.adr(9)='1' and cmd.adr(8)='0' and cmd.adr(0)='0' ) then
|
398 |
|
|
v1:=cmd_data_in( 12 );
|
399 |
|
|
end if;
|
400 |
|
|
end if;
|
401 |
|
|
else
|
402 |
|
|
v1:=not cmd.data_cs;
|
403 |
|
|
end if;
|
404 |
|
|
|
405 |
|
|
if( cmd.cmd_data_we='1' ) then
|
406 |
|
|
if( cmd.adr(9)='1' and cmd.adr(8)='0' and cmd.adr(0)='0' ) then
|
407 |
|
|
v0:=cmd_data_in( 11 );
|
408 |
|
|
end if;
|
409 |
|
|
end if;
|
410 |
|
|
|
411 |
|
|
fack_wr_clr<=v0;
|
412 |
|
|
fack_rd_clr<=v1;
|
413 |
|
|
|
414 |
|
|
end if;
|
415 |
|
|
end process;
|
416 |
|
|
|
417 |
|
|
cmd_rdy <= cnt_wr_z and (cnt_rd_z or c_mode1(3)) ;
|
418 |
|
|
|
419 |
|
|
pr_pio_out: process( c_rst, clk ) begin
|
420 |
|
|
if( c_rst='0' ) then
|
421 |
|
|
s_pio_out<=(others=>'0');
|
422 |
|
|
elsif( rising_edge( clk ) ) then
|
423 |
|
|
if( cmd.data_we='1' ) then
|
424 |
|
|
s_pio_out<=data_in;
|
425 |
|
|
end if;
|
426 |
|
|
end if;
|
427 |
|
|
end process;
|
428 |
|
|
|
429 |
|
|
pr_c_pio: process( c_rst, pio_read ) begin
|
430 |
|
|
if( c_rst='0' ) then
|
431 |
|
|
c_pio<=(others=>'0');
|
432 |
|
|
elsif( rising_edge( pio_read ) ) then
|
433 |
|
|
c_pio<=s_pio_in;
|
434 |
|
|
end if;
|
435 |
|
|
end process;
|
436 |
|
|
|
437 |
|
|
process(c_mode1(3 downto 2),cnt_rd_z,s_ack_rd,clk )
|
438 |
|
|
begin
|
439 |
|
|
case c_mode1(3 downto 2) is
|
440 |
|
|
when "00" => pio_read <= cnt_rd_z;
|
441 |
|
|
when "01" => pio_read <= s_ack_rd;
|
442 |
|
|
when "10" => pio_read <= clk;
|
443 |
|
|
when others => null;
|
444 |
|
|
end case;
|
445 |
|
|
end process;
|
446 |
|
|
|
447 |
|
|
pio_out <=lvds_pio_out when c_mode1(10)='1' else s_pio_out;
|
448 |
|
|
|
449 |
|
|
s_pio_in <=lvds_pio_in when c_mode1(10)='1' else pio_in;
|
450 |
|
|
|
451 |
|
|
gen_pio: for ii in 0 to 7 generate
|
452 |
|
|
lvds_pio_out(ii*2)<= s_pio_out(ii);
|
453 |
|
|
lvds_pio_in(ii) <= pio_in(2*ii);
|
454 |
|
|
end generate;
|
455 |
|
|
|
456 |
|
|
lvds_pio_out(9)<='1'; --pen0
|
457 |
|
|
lvds_pio_out(11)<='0'; --pen1
|
458 |
|
|
lvds_pio_out(13)<=c_mode1(0);
|
459 |
|
|
lvds_pio_out(15)<=c_mode1(1);
|
460 |
|
|
|
461 |
|
|
|
462 |
|
|
|
463 |
|
|
|
464 |
|
|
pio_enable<=pio_en; -- not c_mode1(11);
|
465 |
|
|
|
466 |
|
|
gen_en1: if use_enable=2 generate pio_en <= not c_mode1(11); end generate;
|
467 |
|
|
gen_en2: if use_enable=1 generate pio_en <= '0'; end generate;
|
468 |
|
|
|
469 |
|
|
pio_wr <= s_pio_wr when c_mode1(10)='0' else s_pio_wr_lvds;
|
470 |
|
|
pio_rd <= s_pio_rd;
|
471 |
|
|
s_ack_wr <= ack_wr when c_mode1(10)='0' else ack_wr_lvds ;
|
472 |
|
|
s_ack_rd <= ack_rd when c_mode1(10)='0' else ack_rd_lvds ;
|
473 |
|
|
|
474 |
|
|
process(c_mode1(13), pen1_in)
|
475 |
|
|
begin
|
476 |
|
|
if c_mode1(13) ='0' then
|
477 |
|
|
ack_wr_lvds<=pen1_in; ack_rd_lvds<=ack_rd;
|
478 |
|
|
else
|
479 |
|
|
ack_rd_lvds<=pen1_in; ack_wr_lvds<=ack_rd;
|
480 |
|
|
end if;
|
481 |
|
|
end process;
|
482 |
|
|
|
483 |
|
|
s_pio_wr_lvds <= s_pio_wr when c_mode1(12)='0' else s_pio_rd;
|
484 |
|
|
|
485 |
|
|
pcout<=s_pio_rd when c_mode1(12)='0' else s_pio_wr;
|
486 |
|
|
|
487 |
|
|
pen0 <= pcout when c_mode1(10)='1' else not c_mode1(0);
|
488 |
|
|
pen1 <= not c_mode1(1);
|
489 |
|
|
|
490 |
|
|
pio_oe0 <= not c_mode1(0) or pio_en;
|
491 |
|
|
pio_oe1 <= not c_mode1(1) or pio_en;
|
492 |
|
|
lvds <= not c_mode1(1) or pio_en when c_mode1(10) ='0' else pio_en;
|
493 |
|
|
|
494 |
|
|
pen1_oe<=c_mode1(10) or pio_en;
|
495 |
|
|
|
496 |
|
|
end trd_pio_std_v4;
|
497 |
|
|
|