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--
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-- Title : ctrl_start_v2
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-- Author : Dmitry Smekhov
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-- Company : Instrumental System
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--
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-- Version : 1.6
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Каталог : rtl_s2e - Реализация для Spartan-2E
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-- rtl_v2 - Реализация для Virtex-II
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Description : Выбор тактовой частоты и сигнала старта
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--
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-- Модификация 2. Не используются счётчики CNT0, CNT1, CNT2
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Version 1.6 28.11.2006
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-- Исправлено формирование сигналов start_a_tr_clr и start_a_tr (по аналогии с ctrl_start_v4)
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-- (Соколов)
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--
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-- Version 1.5 16.02.2006
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-- Исправлено формирование сигнала старта в программном режиме
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-- и установленным битом триггерного старта
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--
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--
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-- Version 1.4 28.04.2004
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-- Исправлено формирование сигнала старта в программном режиме
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-- и установленным битом инверсии старта.
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-- Добавлено описание пакета ctrl_start_v2_pkg.
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--
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-- Version 1.3 19.01.2004
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-- Исправлено формирование тактовой частоты в режиме ADM_MSYNC
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--
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-- Version 1.2 25.12.2003
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-- Исправлено формирование сигнала старта в режиме Slave
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--
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-- Version 1.1 22.12.2003
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-- Исправлена схема формирования триггерного старта
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--
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---------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.std_logic_unsigned.all;
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package ctrl_start_v2_pkg is
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component ctrl_start_v2 is
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port(
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reset: in std_logic; -- 0 - сброс
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mode0: in std_logic_vector( 15 downto 0 ); -- регистр MODE0
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stmode: in std_logic_vector( 15 downto 0 ); -- регистр STMODE
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fmode: in std_logic_vector( 5 downto 0 ); -- регистр FMODE
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fdiv: in std_logic_vector( 15 downto 0 ); -- регистр FDIV
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fdiv_we: in std_logic; -- 1 - запись в регистр FDIV
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b_clk: in std_logic_vector( 15 downto 0 ); -- входы тактовой частоты
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b_start: in std_logic_vector( 15 downto 0 ); -- входы сигнала START
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bx_clk: out std_logic; -- выход тактовой частоты
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bx_start: out std_logic; -- выход сигнала start синхронный с bx_clk
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bx_start_a: out std_logic; -- асинхронный выход сигнала start
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bx_start_sync: out std_logic; -- импульс синхронизации
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goe0: out std_logic; -- включение генератора 60MHz
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goe1: out std_logic -- включение генератора 50MHz
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);
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end component;
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end package ctrl_start_v2_pkg;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.std_logic_unsigned.all;
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entity ctrl_start_v2 is
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port(
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reset: in std_logic; -- 0 - сброс
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mode0: in std_logic_vector( 15 downto 0 ); -- регистр MODE0
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stmode: in std_logic_vector( 15 downto 0 ); -- регистр STMODE
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fmode: in std_logic_vector( 5 downto 0 ); -- регистр FMODE
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fdiv: in std_logic_vector( 15 downto 0 ); -- регистр FDIV
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fdiv_we: in std_logic; -- 1 - запись в регистр FDIV
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b_clk: in std_logic_vector( 15 downto 0 ); -- входы тактовой частоты
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b_start: in std_logic_vector( 15 downto 0 ); -- входы сигнала START
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bx_clk: out std_logic; -- выход тактовой частоты
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bx_start: out std_logic; -- выход сигнала start синхронный с bx_clk
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bx_start_a: out std_logic; -- асинхронный выход сигнала start
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bx_start_sync: out std_logic; -- импульс синхронизации
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goe0: out std_logic; -- включение генератора 60MHz
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goe1: out std_logic -- включение генератора 50MHz
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);
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end ctrl_start_v2;
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architecture ctrl_start_v2 of ctrl_start_v2 is
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signal clki: std_logic; -- выбранный опорный сигнал
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signal clko_cnt: std_logic; -- сигнал с выхода счётчика
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signal clko: std_logic; -- сформированный сигнал
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signal clk_cnt: std_logic_vector( 15 downto 0 ); -- счётчик тактовой частоты
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signal clk_cnt_z, clk_cnt_z1 : std_logic; -- 1 - clk_cnt=0
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signal clk_cnt_half: std_logic; -- 1 - clk_cnt = fdiv/2
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signal clk_div1: std_logic; -- 1 - fdiv=1
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signal xcnt0: std_logic_vector( 15 downto 0 ); -- счётчик начальной задержки
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signal xcnt1: std_logic_vector( 15 downto 0 ); -- счётчик принимаемых слов
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signal xcnt2: std_logic_vector( 15 downto 0 ); -- счётчик пропускаемых слов
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signal xcnt0_z: std_logic; -- 1 - xcnt0=x"0000"
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signal xcnt1_z: std_logic; -- 1 - xcnt1=x"0000"
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signal xcnt2_z: std_logic; -- 1 - xcnt2=x"0000"
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signal start_a: std_logic; -- 0 - асинхронный старт
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signal start_a_tr, start_a_tr1: std_logic; -- 0 - асинхронный триггерный страт
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signal start_a_tr_clr: std_logic;
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signal start_i, start_i1: std_logic; -- 0 - выбранный источник сторта
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signal stop_i, stop_i1: std_logic; -- 0 - выбранный источник останова
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signal start_s, start_si: std_logic; -- 0 - синхронный старт
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signal start_cnt0: std_logic; -- 1 - блокировка на время работы счётчика 0
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signal start_cnt12: std_logic; -- 1 - блокировка на время работы счётчиков 1 и 2
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signal xcnt1_start: std_logic; -- 1 - разрешение работы счётчика xcnt1
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signal xcnt2_start: std_logic; -- 1 - разрешение работы счётчика xcnt2
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signal adcen: std_logic; -- 1 - программный старт
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signal start_o: std_logic; -- сформированный сигнал синхронного старта
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signal clk_clr: std_logic; -- 1 - сброс счётчика тактовой частоты
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signal clk_clr_cl0: std_logic; -- 1 - сброс clk_clr
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signal clk_clr_block: std_logic; -- 1 - блокировка сброса
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signal start_prog: std_logic;
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signal prog_start: std_logic; -- 1 - выбран программный старт
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begin
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adcen <= mode0(5);
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pr_clk: process( b_clk, fmode ) is
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begin
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case fmode( 3 downto 0 ) is
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when "0000" => clki <= b_clk(0);
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when "0001" => clki <= b_clk(1);
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when "0010" => clki <= b_clk(2);
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when "0011" => clki <= b_clk(3);
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when "0100" => clki <= b_clk(4);
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when "0101" => clki <= b_clk(5);
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when "0110" => clki <= b_clk(6);
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when "0111" => clki <= b_clk(7);
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when "1000" => clki <= b_clk(8);
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when "1001" => clki <= b_clk(9);
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when "1010" => clki <= b_clk(10);
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when "1011" => clki <= b_clk(11);
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when "1100" => clki <= b_clk(12);
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when "1101" => clki <= b_clk(13);
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when "1110" => clki <= b_clk(14);
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when "1111" => clki <= b_clk(15);
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when others => null;
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end case;
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end process;
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goe0<='1' when fmode( 3 downto 0 )="0001" else '0';
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goe1<='1' when fmode( 3 downto 0 )="0010" else '0';
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pr_cnt_clk: process( reset, start_a, fdiv_we, fmode, clki ) is
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begin
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if( reset='0' or ( clk_clr='1' and fmode(5)='1' ) or fdiv_we='1' ) then
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--clk_cnt<=(others=>'0');
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clk_cnt<=x"0001";
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elsif( rising_edge( clki ) ) then
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if( clk_cnt_z='1' ) then
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clk_cnt<=fdiv;
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else
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clk_cnt<=clk_cnt-1;
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end if;
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end if;
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end process;
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clk_div1<='1' when fdiv=x"0001" else '0';
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clk_cnt_z<='1' when clk_cnt=x"0001" else '0';
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clk_cnt_half<='1' when clk_cnt( 14 downto 0 )=fdiv( 15 downto 1 ) else '0';
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pr_clk_cnt_z1: process( clki ) begin
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if( rising_edge( clki ) ) then
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clk_cnt_z1<=clk_cnt_z;
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end if;
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end process;
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pr_clko_cnt: process( clki, clk_cnt, clk_div1, clk_cnt_half ) is
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begin
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if( clk_div1='1' ) then
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clko_cnt<=clki;
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elsif( rising_edge( clki ) ) then
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if( clk_cnt_z1='1' ) then clko_cnt<='0';
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elsif( clk_cnt_half='1' ) then clko_cnt<='1';
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end if;
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end if;
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end process;
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pr_clko: process( mode0, b_clk, clko_cnt ) is
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begin
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if( mode0(4)='0' ) then
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clko<=b_clk(4);
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elsif( mode0(6)='1' ) then
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clko<=b_clk(7);
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else
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clko<=clko_cnt;
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end if;
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end process;
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bx_clk<=clko;
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-- Старт
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pr_starto: process( mode0, b_start, start_s ) is
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begin
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if( mode0(4)='0' ) then -- SLAVE
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start_o<=b_start(4) or not mode0(5);
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else
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start_o<=start_s;
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end if;
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end process;
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bx_start<=start_o;
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pr_start_i: process( stmode, b_start, start_prog ) is
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begin
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case stmode( 3 downto 0 ) is
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when "0000" => start_i <= start_prog;
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when "0001" => start_i <= b_start(1);
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when "0010" => start_i <= b_start(2);
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when "0011" => start_i <= b_start(3);
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when "0100" => start_i <= b_start(4);
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when "0101" => start_i <= b_start(5);
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when "0110" => start_i <= b_start(6);
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when "0111" => start_i <= b_start(7);
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when "1000" => start_i <= b_start(8);
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when "1001" => start_i <= b_start(9);
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when "1010" => start_i <= b_start(10);
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when "1011" => start_i <= b_start(11);
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when "1100" => start_i <= b_start(12);
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when "1101" => start_i <= b_start(13);
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when "1110" => start_i <= b_start(14);
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when "1111" => start_i <= b_start(15);
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when others => null;
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end case;
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end process;
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start_prog<=( not mode0(5) ) xor stmode(6) when rising_edge(b_clk(0) );
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--start_i1<= ( start_i xor stmode(6) ) or ( not mode0(5) );
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start_i1<= ( start_i xor stmode(6) );
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pr_stop_i: process( stmode, b_start, mode0(5) ) is
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begin
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case stmode( 11 downto 8 ) is
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when "0000" => stop_i <= ( not mode0(5) ) xor stmode(14);
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when "0001" => stop_i <= b_start(1);
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when "0010" => stop_i <= b_start(2);
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when "0011" => stop_i <= b_start(3);
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when "0100" => stop_i <= b_start(4);
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when "0101" => stop_i <= b_start(5);
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when "0110" => stop_i <= b_start(6);
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when "0111" => stop_i <= b_start(7);
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when "1000" => stop_i <= b_start(8);
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when "1001" => stop_i <= b_start(9);
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when "1010" => stop_i <= b_start(10);
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when "1011" => stop_i <= b_start(11);
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when "1100" => stop_i <= b_start(12);
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when "1101" => stop_i <= b_start(13);
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when "1110" => stop_i <= b_start(14);
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when "1111" => stop_i <= b_start(15);
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when others => null;
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end case;
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end process;
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stop_i1<= stop_i xor stmode(14);
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pr_start_a_tr: process( mode0, start_a_tr_clr, start_i1 )
|
| 297 |
|
|
begin
|
| 298 |
|
|
if( mode0(5)='0' or start_a_tr_clr='1' ) then
|
| 299 |
|
|
start_a_tr<='1';
|
| 300 |
|
|
elsif( prog_start='1' and mode0(5)='1' ) then
|
| 301 |
|
|
start_a_tr<='0';
|
| 302 |
|
|
elsif( falling_edge( start_i1 ) ) then
|
| 303 |
|
|
start_a_tr<='0';
|
| 304 |
|
|
end if;
|
| 305 |
|
|
end process;
|
| 306 |
|
|
|
| 307 |
|
|
|
| 308 |
|
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pr_start_a_tr1: process( b_clk ) begin
|
| 309 |
|
|
if( rising_edge( b_clk(0) ) ) then
|
| 310 |
|
|
start_a_tr1<=start_a_tr;
|
| 311 |
|
|
end if;
|
| 312 |
|
|
end process;
|
| 313 |
|
|
|
| 314 |
|
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pr_start_a_tr_clr: process( mode0, prog_start, start_a_tr1, stop_i1 ) begin
|
| 315 |
|
|
if( start_a_tr1='1' or mode0(5)='0' or prog_start='1' ) then
|
| 316 |
|
|
start_a_tr_clr<='0';
|
| 317 |
|
|
elsif( rising_edge( stop_i1 ) ) then
|
| 318 |
|
|
start_a_tr_clr<='1';
|
| 319 |
|
|
end if;
|
| 320 |
|
|
end process;
|
| 321 |
|
|
|
| 322 |
|
|
|
| 323 |
|
|
--start_a<=start_a_tr when stmode(7)='1' else start_i1;
|
| 324 |
|
|
start_a<=start_a_tr when stmode(7)='1' else start_i1 or ( not mode0(5) );
|
| 325 |
|
|
bx_start_a<=start_a;
|
| 326 |
|
|
|
| 327 |
|
|
pr_start_si: process( clko ) begin
|
| 328 |
|
|
if( rising_edge( clko ) ) then
|
| 329 |
|
|
start_si<=start_a;
|
| 330 |
|
|
end if;
|
| 331 |
|
|
end process;
|
| 332 |
|
|
|
| 333 |
|
|
start_s<=start_si;
|
| 334 |
|
|
|
| 335 |
|
|
|
| 336 |
|
|
|
| 337 |
|
|
pr_clk_clr: process( reset, clk_clr_cl0, start_a ) begin
|
| 338 |
|
|
if( reset='0' or clk_clr_cl0='1' ) then
|
| 339 |
|
|
clk_clr<='0';
|
| 340 |
|
|
elsif( falling_edge( start_a ) ) then
|
| 341 |
|
|
clk_clr<='1';
|
| 342 |
|
|
end if;
|
| 343 |
|
|
end process;
|
| 344 |
|
|
|
| 345 |
|
|
bx_start_sync <= clk_clr;
|
| 346 |
|
|
|
| 347 |
|
|
pr_clk_cl0: process( reset, b_clk(0) ) begin
|
| 348 |
|
|
if( reset='0' ) then
|
| 349 |
|
|
clk_clr_cl0<='0';
|
| 350 |
|
|
elsif( rising_edge( b_clk(0) ) ) then
|
| 351 |
|
|
if( clk_clr='1' and clk_clr_block='0' ) then
|
| 352 |
|
|
clk_clr_cl0<='1';
|
| 353 |
|
|
else
|
| 354 |
|
|
clk_clr_cl0<='0';
|
| 355 |
|
|
end if;
|
| 356 |
|
|
end if;
|
| 357 |
|
|
end process;
|
| 358 |
|
|
|
| 359 |
|
|
|
| 360 |
|
|
pr_clk_clr_block: process( reset, b_clk(0) )
|
| 361 |
|
|
begin
|
| 362 |
|
|
if( reset='0' ) then
|
| 363 |
|
|
clk_clr_block<='0';
|
| 364 |
|
|
elsif( rising_edge( b_clk(0) ) ) then
|
| 365 |
|
|
if( clk_cnt_half='1' and clk_clr_block='0' ) then
|
| 366 |
|
|
clk_clr_block<='1';
|
| 367 |
|
|
else
|
| 368 |
|
|
clk_clr_block<='0';
|
| 369 |
|
|
end if;
|
| 370 |
|
|
end if;
|
| 371 |
|
|
end process;
|
| 372 |
|
|
|
| 373 |
|
|
|
| 374 |
|
|
end ctrl_start_v2;
|
