1 |
17 |
dsmv |
-------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- Title : pcie_core64_wishbone_m8
|
4 |
|
|
-- Author : Dmitry Smekhov
|
5 |
|
|
-- Company : Instrumental Systems
|
6 |
|
|
-- E-mail : dsmv@insys.ru
|
7 |
|
|
--
|
8 |
|
|
-- Version : 1.0
|
9 |
|
|
--
|
10 |
|
|
-------------------------------------------------------------------------------
|
11 |
|
|
--
|
12 |
|
|
-- Description : PCI Express controller
|
13 |
|
|
-- Modification 8 - Wishbone - Virtex 5 PCI Express v1.1 x8
|
14 |
|
|
--
|
15 |
|
|
-------------------------------------------------------------------------------
|
16 |
|
|
--
|
17 |
|
|
-- Version 1.0 20.04.2013
|
18 |
|
|
-- Created from pcie_core64_wishbone v1.3
|
19 |
|
|
--
|
20 |
|
|
-------------------------------------------------------------------------------
|
21 |
|
|
|
22 |
|
|
library ieee;
|
23 |
|
|
use ieee.std_logic_1164.all;
|
24 |
|
|
|
25 |
|
|
package pcie_core64_wishbone_m8_pkg is
|
26 |
|
|
|
27 |
|
|
component pcie_core64_wishbone_m8 is
|
28 |
|
|
generic
|
29 |
|
|
(
|
30 |
|
|
Device_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
|
31 |
|
|
Revision : in std_logic_vector( 15 downto 0 ):=x"0000"; -- версия модуля
|
32 |
|
|
PLD_VER : in std_logic_vector( 15 downto 0 ):=x"0000"; -- версия ПЛИС
|
33 |
|
|
|
34 |
|
|
is_simulation : integer:=0 --! 0 - synthesis, 1 - simulation
|
35 |
|
|
);
|
36 |
|
|
port
|
37 |
|
|
(
|
38 |
|
|
---- PCI-Express ----
|
39 |
|
|
txp : out std_logic_vector( 7 downto 0 );
|
40 |
|
|
txn : out std_logic_vector( 7 downto 0 );
|
41 |
|
|
|
42 |
|
|
rxp : in std_logic_vector( 7 downto 0 );
|
43 |
|
|
rxn : in std_logic_vector( 7 downto 0 );
|
44 |
|
|
|
45 |
|
|
mgt250 : in std_logic; -- reference clock 250 MHz from PCI_Express
|
46 |
|
|
|
47 |
|
|
perst : in std_logic; -- 0 - reset
|
48 |
|
|
|
49 |
|
|
px : out std_logic_vector( 7 downto 0 ); --! контрольные точки
|
50 |
|
|
|
51 |
|
|
pcie_lstatus : out std_logic_vector( 15 downto 0 ); -- регистр LSTATUS
|
52 |
|
|
pcie_link_up : out std_logic; -- 0 - завершена инициализация PCI-Express
|
53 |
|
|
|
54 |
|
|
---- Wishbone SYS_CON -----
|
55 |
|
|
o_wb_clk : out std_logic;
|
56 |
|
|
o_wb_rst : out std_logic;
|
57 |
|
|
---- Wishbone BUS -----
|
58 |
|
|
ov_wbm_addr : out std_logic_vector(31 downto 0);
|
59 |
|
|
ov_wbm_data : out std_logic_vector(63 downto 0);
|
60 |
|
|
ov_wbm_sel : out std_logic_vector( 7 downto 0);
|
61 |
|
|
o_wbm_we : out std_logic;
|
62 |
|
|
o_wbm_cyc : out std_logic;
|
63 |
|
|
o_wbm_stb : out std_logic;
|
64 |
|
|
ov_wbm_cti : out std_logic_vector( 2 downto 0); -- Cycle Type Identifier Address Tag
|
65 |
|
|
ov_wbm_bte : out std_logic_vector( 1 downto 0); -- Burst Type Extension Address Tag
|
66 |
|
|
|
67 |
|
|
iv_wbm_data : in std_logic_vector(63 downto 0);
|
68 |
|
|
i_wbm_ack : in std_logic;
|
69 |
|
|
i_wbm_err : in std_logic; -- error input - abnormal cycle termination
|
70 |
|
|
i_wbm_rty : in std_logic; -- retry input - interface is not ready
|
71 |
|
|
|
72 |
|
|
i_wdm_irq_0 : in std_logic;
|
73 |
|
|
iv_wbm_irq_dmar : in std_logic_vector( 1 downto 0)
|
74 |
|
|
|
75 |
|
|
);
|
76 |
|
|
end component pcie_core64_wishbone_m8;
|
77 |
|
|
|
78 |
|
|
end package pcie_core64_wishbone_m8_pkg;
|
79 |
|
|
-------------------------------------------------------------------------------
|
80 |
|
|
library ieee;
|
81 |
|
|
use ieee.std_logic_1164.all;
|
82 |
|
|
|
83 |
|
|
use work.core64_type_pkg.all;
|
84 |
|
|
use work.pcie_core64_m1_pkg.all;
|
85 |
|
|
use work.core64_pb_wishbone_pkg.all;
|
86 |
|
|
use work.block_pe_main_pkg.all;
|
87 |
|
|
|
88 |
32 |
dsmv |
library unisim;
|
89 |
|
|
use unisim.vcomponents.all;
|
90 |
|
|
|
91 |
17 |
dsmv |
entity pcie_core64_wishbone_m8 is
|
92 |
|
|
generic
|
93 |
|
|
(
|
94 |
|
|
Device_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
|
95 |
|
|
Revision : in std_logic_vector( 15 downto 0 ):=x"0000"; -- версия модуля
|
96 |
|
|
PLD_VER : in std_logic_vector( 15 downto 0 ):=x"0000"; -- версия ПЛИС
|
97 |
|
|
|
98 |
|
|
is_simulation : integer:=0 --! 0 - synthesis, 1 - simulation --! 0 - синтез, 1 - моделирование
|
99 |
|
|
);
|
100 |
|
|
port
|
101 |
|
|
(
|
102 |
|
|
---- PCI-Express ----
|
103 |
|
|
txp : out std_logic_vector( 7 downto 0 );
|
104 |
|
|
txn : out std_logic_vector( 7 downto 0 );
|
105 |
|
|
|
106 |
|
|
rxp : in std_logic_vector( 7 downto 0 );
|
107 |
|
|
rxn : in std_logic_vector( 7 downto 0 );
|
108 |
|
|
|
109 |
|
|
mgt250 : in std_logic; -- reference clock 250 MHz from PCI_Express
|
110 |
|
|
|
111 |
|
|
perst : in std_logic; -- 0 - reset
|
112 |
|
|
|
113 |
|
|
px : out std_logic_vector( 7 downto 0 ); --! контрольные точки
|
114 |
|
|
|
115 |
|
|
pcie_lstatus : out std_logic_vector( 15 downto 0 ); -- регистр LSTATUS
|
116 |
|
|
pcie_link_up : out std_logic; -- 0 - завершена инициализация PCI-Express
|
117 |
|
|
|
118 |
|
|
---- Wishbone SYS_CON -----
|
119 |
|
|
o_wb_clk : out std_logic;
|
120 |
|
|
o_wb_rst : out std_logic;
|
121 |
|
|
---- Wishbone BUS -----
|
122 |
|
|
ov_wbm_addr : out std_logic_vector(31 downto 0);
|
123 |
|
|
ov_wbm_data : out std_logic_vector(63 downto 0);
|
124 |
|
|
ov_wbm_sel : out std_logic_vector( 7 downto 0);
|
125 |
|
|
o_wbm_we : out std_logic;
|
126 |
|
|
o_wbm_cyc : out std_logic;
|
127 |
|
|
o_wbm_stb : out std_logic;
|
128 |
|
|
ov_wbm_cti : out std_logic_vector( 2 downto 0); -- Cycle Type Identifier Address Tag
|
129 |
|
|
ov_wbm_bte : out std_logic_vector( 1 downto 0); -- Burst Type Extension Address Tag
|
130 |
|
|
|
131 |
|
|
iv_wbm_data : in std_logic_vector(63 downto 0);
|
132 |
|
|
i_wbm_ack : in std_logic;
|
133 |
|
|
i_wbm_err : in std_logic; -- error input - abnormal cycle termination
|
134 |
|
|
i_wbm_rty : in std_logic; -- retry input - interface is not ready
|
135 |
|
|
|
136 |
|
|
i_wdm_irq_0 : in std_logic;
|
137 |
|
|
iv_wbm_irq_dmar : in std_logic_vector( 1 downto 0)
|
138 |
|
|
|
139 |
|
|
);
|
140 |
|
|
end pcie_core64_wishbone_m8;
|
141 |
|
|
|
142 |
|
|
architecture pcie_core64_wishbone_m8 of pcie_core64_wishbone_m8 is
|
143 |
|
|
-------------------------------------------------------------------------------
|
144 |
|
|
--
|
145 |
|
|
-- BAR0 - блоки управления ----
|
146 |
|
|
signal bp_host_data : std_logic_vector( 31 downto 0 ); --! шина данных - выход
|
147 |
|
|
signal bp_data : std_logic_vector( 31 downto 0 ); --! шина данных - вход
|
148 |
|
|
signal bp_adr : std_logic_vector( 19 downto 0 ); --! адрес регистра внутри блока
|
149 |
|
|
signal bp_we : std_logic_vector( 3 downto 0 ); --! 1 - запись в регистры
|
150 |
|
|
signal bp_rd : std_logic_vector( 3 downto 0 ); --! 1 - чтение из регистров блока
|
151 |
|
|
signal bp_sel : std_logic_vector( 1 downto 0 ); --! номер блока для чтения
|
152 |
|
|
signal bp_reg_we : std_logic; --! 1 - запись в регистр по адресам 0x100000 - 0x1FFFFF
|
153 |
|
|
signal bp_reg_rd : std_logic; --! 1 - чтение из регистра по адресам 0x100000 - 0x1FFFFF
|
154 |
|
|
signal bp_irq : std_logic; --! 1 - запрос прерывания
|
155 |
|
|
|
156 |
|
|
signal pb_master : type_pb_master; --! запрос
|
157 |
|
|
signal pb_slave : type_pb_slave; --! ответ
|
158 |
|
|
|
159 |
|
|
signal pb_reset : std_logic;
|
160 |
|
|
signal brd_mode : std_logic_vector( 15 downto 0 );
|
161 |
|
|
|
162 |
|
|
signal bp0_data : std_logic_vector( 31 downto 0 );
|
163 |
|
|
-------------------------------------------------------------------------------
|
164 |
|
|
--
|
165 |
|
|
-- Declare Global SYS_CON stuff:
|
166 |
|
|
signal clk : std_logic;
|
167 |
|
|
signal reset : std_logic;
|
168 |
|
|
signal dcm_rst_out : std_logic;
|
169 |
|
|
signal reset_p : std_logic;
|
170 |
|
|
signal reset_p_z1 : std_logic;
|
171 |
|
|
signal reset_p_z2 : std_logic;
|
172 |
32 |
dsmv |
|
173 |
|
|
signal clk125x : std_logic:='0';
|
174 |
|
|
signal clk125 : std_logic;
|
175 |
|
|
|
176 |
17 |
dsmv |
-------------------------------------------------------------------------------
|
177 |
|
|
begin
|
178 |
|
|
-------------------------------------------------------------------------------
|
179 |
|
|
--
|
180 |
|
|
-- Instantiate CORE64_M6 module with PB BUS:
|
181 |
|
|
--
|
182 |
|
|
CORE : pcie_core64_m1
|
183 |
|
|
generic map
|
184 |
|
|
(
|
185 |
|
|
is_simulation => is_simulation --! 0 - synthesis, 1 - simulation
|
186 |
|
|
)
|
187 |
|
|
port map
|
188 |
|
|
(
|
189 |
|
|
---- PCI-Express ----
|
190 |
|
|
txp => txp,
|
191 |
|
|
txn => txn,
|
192 |
|
|
|
193 |
|
|
rxp => rxp,
|
194 |
|
|
rxn => rxn,
|
195 |
|
|
|
196 |
|
|
mgt250 => mgt250,
|
197 |
|
|
|
198 |
|
|
perst => perst,
|
199 |
|
|
|
200 |
|
|
px => px,
|
201 |
|
|
|
202 |
|
|
pcie_lstatus => pcie_lstatus,
|
203 |
|
|
pcie_link_up => pcie_link_up,
|
204 |
|
|
|
205 |
|
|
---- Локальная шина ----
|
206 |
|
|
clk_out => clk, -- S6 PCIE x1 module clock output
|
207 |
|
|
reset_out => reset, --
|
208 |
|
|
dcm_rstp => dcm_rst_out, -- S6 PCIE x1 module INV trn_reset_n_c
|
209 |
|
|
|
210 |
|
|
---- BAR1 (PB bus) ----
|
211 |
32 |
dsmv |
aclk => clk125,
|
212 |
17 |
dsmv |
aclk_lock => '1', --
|
213 |
|
|
pb_master => pb_master, --
|
214 |
|
|
pb_slave => pb_slave, --
|
215 |
|
|
|
216 |
|
|
---- BAR0 (to PE_MAIN) - блоки управления ----
|
217 |
|
|
bp_host_data => bp_host_data,
|
218 |
|
|
bp_data => bp_data,
|
219 |
|
|
bp_adr => bp_adr,
|
220 |
|
|
bp_we => bp_we,
|
221 |
|
|
bp_rd => bp_rd,
|
222 |
|
|
bp_sel => bp_sel,
|
223 |
|
|
bp_reg_we => bp_reg_we,
|
224 |
|
|
bp_reg_rd => bp_reg_rd,
|
225 |
|
|
bp_irq => bp_irq
|
226 |
|
|
|
227 |
|
|
);
|
228 |
|
|
|
229 |
32 |
dsmv |
clk125x <= not clk125x after 0.5 ns when rising_edge( clk );
|
230 |
|
|
xclk125: bufg port map( clk125, clk125x );
|
231 |
|
|
|
232 |
18 |
dsmv |
reset_p <= (not reset) or (not brd_mode(3));
|
233 |
32 |
dsmv |
reset_p_z1 <= reset_p after 1 ns when rising_edge( clk125 );
|
234 |
|
|
reset_p_z2 <= reset_p_z1 after 1 ns when rising_edge( clk125 );
|
235 |
17 |
dsmv |
|
236 |
|
|
-- Deal with CORE BP Input data:
|
237 |
|
|
bp_data <= bp0_data when bp_sel="00" else (others=>'0');
|
238 |
|
|
-------------------------------------------------------------------------------
|
239 |
|
|
--
|
240 |
|
|
-- Instantiate PE_MAIN module:
|
241 |
|
|
--
|
242 |
|
|
PE_MAIN : block_pe_main
|
243 |
|
|
generic map
|
244 |
|
|
(
|
245 |
|
|
Device_ID => Device_ID, -- идентификатор модуля
|
246 |
|
|
Revision => Revision, -- версия модуля
|
247 |
|
|
PLD_VER => PLD_VER, -- версия ПЛИС
|
248 |
|
|
BLOCK_CNT => x"0008" -- число блоков управления
|
249 |
|
|
)
|
250 |
|
|
port map
|
251 |
|
|
(
|
252 |
|
|
---- Global ----
|
253 |
|
|
reset_hr1 => reset, -- 0 - сброс
|
254 |
|
|
clk => clk, -- Тактовая частота PCIE x1 S6
|
255 |
|
|
pb_reset => pb_reset, -- 0 - сброс ведомой ПЛИС
|
256 |
|
|
|
257 |
|
|
---- HOST ----
|
258 |
|
|
bl_adr => bp_adr( 4 downto 0 ), -- адрес
|
259 |
|
|
bl_data_in => bp_host_data, -- данные
|
260 |
|
|
bl_data_out => bp0_data, -- данные
|
261 |
|
|
bl_data_we => bp_we(0), -- 1 - запись данных
|
262 |
|
|
|
263 |
|
|
---- Управление ----
|
264 |
|
|
brd_mode => brd_mode -- регистр BRD_MODE
|
265 |
|
|
|
266 |
|
|
);
|
267 |
|
|
-------------------------------------------------------------------------------
|
268 |
|
|
--
|
269 |
|
|
-- Instantiate PB BUS <-> WB BUS translator module:
|
270 |
|
|
--
|
271 |
|
|
PW_WB : core64_pb_wishbone
|
272 |
|
|
port map
|
273 |
|
|
(
|
274 |
|
|
reset => reset_p_z2, --! 1 - сброс
|
275 |
32 |
dsmv |
clk => clk125, --! тактовая частота локальной шины
|
276 |
17 |
dsmv |
|
277 |
|
|
---- BAR1 ----
|
278 |
|
|
pb_master => pb_master, --! запрос
|
279 |
|
|
pb_slave => pb_slave, --! ответ
|
280 |
|
|
|
281 |
|
|
---- Wishbone BUS -----
|
282 |
|
|
ov_wbm_addr => ov_wbm_addr,
|
283 |
|
|
ov_wbm_data => ov_wbm_data,
|
284 |
|
|
ov_wbm_sel => ov_wbm_sel,
|
285 |
|
|
o_wbm_we => o_wbm_we,
|
286 |
|
|
o_wbm_cyc => o_wbm_cyc,
|
287 |
|
|
o_wbm_stb => o_wbm_stb,
|
288 |
|
|
ov_wbm_cti => ov_wbm_cti, -- Cycle Type Identifier Address Tag
|
289 |
|
|
ov_wbm_bte => ov_wbm_bte, -- Burst Type Extension Address Tag
|
290 |
|
|
|
291 |
|
|
iv_wbm_data => iv_wbm_data,
|
292 |
|
|
i_wbm_ack => i_wbm_ack,
|
293 |
|
|
i_wbm_err => i_wbm_err, -- error input - abnormal cycle termination
|
294 |
|
|
i_wbm_rty => i_wbm_rty, -- retry input - interface is not ready
|
295 |
|
|
|
296 |
|
|
i_wdm_irq_0 => i_wdm_irq_0,
|
297 |
|
|
iv_wbm_irq_dmar => iv_wbm_irq_dmar
|
298 |
|
|
);
|
299 |
|
|
-------------------------------------------------------------------------------
|
300 |
|
|
--
|
301 |
|
|
-- Module Output route:
|
302 |
|
|
--
|
303 |
32 |
dsmv |
o_wb_clk <= clk125; -- route from PW_WB wrk clock
|
304 |
17 |
dsmv |
--
|
305 |
32 |
dsmv |
pr_o_wb_rst: process( reset_p, clk125 ) begin
|
306 |
17 |
dsmv |
if( reset_p='1' ) then
|
307 |
|
|
o_wb_rst <= '1' after 1 ns;
|
308 |
32 |
dsmv |
elsif( rising_edge( clk125 ) ) then
|
309 |
17 |
dsmv |
o_wb_rst <= reset_p_z2 after 1 ns;
|
310 |
|
|
end if;
|
311 |
|
|
end process;
|
312 |
|
|
|
313 |
|
|
|
314 |
|
|
-------------------------------------------------------------------------------
|
315 |
|
|
end pcie_core64_wishbone_m8;
|