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-------------------------------------------------------------------------------
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--
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-- Title : core64_pb_transaction
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.2
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Узел управления локальной шиной
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--
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-- pb_master.cmd - команда управления, сопровождается стробом stb0
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-- 0: - 1 запись данных
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-- 1: - 1 чтение данных
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-- 2: - 0 - одно слово, 1 - пакет 512 слов (4096 байт)
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.2 14.12.2011
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-- Добавлен lc_rd_cfg
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--
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---------------------------------------------------------------------------------
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--
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dsmv |
-- Version 1.1 28.09.2011 Dmitry Smekhov
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-- Добавлен сигнал pb_slave.complete
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.core64_type_pkg.all;
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package core64_pb_transaction_pkg is
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component core64_pb_transaction is
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port(
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reset : in std_logic; --! 0 - сброс
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clk : in std_logic; --! тактовая частота локальной шины - 266 МГц
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---- BAR1 ----
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pb_master : in type_pb_master; --! запрос
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pb_slave : out type_pb_slave; --! ответ
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---- локальная шина -----
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lc_adr : out std_logic_vector( 31 downto 0 ); --! шина адреса
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lc_host_data : out std_logic_vector( 63 downto 0 ); --! шина данных - выход
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lc_data : in std_logic_vector( 63 downto 0 ); --! шина данных - вход
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lc_wr : out std_logic; --! 1 - запись
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lc_rd : out std_logic; --! 1 - чтение, данные должны быть на шестой такт после rd
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lc_dma_req : in std_logic_vector( 1 downto 0 ); --! 1 - запрос DMA
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lc_irq : in std_logic; --! 1 - запрос прерывания
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lc_rd_cfg : in std_logic_vector( 3 downto 0 ):="0101" --! настройка задержки захвата данных по сигналу lc_rd
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);
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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use work.core64_type_pkg.all;
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entity core64_pb_transaction is
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port(
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reset : in std_logic; --! 0 - сброс
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clk : in std_logic; --! тактовая частота локальной шины - 266 МГц
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---- BAR1 ----
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pb_master : in type_pb_master; --! запрос
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pb_slave : out type_pb_slave; --! ответ
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---- локальная шина -----
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lc_adr : out std_logic_vector( 31 downto 0 ); --! шина адреса
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lc_host_data : out std_logic_vector( 63 downto 0 ); --! шина данных - выход
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lc_data : in std_logic_vector( 63 downto 0 ); --! шина данных - вход
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lc_wr : out std_logic; --! 1 - запись
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lc_rd : out std_logic; --! 1 - чтение, данные должны быть на шестой такт после rd
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lc_dma_req : in std_logic_vector( 1 downto 0 ); --! 1 - запрос DMA
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lc_irq : in std_logic; --! 1 - запрос прерывания
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lc_rd_cfg : in std_logic_vector( 3 downto 0 ):="0101" --! настройка задержки захвата данных по сигналу lc_rd
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);
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end core64_pb_transaction;
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architecture core64_pb_transaction of core64_pb_transaction is
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signal cnt_start : std_logic;
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signal cnt : std_logic_vector( 9 downto 0 );
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signal rstp : std_logic;
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signal rd_start : std_logic;
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signal rd_start_z : std_logic;
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signal rd_start_z1 : std_logic;
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signal stb1_z : std_logic;
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begin
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rstp <= not reset after 1 ns when rising_edge( clk );
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--rstp <= '1', '0' after 30 us;
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lc_adr <= pb_master.adr after 1 ns when rising_edge( clk );
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lc_host_data <= pb_master.data after 1 ns when rising_edge( clk );
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lc_wr <= pb_master.stb1 after 1 ns when rising_edge( clk );
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lc_rd <= rd_start after 1 ns when rising_edge( clk );
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pr_cnt: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( cnt_start='0' ) then
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if( pb_master.cmd(2)='0' ) then
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cnt <= "0111111111" after 1 ns;
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else
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cnt <= "0000000000" after 1 ns;
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end if;
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else
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cnt <= cnt + 1 after 1 ns;
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end if;
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end if;
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end process;
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pr_cnt_start: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( rstp='1' or cnt(9)='1' ) then
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cnt_start <= '0' after 1 ns;
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elsif( pb_master.cmd(1)='1' and pb_master.stb0='1' ) then
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cnt_start <= '1' after 1 ns;
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end if;
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end if;
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end process;
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rd_start <= cnt_start and not cnt(9);
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--xrdz: srl16 port map( q=>rd_start_z, clk=>clk, d=>rd_start, a3=>'0', a2=>'1', a1=>'0', a0=>'1' );
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xrdz: srl16 port map( q=>rd_start_z, clk=>clk, d=>rd_start, a3=>lc_rd_cfg(3), a2=>lc_rd_cfg(2), a1=>lc_rd_cfg(1), a0=>lc_rd_cfg(0) );
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pb_slave.stb0 <= pb_master.stb0 after 1 ns when rising_edge( clk );
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pb_slave.stb1 <= rd_start_z after 1 ns when rising_edge( clk );
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pb_slave.data <= lc_data after 1 ns when rising_edge( clk );
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pb_slave.dmar <= lc_dma_req;
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pb_slave.irq <= lc_irq;
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rd_start_z1 <= rd_start_z after 1 ns when rising_edge( clk );
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stb1_z <= pb_master.stb1 after 1 ns when rising_edge( clk );
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pb_slave.complete <= ((not rd_start_z) and rd_start_z1) or
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((not pb_master.stb1) and stb1_z ) after 1 ns
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when rising_edge( clk );
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pb_slave.ready <= '1';
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end core64_pb_transaction;
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