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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [components/] [rtl/] [core64_pb_wishbone.vhd] - Blame information for rev 2

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1 2 dsmv
-------------------------------------------------------------------------------
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--
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-- Title       : core64_pb_wishbone
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-- Author      : Dmitry Smekhov
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-- Company     : Instrumental Systems
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-- E-mail      : dsmv@insys.ru
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--
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-- Version     : 1.0
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Узел управления локальной шиной 
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--                                                                                              
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--              pb_master.cmd   - команда управления, сопровождается стробом stb0
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--                                      0:      - 1 запись данных
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--                                      1:  - 1 чтение данных
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--                                      2:  - 0 - одно слово, 1 - пакет 512 слов (4096 байт)
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--
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-------------------------------------------------------------------------------
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--
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--  Version 1.0  07.10.2011 Dmitry Smekhov
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--                               Создан из core64_pb_transaction v1.1
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--
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--  Version 1.1  14.10.2011, Kuzmi4
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--                  Add PB_WB converter
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--
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--  Version 1.2  19.10.2011, Kuzmi4
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--                  Move "core64_pb_wishbone_ctrl" component declaration for PKG to here 
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--                    (in accordance to http://ds-dev.ru/boards/1/topics/4, point#4)
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.core64_type_pkg.all;
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package core64_pb_wishbone_pkg is
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component core64_pb_wishbone is
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port
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(
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    reset               : in std_logic;     --! 1 - сброс
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    clk                 : in std_logic;     --! тактовая частота локальной шины 
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    ---- BAR1 ----
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    pb_master           : in  type_pb_master;   --! запрос 
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    pb_slave            : out type_pb_slave;    --! ответ  
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    ---- Wishbone BUS -----
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    ov_wbm_addr     :   out std_logic_vector(31 downto 0);
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    ov_wbm_data     :   out std_logic_vector(63 downto 0);
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    ov_wbm_sel      :   out std_logic_vector( 7 downto 0);
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    o_wbm_we        :   out std_logic;
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    o_wbm_cyc       :   out std_logic;
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    o_wbm_stb       :   out std_logic;
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    ov_wbm_cti      :   out std_logic_vector( 2 downto 0);  -- Cycle Type Identifier Address Tag
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    ov_wbm_bte      :   out std_logic_vector( 1 downto 0);  -- Burst Type Extension Address Tag
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    iv_wbm_data     :   in  std_logic_vector(63 downto 0);
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    i_wbm_ack       :   in  std_logic;
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    i_wbm_err       :   in  std_logic;                      -- error input - abnormal cycle termination
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    i_wbm_rty       :   in  std_logic;                      -- retry input - interface is not ready
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    i_wdm_irq_0     :   in  std_logic;
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    iv_wbm_irq_dmar :   in  std_logic_vector( 1 downto 0)
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);
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end component core64_pb_wishbone;
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end package core64_pb_wishbone_pkg;
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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library work;
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use work.core64_type_pkg.all;
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entity core64_pb_wishbone is
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port
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(
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    reset               : in std_logic;     --! 1 - сброс
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    clk                 : in std_logic;     --! тактовая частота локальной шины 
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    ---- BAR1 ----
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    pb_master           : in  type_pb_master;   --! запрос 
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    pb_slave            : out type_pb_slave;    --! ответ  
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    ---- Wishbone BUS -----
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    ov_wbm_addr     :   out std_logic_vector(31 downto 0);
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    ov_wbm_data     :   out std_logic_vector(63 downto 0);
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    ov_wbm_sel      :   out std_logic_vector( 7 downto 0);
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    o_wbm_we        :   out std_logic;
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    o_wbm_cyc       :   out std_logic;
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    o_wbm_stb       :   out std_logic;
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    ov_wbm_cti      :   out std_logic_vector( 2 downto 0);  -- Cycle Type Identifier Address Tag
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    ov_wbm_bte      :   out std_logic_vector( 1 downto 0);  -- Burst Type Extension Address Tag
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    iv_wbm_data     :   in  std_logic_vector(63 downto 0);
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    i_wbm_ack       :   in  std_logic;
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    i_wbm_err       :   in  std_logic;                      -- error input - abnormal cycle termination
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    i_wbm_rty       :   in  std_logic;                      -- retry input - interface is not ready
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    i_wdm_irq_0     :   in  std_logic;
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    iv_wbm_irq_dmar :   in  std_logic_vector( 1 downto 0)
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);
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end core64_pb_wishbone;
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architecture core64_pb_wishbone of core64_pb_wishbone is
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-------------------------------------------------------------------------------
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--
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-- Declare "core64_pb_wishbone_ctrl" component here:
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component core64_pb_wishbone_ctrl is
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port
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(
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    --
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    -- SYS_CON
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    i_clk : in  STD_LOGIC;
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    i_rst : in  STD_LOGIC;
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    --
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    -- PB_MASTER (in) IF
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    i_pb_master_stb0    :   in  std_logic;
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    i_pb_master_stb1    :   in  std_logic;
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    iv_pb_master_cmd    :   in  std_logic_vector( 2 downto 0);
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    iv_pb_master_addr   :   in  std_logic_vector(31 downto 0);
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    iv_pb_master_data   :   in  std_logic_vector(63 downto 0);
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    --
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    -- PB_SLAVE (out) IF:
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    o_pb_slave_ready    :   out std_logic;
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    o_pb_slave_complete :   out std_logic;
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    o_pb_slave_stb0     :   out std_logic;
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    o_pb_slave_stb1     :   out std_logic;
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    ov_pb_slave_data    :   out std_logic_vector(63 downto 0);
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    ov_pb_slave_dmar    :   out std_logic_vector( 1 downto 0);
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    o_pb_slave_irq      :   out std_logic;
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    --
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    -- WB BUS:
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    ov_wbm_addr     :   out std_logic_vector(31 downto 0);
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    ov_wbm_data     :   out std_logic_vector(63 downto 0);
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    ov_wbm_sel      :   out std_logic_vector( 7 downto 0);
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    o_wbm_we        :   out std_logic;
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    o_wbm_cyc       :   out std_logic;
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    o_wbm_stb       :   out std_logic;
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    ov_wbm_cti      :   out std_logic_vector( 2 downto 0);  -- Cycle Type Identifier Address Tag
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    ov_wbm_bte      :   out std_logic_vector( 1 downto 0);  -- Burst Type Extension Address Tag
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    iv_wbm_data     :   in  std_logic_vector(63 downto 0);
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    i_wbm_ack       :   in  std_logic;
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    i_wbm_err       :   in  std_logic;                      -- error input - abnormal cycle termination
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    i_wbm_rty       :   in  std_logic;                      -- retry input - interface is not ready
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    i_wdm_irq_0     :   in  std_logic;
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    iv_wbm_irq_dmar :   in  std_logic_vector( 1 downto 0)
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);
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end component core64_pb_wishbone_ctrl;
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-------------------------------------------------------------------------------
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begin
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-------------------------------------------------------------------------------
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--
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-- Instantiate PB_WB_BRIDGE (and route PB wires):
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--
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PB_WB_BRIDGE    :   core64_pb_wishbone_ctrl
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port map
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(
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    --
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    -- SYS_CON
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    i_clk => clk,           -- 
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    i_rst => reset,         -- 
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    --
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    -- PB_MASTER (in) IF
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    i_pb_master_stb0    => pb_master.stb0,
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    i_pb_master_stb1    => pb_master.stb1,
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    iv_pb_master_cmd    => pb_master.cmd,
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    iv_pb_master_addr   => pb_master.adr,
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    iv_pb_master_data   => pb_master.data,
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    --
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    -- PB_SLAVE (out) IF:
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    o_pb_slave_ready    => pb_slave.ready,
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    o_pb_slave_complete => pb_slave.complete,
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    o_pb_slave_stb0     => pb_slave.stb0,
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    o_pb_slave_stb1     => pb_slave.stb1,
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    ov_pb_slave_data    => pb_slave.data,
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    ov_pb_slave_dmar    => pb_slave.dmar,
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    o_pb_slave_irq      => pb_slave.irq,
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    --
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    -- WB BUS:
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    ov_wbm_addr     => ov_wbm_addr,
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    ov_wbm_data     => ov_wbm_data,
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    ov_wbm_sel      => ov_wbm_sel,
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    o_wbm_we        => o_wbm_we,
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    o_wbm_cyc       => o_wbm_cyc,
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    o_wbm_stb       => o_wbm_stb,
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    ov_wbm_cti      => ov_wbm_cti,      -- Cycle Type Identifier Address Tag
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    ov_wbm_bte      => ov_wbm_bte,      -- Burst Type Extension Address Tag
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    iv_wbm_data     => iv_wbm_data,
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    i_wbm_ack       => i_wbm_ack,
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    i_wbm_err       => i_wbm_err,       -- error input - abnormal cycle termination
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    i_wbm_rty       => i_wbm_rty,       -- retry input - interface is not ready
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    i_wdm_irq_0     => i_wdm_irq_0,
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    iv_wbm_irq_dmar => iv_wbm_irq_dmar
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);
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-------------------------------------------------------------------------------
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end core64_pb_wishbone;

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