1 |
2 |
dsmv |
//////////////////////////////////////////////////////////////////////////////////
|
2 |
|
|
// Company: ;)
|
3 |
|
|
// Engineer: Kuzmi4
|
4 |
|
|
//
|
5 |
|
|
// Create Date: 14:39:52 05/19/2010
|
6 |
|
|
// Design Name:
|
7 |
|
|
// Module Name: core64_pb_wishbone_ctrl
|
8 |
|
|
// Project Name: DS_DMA
|
9 |
|
|
// Target Devices:
|
10 |
|
|
// Tool versions:
|
11 |
|
|
// Description:
|
12 |
|
|
//
|
13 |
|
|
// Module serves for PB<->WB conversion
|
14 |
|
|
//
|
15 |
|
|
// Data Transfers:
|
16 |
|
|
// ==> 1 WORD (64bit)
|
17 |
|
|
// ==> 512 WORDS (64bit) - in this case slave must have holder for N*64bit,
|
18 |
|
|
// because PB_MASTER stops data transfer after K cycles "o_pb_slave_ready" falling (N>K)
|
19 |
|
|
//
|
20 |
|
|
// For now:
|
21 |
|
|
// 1) we have 64bit data transfer at WB bus
|
22 |
|
|
// 2) i_wbm_err/i_wbm_rty - not avaliable func
|
23 |
|
|
//
|
24 |
|
|
//
|
25 |
|
|
// Revision:
|
26 |
|
|
// Revision 0.01 - File Created
|
27 |
|
|
// Revision 0.02 - upd PB_SLAVE if with COMPLETE/READY signals, upgrade LOGIC
|
28 |
|
|
//
|
29 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
30 |
|
|
`timescale 1ns / 1ps
|
31 |
|
|
|
32 |
|
|
module core64_pb_wishbone_ctrl
|
33 |
|
|
(
|
34 |
|
|
// SYS_CON (same for PB/WB bus)
|
35 |
|
|
input i_clk,
|
36 |
|
|
input i_rst,
|
37 |
|
|
//
|
38 |
|
|
// PB_MASTER (in) IF
|
39 |
|
|
input i_pb_master_stb0, // CMD STB
|
40 |
|
|
input i_pb_master_stb1, // DATA STB
|
41 |
|
|
input [ 2:0] iv_pb_master_cmd, // CMD
|
42 |
|
|
input [31:0] iv_pb_master_addr, // ADDR
|
43 |
|
|
input [63:0] iv_pb_master_data, // DATA
|
44 |
|
|
//
|
45 |
|
|
// PB_SLAVE (out) IF:
|
46 |
|
|
output o_pb_slave_ready,
|
47 |
|
|
output reg o_pb_slave_complete,
|
48 |
|
|
output reg o_pb_slave_stb0, // WR CMD ACK STB (to pcie_core64_m6)
|
49 |
|
|
output reg o_pb_slave_stb1, // DATA ACK STB (to pcie_core64_m6)
|
50 |
|
|
output reg [63:0] ov_pb_slave_data, // DATA (to pcie_core64_m6)
|
51 |
|
|
output [ 1:0] ov_pb_slave_dmar, // ...
|
52 |
|
|
output o_pb_slave_irq, // ...
|
53 |
|
|
//
|
54 |
|
|
// WB BUS:
|
55 |
|
|
output [31:0] ov_wbm_addr,
|
56 |
|
|
output [63:0] ov_wbm_data,
|
57 |
|
|
output [ 7:0] ov_wbm_sel,
|
58 |
|
|
output o_wbm_we,
|
59 |
|
|
output reg o_wbm_cyc,
|
60 |
|
|
output o_wbm_stb,
|
61 |
|
|
output reg [ 2:0] ov_wbm_cti, // Cycle Type Identifier Address Tag
|
62 |
|
|
output [ 1:0] ov_wbm_bte, // Burst Type Extension Address Tag
|
63 |
|
|
|
64 |
|
|
input [63:0] iv_wbm_data, //
|
65 |
|
|
input i_wbm_ack, //
|
66 |
|
|
input i_wbm_err, // error input - abnormal cycle termination
|
67 |
|
|
input i_wbm_rty, // retry input - interface is not ready
|
68 |
|
|
|
69 |
|
|
input i_wdm_irq_0,
|
70 |
|
|
input [ 1:0] iv_wbm_irq_dmar
|
71 |
|
|
|
72 |
|
|
);
|
73 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
74 |
|
|
//
|
75 |
|
|
localparam lp_CASE0 = 0;
|
76 |
|
|
localparam lp_RD_CASE0 = 1;
|
77 |
|
|
localparam lp_RD_CASE1 = 2;
|
78 |
|
|
localparam lp_RD_CASE2 = 3;
|
79 |
|
|
localparam lp_WR_CASE0 = 4;
|
80 |
|
|
localparam lp_WR_CASE1 = 5;
|
81 |
|
|
localparam lp_WR_CASE2 = 6;
|
82 |
|
|
//
|
83 |
|
|
localparam lp_PB_VOL512 = 2;
|
84 |
|
|
localparam lp_PB_RD = 1;
|
85 |
|
|
localparam lp_PB_WR = 0;
|
86 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
87 |
|
|
// Declare PB_MASTER stuff:
|
88 |
|
|
reg s_pb_master_stb0;
|
89 |
|
|
reg s_pb_master_stb1;
|
90 |
|
|
reg [ 2:0] sv_pb_master_cmd;
|
91 |
|
|
reg [31:0] sv_pb_master_addr;
|
92 |
|
|
// Declare WB_COMP_OUTGOING_FIFO stuff:
|
93 |
|
|
wire s_wb_comp_outgoing_fifo_rd_en;
|
94 |
|
|
wire s_wb_comp_outgoing_fifo_full;
|
95 |
|
|
wire s_wb_comp_outgoing_fifo_empty;
|
96 |
|
|
wire [ 8:0] sv_wb_comp_outgoing_fifo_data_count;
|
97 |
|
|
// PB_SLAVE.COMPLETE stuff:
|
98 |
|
|
reg s_pb_slave_complete;
|
99 |
|
|
// PB_DATA_COUNTERs stuff:
|
100 |
|
|
reg [8:0] sv_wb_comp_outgoing_in_data_count;
|
101 |
|
|
reg [8:0] sv_wb_comp_outgoing_out_data_count;
|
102 |
|
|
reg [8:0] sv_wb_comp_incoming_data_count;
|
103 |
|
|
//
|
104 |
|
|
// FSM
|
105 |
|
|
reg [3:0] sv_wbm_fsm;
|
106 |
|
|
reg [3:0] sv_pb_fsm;
|
107 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
108 |
|
|
//
|
109 |
|
|
// WB stuff:
|
110 |
|
|
assign ov_wbm_addr = sv_pb_master_addr;
|
111 |
|
|
assign o_wbm_we = sv_wbm_fsm==lp_WR_CASE0 | sv_wbm_fsm==lp_WR_CASE2;
|
112 |
|
|
|
113 |
|
|
assign o_wbm_stb = o_wbm_cyc;
|
114 |
|
|
assign ov_wbm_sel = 8'hFF; // --> always ENA all 64bit
|
115 |
|
|
assign ov_wbm_bte = 0; // --> always Linear burst
|
116 |
|
|
//
|
117 |
|
|
// DMAR[1:0] and IRQ direct route:
|
118 |
|
|
assign ov_pb_slave_dmar = iv_wbm_irq_dmar;
|
119 |
|
|
assign o_pb_slave_irq = i_wdm_irq_0;
|
120 |
|
|
//
|
121 |
|
|
//
|
122 |
|
|
assign o_pb_slave_ready = (sv_wb_comp_outgoing_fifo_data_count < 32);
|
123 |
|
|
//
|
124 |
|
|
// OUTGOING FIFO controls:
|
125 |
|
|
assign s_wb_comp_outgoing_fifo_rd_en = (i_wbm_ack & o_wbm_we & o_wbm_cyc) |
|
126 |
|
|
(o_wbm_we & !o_wbm_cyc);
|
127 |
|
|
// because at WR side of FIFO we have no WR brackes -
|
128 |
|
|
// at RD side of FIFO we will have speed always EQU
|
129 |
|
|
// or LESS than at WR side
|
130 |
|
|
|
131 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
132 |
|
|
//
|
133 |
|
|
// Register Inputs from PB MASTER (in) IF:
|
134 |
|
|
//
|
135 |
|
|
always @ (posedge i_clk or posedge i_rst)
|
136 |
|
|
begin : REG_PB_MASTER
|
137 |
|
|
if (i_rst)
|
138 |
|
|
begin : RST
|
139 |
|
|
s_pb_master_stb0 <= 0;
|
140 |
|
|
s_pb_master_stb1 <= 0;
|
141 |
|
|
sv_pb_master_cmd <= 0;
|
142 |
|
|
sv_pb_master_addr <= 0;
|
143 |
|
|
end
|
144 |
|
|
else
|
145 |
|
|
begin : WRK
|
146 |
|
|
// REG controls
|
147 |
|
|
s_pb_master_stb0 <= i_pb_master_stb0;
|
148 |
|
|
s_pb_master_stb1 <= i_pb_master_stb1;
|
149 |
|
|
// CMD STB
|
150 |
|
|
if (i_pb_master_stb0)
|
151 |
|
|
begin
|
152 |
|
|
sv_pb_master_cmd <= iv_pb_master_cmd;
|
153 |
|
|
sv_pb_master_addr <= iv_pb_master_addr;
|
154 |
|
|
end
|
155 |
|
|
end
|
156 |
|
|
end
|
157 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
158 |
|
|
//
|
159 |
|
|
// Construct WB Master logic for 1W/512W trasfers:
|
160 |
|
|
//
|
161 |
|
|
always @ (posedge i_clk or posedge i_rst)
|
162 |
|
|
begin : WBM_LOGIC
|
163 |
|
|
if (i_rst)
|
164 |
|
|
begin : RST
|
165 |
|
|
sv_wbm_fsm <= lp_CASE0;
|
166 |
|
|
o_wbm_cyc <= 0;
|
167 |
|
|
ov_wbm_cti <= 0;
|
168 |
|
|
end
|
169 |
|
|
else
|
170 |
|
|
begin : WRK
|
171 |
|
|
case (sv_wbm_fsm)
|
172 |
|
|
// init case
|
173 |
|
|
lp_CASE0 : begin // WRK with registered controls
|
174 |
|
|
if (s_pb_master_stb0)
|
175 |
|
|
begin : START_CYC
|
176 |
|
|
if (sv_pb_master_cmd[lp_PB_WR])
|
177 |
|
|
begin : WR_DEAL
|
178 |
|
|
if (sv_pb_master_cmd[lp_PB_VOL512]) // 512 WORDs
|
179 |
|
|
sv_wbm_fsm <= lp_WR_CASE1;
|
180 |
|
|
else // 1 WORD
|
181 |
|
|
sv_wbm_fsm <= lp_WR_CASE0;
|
182 |
|
|
end
|
183 |
|
|
else
|
184 |
|
|
begin : RD_DEAL
|
185 |
|
|
if (sv_pb_master_cmd[lp_PB_VOL512]) // 512 WORDs
|
186 |
|
|
sv_wbm_fsm <= lp_RD_CASE1;
|
187 |
|
|
else // 1 WORD
|
188 |
|
|
sv_wbm_fsm <= lp_RD_CASE0;
|
189 |
|
|
end
|
190 |
|
|
end
|
191 |
|
|
//
|
192 |
|
|
o_wbm_cyc <= s_pb_master_stb0 & sv_pb_master_cmd[lp_PB_RD];
|
193 |
|
|
ov_wbm_cti <= (s_pb_master_stb0 & sv_pb_master_cmd[lp_PB_RD] & sv_pb_master_cmd[lp_PB_VOL512])?3'b001 : // Const_Addr Burst
|
194 |
|
|
3'b000 ; // Classic Cycle
|
195 |
|
|
end
|
196 |
|
|
//
|
197 |
|
|
lp_WR_CASE0 : begin // 1 WORD
|
198 |
|
|
o_wbm_cyc <= !(s_wb_comp_outgoing_fifo_empty & i_wbm_ack);
|
199 |
|
|
ov_wbm_cti <= 3'b000;// Classic Cycle
|
200 |
|
|
|
201 |
|
|
if (s_wb_comp_outgoing_fifo_empty & i_wbm_ack)
|
202 |
|
|
sv_wbm_fsm <= lp_CASE0;
|
203 |
|
|
end
|
204 |
|
|
lp_WR_CASE1 : begin // WR0: 512 WORDs
|
205 |
|
|
if (s_pb_master_stb1)
|
206 |
|
|
sv_wbm_fsm <= lp_WR_CASE2;
|
207 |
|
|
end
|
208 |
|
|
lp_WR_CASE2 : begin // WR1: 512 WORDs
|
209 |
|
|
o_wbm_cyc <= (sv_wb_comp_outgoing_out_data_count==511 & i_wbm_ack)? 1'b0 : 1'b1;
|
210 |
|
|
ov_wbm_cti <= (
|
211 |
|
|
(sv_wb_comp_outgoing_out_data_count==510 & i_wbm_ack) |
|
212 |
|
|
sv_wb_comp_outgoing_out_data_count==511
|
213 |
|
|
)? 3'b111 : 3'b001; // End-of-Burst:Const_Addr Burst
|
214 |
|
|
|
215 |
|
|
if (sv_wb_comp_outgoing_out_data_count==511 & i_wbm_ack)
|
216 |
|
|
sv_wbm_fsm <= lp_CASE0;
|
217 |
|
|
end
|
218 |
|
|
//
|
219 |
|
|
lp_RD_CASE0 : begin // 1 WORD
|
220 |
|
|
o_wbm_cyc <= !i_wbm_ack; // !!!
|
221 |
|
|
ov_wbm_cti <= 3'b000;// Classic Cycle
|
222 |
|
|
|
223 |
|
|
if (i_wbm_ack)
|
224 |
|
|
sv_wbm_fsm <= lp_CASE0;
|
225 |
|
|
end
|
226 |
|
|
lp_RD_CASE1 : begin // 512 WORDs
|
227 |
|
|
o_wbm_cyc <= (i_wbm_ack & sv_wb_comp_incoming_data_count==511)? 1'b0 : 1'b1;
|
228 |
|
|
ov_wbm_cti <= (
|
229 |
|
|
(sv_wb_comp_incoming_data_count==510 & i_wbm_ack) |
|
230 |
|
|
sv_wb_comp_incoming_data_count==511
|
231 |
|
|
)? 3'b111 : 3'b001; // End-of-Burst:Const_Addr Burst
|
232 |
|
|
|
233 |
|
|
if (i_wbm_ack & sv_wb_comp_incoming_data_count==511)
|
234 |
|
|
sv_wbm_fsm <= lp_CASE0;
|
235 |
|
|
end
|
236 |
|
|
endcase
|
237 |
|
|
|
238 |
|
|
end
|
239 |
|
|
end
|
240 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
241 |
|
|
//
|
242 |
|
|
// Construct logic for answer to PB Master via PB Slave (complete) IF:
|
243 |
|
|
//
|
244 |
|
|
always @ (posedge i_clk or posedge i_rst)
|
245 |
|
|
begin : CRE_PB_COMPLETE_LOGIC
|
246 |
|
|
if (i_rst)
|
247 |
|
|
begin : RST
|
248 |
|
|
o_pb_slave_complete <= 0;
|
249 |
|
|
s_pb_slave_complete <= 0;
|
250 |
|
|
end
|
251 |
|
|
else
|
252 |
|
|
begin : WRK
|
253 |
|
|
//
|
254 |
|
|
s_pb_slave_complete <= (sv_wbm_fsm==lp_RD_CASE0 & i_wbm_ack) | //
|
255 |
|
|
(sv_wbm_fsm==lp_RD_CASE1 & i_wbm_ack & sv_wb_comp_incoming_data_count==511) | //
|
256 |
|
|
|
257 |
|
|
(sv_wbm_fsm==lp_WR_CASE0 & s_wb_comp_outgoing_fifo_empty & i_wbm_ack) | //
|
258 |
|
|
(sv_wbm_fsm==lp_WR_CASE2 & sv_wb_comp_outgoing_out_data_count==511 & i_wbm_ack) ; //
|
259 |
|
|
//
|
260 |
|
|
o_pb_slave_complete <= s_pb_slave_complete;
|
261 |
|
|
end
|
262 |
|
|
end
|
263 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
264 |
|
|
//
|
265 |
|
|
// Construct Logic for PB Slave (data) IF:
|
266 |
|
|
//
|
267 |
|
|
always@ (posedge i_clk or posedge i_rst)
|
268 |
|
|
begin : CRE_PB_SLAVE_DATA
|
269 |
|
|
if (i_rst)
|
270 |
|
|
begin : RST
|
271 |
|
|
ov_pb_slave_data <= 0;
|
272 |
|
|
end
|
273 |
|
|
else
|
274 |
|
|
begin : WRK
|
275 |
|
|
if (i_wbm_ack) // ENA
|
276 |
|
|
ov_pb_slave_data <= iv_wbm_data;
|
277 |
|
|
end
|
278 |
|
|
end
|
279 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
280 |
|
|
//
|
281 |
|
|
// Construct Logic for PB Slave (stb1/stb0) IF:
|
282 |
|
|
//
|
283 |
|
|
always @ (posedge i_clk or posedge i_rst)
|
284 |
|
|
begin : CRE_PB_SLAVE_STB_1_LOGIC
|
285 |
|
|
if (i_rst)
|
286 |
|
|
begin : RST
|
287 |
|
|
sv_pb_fsm <= lp_CASE0;
|
288 |
|
|
o_pb_slave_stb1 <= 0;
|
289 |
|
|
end
|
290 |
|
|
else
|
291 |
|
|
begin : WRK
|
292 |
|
|
case (sv_pb_fsm)
|
293 |
|
|
//
|
294 |
|
|
lp_CASE0 : begin // WRK with registered controls
|
295 |
|
|
if (s_pb_master_stb0 & sv_pb_master_cmd[lp_PB_RD])
|
296 |
|
|
begin : RD_DEAL
|
297 |
|
|
sv_pb_fsm <= lp_RD_CASE0;
|
298 |
|
|
end
|
299 |
|
|
//
|
300 |
|
|
o_pb_slave_stb1 <= 0;
|
301 |
|
|
end
|
302 |
|
|
//
|
303 |
|
|
lp_RD_CASE0 : begin // 1/512 WORD
|
304 |
|
|
o_pb_slave_stb1 <= i_wbm_ack;
|
305 |
|
|
if (
|
306 |
|
|
(i_wbm_ack & sv_wb_comp_incoming_data_count==511) | // 512 WORD case
|
307 |
|
|
s_pb_slave_complete // 1 WORD case
|
308 |
|
|
)
|
309 |
|
|
sv_pb_fsm <= lp_CASE0;
|
310 |
|
|
end
|
311 |
|
|
|
312 |
|
|
endcase
|
313 |
|
|
end
|
314 |
|
|
end
|
315 |
|
|
/**/
|
316 |
|
|
always @ (posedge i_clk or posedge i_rst)
|
317 |
|
|
begin : CRE_PB_SLAVE_STB_0
|
318 |
|
|
if (i_rst)
|
319 |
|
|
o_pb_slave_stb0 <= 0;
|
320 |
|
|
else if (sv_wbm_fsm==lp_CASE0)
|
321 |
|
|
o_pb_slave_stb0 <= i_pb_master_stb0;
|
322 |
|
|
else
|
323 |
|
|
o_pb_slave_stb0 <= 0;
|
324 |
|
|
end
|
325 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
326 |
|
|
//
|
327 |
|
|
// Construct counter logic for PB Master/Slave control purposes:
|
328 |
|
|
//
|
329 |
|
|
always @ (posedge i_clk or posedge i_rst)
|
330 |
|
|
begin : CRE_PB_DATA_COUNTERs
|
331 |
|
|
if (i_rst)
|
332 |
|
|
begin : RST
|
333 |
|
|
sv_wb_comp_outgoing_in_data_count <= 0;
|
334 |
|
|
sv_wb_comp_outgoing_out_data_count <= 0;
|
335 |
|
|
|
336 |
|
|
sv_wb_comp_incoming_data_count <= 0;
|
337 |
|
|
end
|
338 |
|
|
else
|
339 |
|
|
begin
|
340 |
|
|
// INCOMING PB_MASTER data counter for WB_COMP_OUTGOING_FIFO
|
341 |
|
|
if (sv_wbm_fsm==lp_WR_CASE0 | sv_wbm_fsm==lp_WR_CASE1 | sv_wbm_fsm==lp_WR_CASE2)
|
342 |
|
|
begin : IN_COUNT_TIME
|
343 |
|
|
if (i_pb_master_stb1)
|
344 |
|
|
sv_wb_comp_outgoing_in_data_count <= sv_wb_comp_outgoing_in_data_count + 1'b1;
|
345 |
|
|
end
|
346 |
|
|
else
|
347 |
|
|
sv_wb_comp_outgoing_in_data_count <= 0;
|
348 |
|
|
// OUTGOING PB_MASTER data counter for WB_COMP_OUTGOING_FIFO
|
349 |
|
|
if (sv_wbm_fsm==lp_WR_CASE0 | sv_wbm_fsm==lp_WR_CASE1 | sv_wbm_fsm==lp_WR_CASE2)
|
350 |
|
|
begin : OUT_COUNT_TIME
|
351 |
|
|
if (i_wbm_ack)
|
352 |
|
|
sv_wb_comp_outgoing_out_data_count <= sv_wb_comp_outgoing_out_data_count + 1'b1;
|
353 |
|
|
end
|
354 |
|
|
else
|
355 |
|
|
sv_wb_comp_outgoing_out_data_count <= 0;
|
356 |
|
|
//
|
357 |
|
|
// IN WB/OUT PB_SLAVE data transfer counter
|
358 |
|
|
if (sv_wbm_fsm==lp_RD_CASE1)
|
359 |
|
|
begin : COUNT_TIME
|
360 |
|
|
if (i_wbm_ack)
|
361 |
|
|
sv_wb_comp_incoming_data_count <= sv_wb_comp_incoming_data_count + 1'b1;
|
362 |
|
|
end
|
363 |
|
|
else
|
364 |
|
|
sv_wb_comp_incoming_data_count <= 0;
|
365 |
|
|
end
|
366 |
|
|
end
|
367 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
368 |
|
|
//
|
369 |
|
|
// Instantiate "WB_COMP_FIFO" (because PB_MASTER IF stops Transaction after K cycles of falling "o_pb_slave_ready")
|
370 |
|
|
//
|
371 |
|
|
// ==> all outgoing DATA transaction routes throught this FIFO: from PB_MASTER IF to WB IF
|
372 |
|
|
//
|
373 |
|
|
ctrl_fifo512x64st_v0 WB_COMP_OUTGOING_FIFO
|
374 |
|
|
(
|
375 |
|
|
.clk (i_clk),
|
376 |
|
|
.rst (i_rst),
|
377 |
|
|
//
|
378 |
|
|
.wr_en (i_pb_master_stb1),
|
379 |
|
|
.din (iv_pb_master_data),
|
380 |
|
|
//
|
381 |
|
|
.rd_en (s_wb_comp_outgoing_fifo_rd_en),
|
382 |
|
|
.dout (ov_wbm_data),
|
383 |
|
|
//
|
384 |
|
|
.full (s_wb_comp_outgoing_fifo_full),
|
385 |
|
|
.empty (s_wb_comp_outgoing_fifo_empty),
|
386 |
|
|
//
|
387 |
|
|
.data_count (sv_wb_comp_outgoing_fifo_data_count)
|
388 |
|
|
);
|
389 |
|
|
|
390 |
|
|
// synthesis translate_off
|
391 |
|
|
integer si_wb_outgoing_fifo_wr_counter=0;
|
392 |
|
|
always @ (posedge i_clk or posedge i_rst)
|
393 |
|
|
begin : SIM_FIFO_WR_COUNTER
|
394 |
|
|
if (i_rst)
|
395 |
|
|
si_wb_outgoing_fifo_wr_counter=0;
|
396 |
|
|
else if (i_pb_master_stb1)
|
397 |
|
|
si_wb_outgoing_fifo_wr_counter=si_wb_outgoing_fifo_wr_counter+1;
|
398 |
|
|
else if (o_pb_slave_complete)
|
399 |
|
|
si_wb_outgoing_fifo_wr_counter=0;
|
400 |
|
|
end
|
401 |
|
|
|
402 |
|
|
initial
|
403 |
|
|
begin : WB_COMP_OUTGOING_FIFO_WR_SNIFF
|
404 |
|
|
forever
|
405 |
|
|
begin : LOGIC
|
406 |
|
|
@(posedge i_clk);
|
407 |
|
|
if (si_wb_outgoing_fifo_wr_counter>512)
|
408 |
|
|
begin : ERR_MSG
|
409 |
|
|
$display("[%t]: %m", $time);
|
410 |
|
|
$stop;
|
411 |
|
|
end
|
412 |
|
|
end
|
413 |
|
|
end
|
414 |
|
|
// synthesis translate_on
|
415 |
|
|
|
416 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
417 |
|
|
//
|
418 |
|
|
// Process WB ERR functionality here:
|
419 |
|
|
// ==> Now only SNIFF, MSG and STOP
|
420 |
|
|
//
|
421 |
|
|
|
422 |
|
|
// synthesis translate_off
|
423 |
|
|
initial
|
424 |
|
|
begin : WB_ERR
|
425 |
|
|
@(posedge i_clk);
|
426 |
|
|
forever
|
427 |
|
|
begin : ERR_SNIFF
|
428 |
|
|
@(posedge i_wbm_err);
|
429 |
|
|
$display("[%t]: %m: WB_ERR functionality NOT SUPPORTED, ONLY INFORM!!!", $time); #1;
|
430 |
|
|
$stop;
|
431 |
|
|
end
|
432 |
|
|
|
433 |
|
|
end
|
434 |
|
|
initial
|
435 |
|
|
begin : WB_RTY
|
436 |
|
|
@(posedge i_clk);
|
437 |
|
|
forever
|
438 |
|
|
begin : ERR_SNIFF
|
439 |
|
|
@(posedge i_wbm_rty);
|
440 |
|
|
$display("[%t]: %m: WB_RTY functionality NOT SUPPORTED, ONLY INFORM!!!", $time); #1;
|
441 |
|
|
$stop;
|
442 |
|
|
end
|
443 |
|
|
|
444 |
|
|
end
|
445 |
|
|
// synthesis translate_on
|
446 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
447 |
|
|
endmodule
|