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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [components/] [rtl/] [ctrl_ram16_v1.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dsmv
---------------------------------------------------------------------------------------------------
2
--
3
-- Title       : ctrl_ram16_v1
4
-- Author      : Dmitry Smekhov
5
-- Company     : Instrumental System
6
-- E-mail      : dsmv@insys.ru
7
--
8
-- Version     : 1.0     
9
--
10
---------------------------------------------------------------------------------------------------
11
--
12
-- Description :  Òåíåâîå ÎÇÓ äëÿ êîìàíäíûõ ðåãèñòðîâ è êîíñòàíò
13
--
14
---------------------------------------------------------------------------------------------------
15
 
16
library ieee;
17
use ieee.std_logic_1164.all;
18
 
19
library work;
20
use     work.host_pkg.all;
21
 
22
package ctrl_ram16_v1_pkg is
23
 
24
component ctrl_ram16_v1 is
25
        generic (
26
                rom                     : in bh_rom                     -- çíà÷åíèÿ êîíñòàíò
27
        );
28
        port(
29
                clk                     : in std_logic;         -- Òàêòîâàÿ ÷àñòîòà
30
 
31
                adr                     : in std_logic_vector( 4 downto 0 );     -- àäðåñ
32
                data_in         : in std_logic_vector( 15 downto 0 );    -- âõîä äàííûõ
33
                data_out        : out std_logic_vector( 15 downto 0 );   -- âûõîä äàííûõ
34
 
35
                data_we         : in std_logic          -- 1 - çàïèñü äàííûõ
36
 
37
        );
38
end component;
39
 
40
end package ctrl_ram16_v1_pkg;
41
 
42
 
43
 
44
 
45
library ieee;
46
use ieee.std_logic_1164.all;
47
 
48
library unisim;
49
use unisim.vcomponents.all;
50
 
51
library work;
52
use     work.host_pkg.all;
53
 
54
 
55
 
56
entity ctrl_ram16_v1 is
57
        generic (
58
                rom                     : in bh_rom                     -- çíà÷åíèÿ êîíñòàíò
59
        );
60
        port(
61
                clk                     : in std_logic;         -- Òàêòîâàÿ ÷àñòîòà
62
 
63
                adr                     : in std_logic_vector( 4 downto 0 );     -- àäðåñ
64
                data_in         : in std_logic_vector( 15 downto 0 );    -- âõîä äàííûõ
65
                data_out        : out std_logic_vector( 15 downto 0 );   -- âûõîä äàííûõ
66
 
67
                data_we         : in std_logic          -- 1 - çàïèñü äàííûõ
68
 
69
        );
70
end ctrl_ram16_v1;
71
 
72
 
73
architecture ctrl_ram16_v1 of ctrl_ram16_v1 is
74
 
75
function conv_rom( rom: in bh_rom; mode: integer ) return bit_vector is
76
 variable ret: bit_vector( 15 downto 0 );
77
begin
78
        for i in 0 to 7 loop
79
                ret( i ):=to_bit( rom( i )( mode ), '0' );
80
        end loop;
81
        for i in 8 to 15 loop
82
                ret( i ):='0';
83
        end loop;
84
        return ret;
85
end conv_rom;
86
 
87
function conv_string( rom: in bh_rom; mode: integer ) return string is
88
 variable str: string( 4 downto 1 );
89
 
90
 variable d     : std_logic_vector( 15 downto 0 );
91
 variable c     : std_logic_vector( 3 downto 0 );
92
 variable k     : integer;
93
begin
94
 
95
 
96
 
97
  for i in 0 to 7 loop
98
        d(i):=rom( i )( mode );
99
  end loop;
100
  for i in 8 to 15 loop
101
        d(i):='0';
102
  end loop;
103
 
104
  for j in 0 to 3 loop
105
         c:=d( j*4+3 downto j*4 );
106
         k:=j+1;
107
         case c is
108
                when x"0" => str(k) := '0';
109
                when x"1" => str(k) := '1';
110
                when x"2" => str(k) := '2';
111
                when x"3" => str(k) := '3';
112
                when x"4" => str(k) := '4';
113
                when x"5" => str(k) := '5';
114
                when x"6" => str(k) := '6';
115
                when x"7" => str(k) := '7';
116
                when x"8" => str(k) := '8';
117
                when x"9" => str(k) := '9';
118
                when x"A" => str(k) := 'A';
119
                when x"B" => str(k) := 'B';
120
                when x"C" => str(k) := 'C';
121
                when x"D" => str(k) := 'D';
122
                when x"E" => str(k) := 'E';
123
                when x"F" => str(k) := 'F';
124
                when others => null;
125
         end case;
126
  end loop;
127
 
128
  return str;
129
end conv_string;
130
 
131
 
132
constant rom_init_00    : bit_vector( 15 downto 0 ):= conv_rom( rom, 0 );
133
constant rom_init_01    : bit_vector( 15 downto 0 ):= conv_rom( rom, 1 );
134
constant rom_init_02    : bit_vector( 15 downto 0 ):= conv_rom( rom, 2 );
135
constant rom_init_03    : bit_vector( 15 downto 0 ):= conv_rom( rom, 3 );
136
constant rom_init_04    : bit_vector( 15 downto 0 ):= conv_rom( rom, 4 );
137
constant rom_init_05    : bit_vector( 15 downto 0 ):= conv_rom( rom, 5 );
138
constant rom_init_06    : bit_vector( 15 downto 0 ):= conv_rom( rom, 6 );
139
constant rom_init_07    : bit_vector( 15 downto 0 ):= conv_rom( rom, 7 );
140
constant rom_init_08    : bit_vector( 15 downto 0 ):= conv_rom( rom, 8 );
141
constant rom_init_09    : bit_vector( 15 downto 0 ):= conv_rom( rom, 9 );
142
constant rom_init_0A    : bit_vector( 15 downto 0 ):= conv_rom( rom, 10 );
143
constant rom_init_0B    : bit_vector( 15 downto 0 ):= conv_rom( rom, 11 );
144
constant rom_init_0C    : bit_vector( 15 downto 0 ):= conv_rom( rom, 12 );
145
constant rom_init_0D    : bit_vector( 15 downto 0 ):= conv_rom( rom, 13 );
146
constant rom_init_0E    : bit_vector( 15 downto 0 ):= conv_rom( rom, 14 );
147
constant rom_init_0F    : bit_vector( 15 downto 0 ):= conv_rom( rom, 15 );
148
 
149
 
150
 
151
constant str_init_00    : string:= conv_string( rom, 0 );
152
constant str_init_01    : string:= conv_string( rom, 1 );
153
constant str_init_02    : string:= conv_string( rom, 2 );
154
constant str_init_03    : string:= conv_string( rom, 3 );
155
constant str_init_04    : string:= conv_string( rom, 4 );
156
constant str_init_05    : string:= conv_string( rom, 5 );
157
constant str_init_06    : string:= conv_string( rom, 6 );
158
constant str_init_07    : string:= conv_string( rom, 7 );
159
constant str_init_08    : string:= conv_string( rom, 8 );
160
constant str_init_09    : string:= conv_string( rom, 9 );
161
constant str_init_0A    : string:= conv_string( rom, 10 );
162
constant str_init_0B    : string:= conv_string( rom, 11 );
163
constant str_init_0C    : string:= conv_string( rom, 12 );
164
constant str_init_0D    : string:= conv_string( rom, 13 );
165
constant str_init_0E    : string:= conv_string( rom, 14 );
166
constant str_init_0F    : string:= conv_string( rom, 15 );
167
 
168
 
169
--attribute rom_style : string;
170
--attribute rom_style of xram   : label is "block";
171
 
172
--attribute init                        : string;
173
--
174
--attribute init of xram0        : label is  str_init_00;
175
--attribute init of xram1        : label is  str_init_01;
176
--attribute init of xram2        : label is  str_init_02;
177
--attribute init of xram3        : label is  str_init_03;
178
--attribute init of xram4        : label is  str_init_04;
179
--attribute init of xram5        : label is  str_init_05;
180
--attribute init of xram6        : label is  str_init_06;
181
--attribute init of xram7        : label is  str_init_07;
182
--attribute init of xram8        : label is  str_init_08;
183
--attribute init of xram9        : label is  str_init_09;
184
--attribute init of xram10 : label is  str_init_0A;
185
--attribute init of xram11 : label is  str_init_0B;
186
--attribute init of xram12 : label is  str_init_0C;
187
--attribute init of xram13 : label is  str_init_0D;
188
--attribute init of xram14 : label is  str_init_0E;
189
--attribute init of xram15 : label is  str_init_0F;
190
--
191
 
192
 
193
signal  wr              : std_logic;    -- 1 - çàïèñü â ïàìÿòü
194
begin
195
 
196
wr <= '1' when data_we='1' and adr(4)='0' and adr(3)='1' else '0';
197
 
198
 
199
xram0:  ram16x1d
200
                generic map(
201
                        init =>  rom_init_00
202
                )
203
                port map(
204
                        we      => wr,
205
                        d       => data_in( 0 ),
206
                        wclk => clk,
207
                        a0      => adr( 0 ),
208
                        a1      => adr( 1 ),
209
                        a2      => adr( 2 ),
210
                        a3      => adr( 3 ),
211
                        spo     => data_out( 0 ),
212
                        dpra0 => adr( 0 ),
213
                        dpra1 => adr( 1 ),
214
                        dpra2 => adr( 2 ),
215
                        dpra3 => adr( 3 )
216
                );
217
 
218
xram1:  ram16x1d
219
                generic map(
220
                        init =>  rom_init_01
221
                )
222
                port map(
223
                        we      => wr,
224
                        d       => data_in( 1 ),
225
                        wclk => clk,
226
                        a0      => adr( 0 ),
227
                        a1      => adr( 1 ),
228
                        a2      => adr( 2 ),
229
                        a3      => adr( 3 ),
230
                        spo     => data_out( 1 ),
231
                        dpra0 => adr( 0 ),
232
                        dpra1 => adr( 1 ),
233
                        dpra2 => adr( 2 ),
234
                        dpra3 => adr( 3 )
235
                );
236
 
237
xram2:  ram16x1d
238
                generic map(
239
                        init =>  rom_init_02
240
                )
241
                port map(
242
                        we      => wr,
243
                        d       => data_in( 2 ),
244
                        wclk => clk,
245
                        a0      => adr( 0 ),
246
                        a1      => adr( 1 ),
247
                        a2      => adr( 2 ),
248
                        a3      => adr( 3 ),
249
                        spo     => data_out( 2 ),
250
                        dpra0 => adr( 0 ),
251
                        dpra1 => adr( 1 ),
252
                        dpra2 => adr( 2 ),
253
                        dpra3 => adr( 3 )
254
                );
255
 
256
xram3:  ram16x1d
257
                generic map(
258
                        init =>  rom_init_03
259
                )
260
                port map(
261
                        we      => wr,
262
                        d       => data_in( 3 ),
263
                        wclk => clk,
264
                        a0      => adr( 0 ),
265
                        a1      => adr( 1 ),
266
                        a2      => adr( 2 ),
267
                        a3      => adr( 3 ),
268
                        spo     => data_out( 3 ),
269
                        dpra0 => adr( 0 ),
270
                        dpra1 => adr( 1 ),
271
                        dpra2 => adr( 2 ),
272
                        dpra3 => adr( 3 )
273
                );
274
 
275
xram4:  ram16x1d
276
                generic map(
277
                        init =>  rom_init_04
278
                )
279
                port map(
280
                        we      => wr,
281
                        d       => data_in( 4 ),
282
                        wclk => clk,
283
                        a0      => adr( 0 ),
284
                        a1      => adr( 1 ),
285
                        a2      => adr( 2 ),
286
                        a3      => adr( 3 ),
287
                        spo     => data_out( 4 ),
288
                        dpra0 => adr( 0 ),
289
                        dpra1 => adr( 1 ),
290
                        dpra2 => adr( 2 ),
291
                        dpra3 => adr( 3 )
292
                );
293
 
294
xram5:  ram16x1d
295
                generic map(
296
                        init =>  rom_init_05
297
                )
298
                port map(
299
                        we      => wr,
300
                        d       => data_in( 5 ),
301
                        wclk => clk,
302
                        a0      => adr( 0 ),
303
                        a1      => adr( 1 ),
304
                        a2      => adr( 2 ),
305
                        a3      => adr( 3 ),
306
                        spo     => data_out( 5 ),
307
                        dpra0 => adr( 0 ),
308
                        dpra1 => adr( 1 ),
309
                        dpra2 => adr( 2 ),
310
                        dpra3 => adr( 3 )
311
                );
312
 
313
xram6:  ram16x1d
314
                generic map(
315
                        init =>  rom_init_06
316
                )
317
                port map(
318
                        we      => wr,
319
                        d       => data_in( 6 ),
320
                        wclk => clk,
321
                        a0      => adr( 0 ),
322
                        a1      => adr( 1 ),
323
                        a2      => adr( 2 ),
324
                        a3      => adr( 3 ),
325
                        spo     => data_out( 6 ),
326
                        dpra0 => adr( 0 ),
327
                        dpra1 => adr( 1 ),
328
                        dpra2 => adr( 2 ),
329
                        dpra3 => adr( 3 )
330
                );
331
 
332
xram7:  ram16x1d
333
                generic map(
334
                        init =>  rom_init_07
335
                )
336
                port map(
337
                        we      => wr,
338
                        d       => data_in( 7 ),
339
                        wclk => clk,
340
                        a0      => adr( 0 ),
341
                        a1      => adr( 1 ),
342
                        a2      => adr( 2 ),
343
                        a3      => adr( 3 ),
344
                        spo     => data_out( 7 ),
345
                        dpra0 => adr( 0 ),
346
                        dpra1 => adr( 1 ),
347
                        dpra2 => adr( 2 ),
348
                        dpra3 => adr( 3 )
349
                );
350
 
351
xram8:  ram16x1d
352
                generic map(
353
                        init =>  rom_init_08
354
                )
355
                port map(
356
                        we      => wr,
357
                        d       => data_in( 8 ),
358
                        wclk => clk,
359
                        a0      => adr( 0 ),
360
                        a1      => adr( 1 ),
361
                        a2      => adr( 2 ),
362
                        a3      => adr( 3 ),
363
                        spo     => data_out( 8 ),
364
                        dpra0 => adr( 0 ),
365
                        dpra1 => adr( 1 ),
366
                        dpra2 => adr( 2 ),
367
                        dpra3 => adr( 3 )
368
                );
369
 
370
xram9:  ram16x1d
371
                generic map(
372
                        init =>  rom_init_09
373
                )
374
                port map(
375
                        we      => wr,
376
                        d       => data_in( 9 ),
377
                        wclk => clk,
378
                        a0      => adr( 0 ),
379
                        a1      => adr( 1 ),
380
                        a2      => adr( 2 ),
381
                        a3      => adr( 3 ),
382
                        spo     => data_out( 9 ),
383
                        dpra0 => adr( 0 ),
384
                        dpra1 => adr( 1 ),
385
                        dpra2 => adr( 2 ),
386
                        dpra3 => adr( 3 )
387
                );
388
 
389
xram10: ram16x1d
390
                generic map(
391
                        init =>  rom_init_0A
392
                )
393
                port map(
394
                        we      => wr,
395
                        d       => data_in( 10 ),
396
                        wclk => clk,
397
                        a0      => adr( 0 ),
398
                        a1      => adr( 1 ),
399
                        a2      => adr( 2 ),
400
                        a3      => adr( 3 ),
401
                        spo     => data_out( 10 ),
402
                        dpra0 => adr( 0 ),
403
                        dpra1 => adr( 1 ),
404
                        dpra2 => adr( 2 ),
405
                        dpra3 => adr( 3 )
406
                );
407
 
408
xram11: ram16x1d
409
                generic map(
410
                        init =>  rom_init_0B
411
                )
412
                port map(
413
                        we      => wr,
414
                        d       => data_in( 11 ),
415
                        wclk => clk,
416
                        a0      => adr( 0 ),
417
                        a1      => adr( 1 ),
418
                        a2      => adr( 2 ),
419
                        a3      => adr( 3 ),
420
                        spo     => data_out( 11 ),
421
                        dpra0 => adr( 0 ),
422
                        dpra1 => adr( 1 ),
423
                        dpra2 => adr( 2 ),
424
                        dpra3 => adr( 3 )
425
                );
426
 
427
xram12: ram16x1d
428
                generic map(
429
                        init =>  rom_init_0C
430
                )
431
                port map(
432
                        we      => wr,
433
                        d       => data_in( 12 ),
434
                        wclk => clk,
435
                        a0      => adr( 0 ),
436
                        a1      => adr( 1 ),
437
                        a2      => adr( 2 ),
438
                        a3      => adr( 3 ),
439
                        spo     => data_out( 12 ),
440
                        dpra0 => adr( 0 ),
441
                        dpra1 => adr( 1 ),
442
                        dpra2 => adr( 2 ),
443
                        dpra3 => adr( 3 )
444
                );
445
 
446
xram13: ram16x1d
447
                generic map(
448
                        init =>  rom_init_0D
449
                )
450
                port map(
451
                        we      => wr,
452
                        d       => data_in( 13 ),
453
                        wclk => clk,
454
                        a0      => adr( 0 ),
455
                        a1      => adr( 1 ),
456
                        a2      => adr( 2 ),
457
                        a3      => adr( 3 ),
458
                        spo     => data_out( 13 ),
459
                        dpra0 => adr( 0 ),
460
                        dpra1 => adr( 1 ),
461
                        dpra2 => adr( 2 ),
462
                        dpra3 => adr( 3 )
463
                );
464
 
465
xram14: ram16x1d
466
                generic map(
467
                        init =>  rom_init_0E
468
                )
469
                port map(
470
                        we      => wr,
471
                        d       => data_in( 14 ),
472
                        wclk => clk,
473
                        a0      => adr( 0 ),
474
                        a1      => adr( 1 ),
475
                        a2      => adr( 2 ),
476
                        a3      => adr( 3 ),
477
                        spo     => data_out( 14 ),
478
                        dpra0 => adr( 0 ),
479
                        dpra1 => adr( 1 ),
480
                        dpra2 => adr( 2 ),
481
                        dpra3 => adr( 3 )
482
                );
483
 
484
xram15: ram16x1d
485
                generic map(
486
                        init =>  rom_init_0F
487
                )
488
                port map(
489
                        we      => wr,
490
                        d       => data_in( 15 ),
491
                        wclk => clk,
492
                        a0      => adr( 0 ),
493
                        a1      => adr( 1 ),
494
                        a2      => adr( 2 ),
495
                        a3      => adr( 3 ),
496
                        spo     => data_out( 15 ),
497
                        dpra0 => adr( 0 ),
498
                        dpra1 => adr( 1 ),
499
                        dpra2 => adr( 2 ),
500
                        dpra3 => adr( 3 )
501
                );
502
 
503
 
504
end ctrl_ram16_v1;

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