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-------------------------------------------------------------------------------
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--
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-- Title : core64_reg_access
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.0
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Óçåë äîñòóïà ê ðåãèñòðàì â ïðîñòðàíñòâàõ BAR0, BAR1
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.core64_type_pkg.all;
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package core64_reg_access_pkg is
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component core64_reg_access is
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port(
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--- General ---
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rstp : in std_logic; --! 1 - ñáðîñ
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clk : in std_logic; --! òàêòîâàÿ ÷àñòîòà ÿäðà - 250 MHz
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--- RX_ENGINE ----
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reg_access : in type_reg_access; --! çàïðîñ íà äîñòóï ê ðåãèñòðàì
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--- TX_ENGINE ----
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reg_access_back : out type_reg_access_back; --! îòâåò íà çàïðîñ
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---- PB_DISP ----
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reg_disp : out type_reg_disp; --! çàïðîñ íà äîñòóï ê ðåãèñòðàì èç BAR1
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reg_disp_back : in type_reg_disp_back; --! îòâåò íà çàïðîñ
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---- BLOCK EXT_FIFO ----
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reg_ext_fifo : out type_reg_ext_fifo; --! çàïðîñ íà äîñòóï ê áëîêàì óïðàâëåíèÿ EXT_FIFO
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reg_ext_fifo_back : in type_reg_ext_fifo_back; --! îòâåò íà çàïðîñ
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---- BAR0 - áëîêè óïðàâëåíèÿ ----
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bp_host_data : out std_logic_vector( 31 downto 0 ); --! øèíà äàííûõ - âûõîä
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bp_data : in std_logic_vector( 31 downto 0 ); --! øèíà äàííûõ - âõîä
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bp_adr : out std_logic_vector( 19 downto 0 ); --! àäðåñ ðåãèñòðà
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bp_we : out std_logic_vector( 3 downto 0 ); --! 1 - çàïèñü â ðåãèñòðû
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bp_rd : out std_logic_vector( 3 downto 0 ); --! 1 - ÷òåíèå èç ðåãèñòðîâ áëîêà
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bp_sel : out std_logic_vector( 1 downto 0 ); --! íîìåð áëîêà äëÿ ÷òåíèÿ
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bp_reg_we : out std_logic; --! 1 - çàïèñü â ðåãèñòð ïî àäðåñàì 0x100000 - 0x1FFFFF
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bp_reg_rd : out std_logic; --! 1 - ÷òåíèå èç ðåãèñòðà ïî àäðåñàì 0x100000 - 0x1FFFFF
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bp_irq : in std_logic --! 1 - çàïðîñ ïðåðûâàíèÿ
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);
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use work.core64_type_pkg.all;
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entity core64_reg_access is
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port(
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--- General ---
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rstp : in std_logic; --! 1 - ñáðîñ
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clk : in std_logic; --! òàêòîâàÿ ÷àñòîòà ÿäðà - 250 MHz
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--- RX_ENGINE ----
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reg_access : in type_reg_access; --! çàïðîñ íà äîñòóï ê ðåãèñòðàì
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--- TX_ENGINE ----
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reg_access_back : out type_reg_access_back; --! îòâåò íà çàïðîñ
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---- PB_DISP ----
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reg_disp : out type_reg_disp; --! çàïðîñ íà äîñòóï ê ðåãèñòðàì èç BAR1
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reg_disp_back : in type_reg_disp_back; --! îòâåò íà çàïðîñ
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---- BLOCK EXT_FIFO ----
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reg_ext_fifo : out type_reg_ext_fifo; --! çàïðîñ íà äîñòóï ê áëîêàì óïðàâëåíèÿ EXT_FIFO
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reg_ext_fifo_back : in type_reg_ext_fifo_back; --! îòâåò íà çàïðîñ
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---- BAR0 - áëîêè óïðàâëåíèÿ ----
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bp_host_data : out std_logic_vector( 31 downto 0 ); --! øèíà äàííûõ - âûõîä
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bp_data : in std_logic_vector( 31 downto 0 ); --! øèíà äàííûõ - âõîä
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bp_adr : out std_logic_vector( 19 downto 0 ); --! àäðåñ ðåãèñòðà
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bp_we : out std_logic_vector( 3 downto 0 ); --! 1 - çàïèñü â ðåãèñòðû
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bp_rd : out std_logic_vector( 3 downto 0 ); --! 1 - ÷òåíèå èç ðåãèñòðîâ áëîêà
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bp_sel : out std_logic_vector( 1 downto 0 ); --! íîìåð áëîêà äëÿ ÷òåíèÿ
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bp_reg_we : out std_logic; --! 1 - çàïèñü â ðåãèñòð ïî àäðåñàì 0x100000 - 0x1FFFFF
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bp_reg_rd : out std_logic; --! 1 - ÷òåíèå èç ðåãèñòðà ïî àäðåñàì 0x100000 - 0x1FFFFF
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bp_irq : in std_logic --! 1 - çàïðîñ ïðåðûâàíèÿ
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);
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end core64_reg_access;
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architecture core64_reg_access of core64_reg_access is
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signal bar0_complete : std_logic;
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signal bar1_complete : std_logic;
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signal adr : std_logic_vector( 31 downto 0 );
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signal bar0_write : std_logic;
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signal bar0_read : std_logic;
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signal bar1_read : std_logic;
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signal bar0i_data : std_logic_vector( 31 downto 0 );
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signal bar0_data : std_logic_vector( 31 downto 0 );
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signal bar1_data : std_logic_vector( 31 downto 0 );
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type stp_type is ( s0, s1, s2 );
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signal stp : stp_type;
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signal st1p : stp_type;
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signal disp_complete : std_logic;
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begin
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bp_adr <= reg_access.adr( 22 downto 3 );
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bp_sel <= reg_access.adr( 9 downto 8 );
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reg_disp.adr <= reg_access.adr( 31 downto 0 );
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reg_ext_fifo.adr <= reg_access.adr( 9 downto 3 );
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bp_host_data <= reg_access.data;
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reg_disp.data <= reg_access.data;
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reg_ext_fifo.data <= reg_access.data;
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reg_access_back.complete <= bar0_complete or bar1_complete after 1 ns when rising_edge( clk );
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adr <= reg_access.adr;
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bp_reg_we <= bar0_write and adr(20) after 1 ns when rising_edge( clk );
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bp_we(0) <= bar0_write and not adr(20) and not adr(10) and not adr(9) and not adr(8) after 1 ns when rising_edge( clk );
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bp_we(1) <= bar0_write and not adr(20) and not adr(10) and not adr(9) and adr(8) after 1 ns when rising_edge( clk );
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bp_we(2) <= bar0_write and not adr(20) and not adr(10) and adr(9) and not adr(8) after 1 ns when rising_edge( clk );
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bp_we(3) <= bar0_write and not adr(20) and not adr(10) and adr(9) and adr(8) after 1 ns when rising_edge( clk );
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bp_reg_rd <= bar0_write and adr(20) after 1 ns when rising_edge( clk );
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bp_rd(0) <= bar0_read and not adr(20) and not adr(10) and not adr(9) and not adr(8) after 1 ns when rising_edge( clk );
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bp_rd(1) <= bar0_read and not adr(20) and not adr(10) and not adr(9) and adr(8) after 1 ns when rising_edge( clk );
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bp_rd(2) <= bar0_read and not adr(20) and not adr(10) and adr(9) and not adr(8) after 1 ns when rising_edge( clk );
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bp_rd(3) <= bar0_read and not adr(20) and not adr(10) and adr(9) and adr(8) after 1 ns when rising_edge( clk );
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reg_ext_fifo.data_we <= bar0_write and not adr(20) and adr(10) after 1 ns when rising_edge( clk );
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bar0i_data <= bp_data when adr(20)='1' or adr(10)='0' else
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reg_ext_fifo_back.data;
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bar0_data <= bar0i_data after 1 ns when rising_edge( clk ) and bar0_read='1';
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bar1_data <= reg_disp_back.data after 1 ns when rising_edge( clk ) and reg_disp_back.data_we='1';
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reg_access_back.data <= bar0_data when reg_access.req_rd(0)='1' else bar1_data;
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reg_access_back.data_we <= bar0_read or bar1_read after 1 ns when rising_edge( clk );
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pr0_state: process( clk ) begin
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if( rising_edge( clk ) ) then
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case( stp ) is
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when s0 =>
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bar0_complete <= '0' after 1 ns;
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bar0_write <= '0' after 1 ns;
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bar0_read <= '0' after 1 ns;
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if( reg_access.req_wr(0)='1' or reg_access.req_rd(0)='1' ) then
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stp <= s1 after 1 ns;
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end if;
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when s1 =>
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bar0_write <= reg_access.req_wr(0) after 1 ns;
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bar0_read <= reg_access.req_rd(0) after 1 ns;
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stp <= s2 after 1 ns;
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when s2 =>
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bar0_write <= '0' after 1 ns;
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bar0_read <= '0' after 1 ns;
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bar0_complete <= '1' after 1 ns;
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if( reg_access.req_wr(0)='0' and reg_access.req_rd(0)='0' ) then
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stp <= s0 after 1 ns;
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end if;
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end case;
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if( rstp='1' ) then
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stp <= s0 after 1 ns;
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end if;
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end if;
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end process;
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disp_complete <= reg_disp_back.complete after 1 ns when rising_edge( clk );
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pr1_state: process( clk ) begin
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if( rising_edge( clk ) ) then
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case( st1p ) is
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when s0 =>
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bar1_complete <= '0' after 1 ns;
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bar1_read <= '0' after 1 ns;
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reg_disp.request_reg_wr <= '0' after 1 ns;
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reg_disp.request_reg_rd <= '0' after 1 ns;
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if( reg_access.req_wr(1)='1' or reg_access.req_rd(1)='1' ) then
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st1p <= s1 after 1 ns;
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end if;
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when s1 =>
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reg_disp.request_reg_wr <= reg_access.req_wr(1) after 1 ns;
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reg_disp.request_reg_rd <= reg_access.req_rd(1) after 1 ns;
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bar1_read <= '1' after 1 ns;
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if( disp_complete='1' ) then
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st1p <= s2 after 1 ns;
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end if;
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when s2 =>
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reg_disp.request_reg_wr <= '0' after 1 ns;
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reg_disp.request_reg_rd <= '0' after 1 ns;
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bar1_read <= '0' after 1 ns;
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bar1_complete <= '1' after 1 ns;
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if( reg_access.req_wr(1)='0' and reg_access.req_rd(1)='0' ) then
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st1p <= s0 after 1 ns;
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end if;
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end case;
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if( rstp='1' ) then
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st1p <= s0 after 1 ns;
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end if;
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end if;
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end process;
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end core64_reg_access;
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