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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_ctrl/] [core64_reg_access.vhd] - Blame information for rev 2

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1 2 dsmv 
-------------------------------------------------------------------------------
2 
--
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-- Title       : core64_reg_access
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-- Author      : Dmitry Smekhov
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-- Company     : Instrumental Systems
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-- E-mail      : dsmv@insys.ru
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--
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-- Version     : 1.0
9 
--
10 
-------------------------------------------------------------------------------
11 
--
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-- Description :  Óçåë äîñòóïà ê ðåãèñòðàì â ïðîñòðàíñòâàõ BAR0, BAR1
13 
--
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-------------------------------------------------------------------------------
15 
 
16 
library ieee;
17 
use ieee.std_logic_1164.all;
18 
 
19 
use work.core64_type_pkg.all;
20 
 
21 
package core64_reg_access_pkg is
22 
 
23 
component core64_reg_access is
24 
        port(
25 
                --- General ---
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                rstp                            : in std_logic;         --! 1 - ñáðîñ
27 
                clk                                     : in std_logic;         --! òàêòîâàÿ ÷àñòîòà ÿäðà - 250 MHz
28 
 
29 
                --- RX_ENGINE ----
30 
                reg_access                      : in  type_reg_access;          --! çàïðîñ íà äîñòóï ê ðåãèñòðàì
31 
 
32 
                --- TX_ENGINE ----
33 
                reg_access_back         : out type_reg_access_back;     --! îòâåò íà çàïðîñ
34 
 
35 
                ---- PB_DISP ----
36 
                reg_disp                        : out type_reg_disp;            --! çàïðîñ íà äîñòóï ê ðåãèñòðàì èç BAR1
37 
                reg_disp_back           : in  type_reg_disp_back;       --! îòâåò íà çàïðîñ
38 
 
39 
                ---- BLOCK EXT_FIFO ----
40 
                reg_ext_fifo            : out type_reg_ext_fifo;                --! çàïðîñ íà äîñòóï ê áëîêàì óïðàâëåíèÿ EXT_FIFO
41 
                reg_ext_fifo_back       : in  type_reg_ext_fifo_back;   --! îòâåò íà çàïðîñ
42 
 
43 
                ---- BAR0 - áëîêè óïðàâëåíèÿ ----
44 
                bp_host_data            : out std_logic_vector( 31 downto 0 );   --! øèíà äàííûõ - âûõîä
45 
                bp_data                         : in  std_logic_vector( 31 downto 0 );  --! øèíà äàííûõ - âõîä
46 
                bp_adr                          : out  std_logic_vector( 19 downto 0 );  --! àäðåñ ðåãèñòðà
47 
                bp_we                           : out std_logic_vector( 3 downto 0 );    --! 1 - çàïèñü â ðåãèñòðû
48 
                bp_rd                           : out std_logic_vector( 3 downto 0 );   --! 1 - ÷òåíèå èç ðåãèñòðîâ áëîêà
49 
                bp_sel                          : out std_logic_vector( 1 downto 0 );    --! íîìåð áëîêà äëÿ ÷òåíèÿ
50 
                bp_reg_we                       : out std_logic;                        --! 1 - çàïèñü â ðåãèñòð ïî àäðåñàì   0x100000 - 0x1FFFFF
51 
                bp_reg_rd                       : out std_logic;                        --! 1 - ÷òåíèå èç ðåãèñòðà ïî àäðåñàì 0x100000 - 0x1FFFFF
52 
                bp_irq                          : in  std_logic                         --! 1 - çàïðîñ ïðåðûâàíèÿ
53 
        );
54 
 
55 
end component;
56 
 
57 
end package;
58 
 
59 
 
60 
 
61 
library ieee;
62 
use ieee.std_logic_1164.all;
63 
 
64 
use work.core64_type_pkg.all;
65 
 
66 
entity core64_reg_access is
67 
        port(
68 
 
69 
                --- General ---
70 
                rstp                            : in std_logic;         --! 1 - ñáðîñ
71 
                clk                                     : in std_logic;         --! òàêòîâàÿ ÷àñòîòà ÿäðà - 250 MHz
72 
 
73 
                --- RX_ENGINE ----
74 
                reg_access                      : in  type_reg_access;          --! çàïðîñ íà äîñòóï ê ðåãèñòðàì
75 
 
76 
                --- TX_ENGINE ----
77 
                reg_access_back         : out type_reg_access_back;     --! îòâåò íà çàïðîñ
78 
 
79 
                ---- PB_DISP ----
80 
                reg_disp                        : out type_reg_disp;            --! çàïðîñ íà äîñòóï ê ðåãèñòðàì èç BAR1
81 
                reg_disp_back           : in  type_reg_disp_back;       --! îòâåò íà çàïðîñ
82 
 
83 
                ---- BLOCK EXT_FIFO ----
84 
                reg_ext_fifo            : out type_reg_ext_fifo;                --! çàïðîñ íà äîñòóï ê áëîêàì óïðàâëåíèÿ EXT_FIFO
85 
                reg_ext_fifo_back       : in  type_reg_ext_fifo_back;   --! îòâåò íà çàïðîñ
86 
 
87 
                ---- BAR0 - áëîêè óïðàâëåíèÿ ----
88 
                bp_host_data            : out std_logic_vector( 31 downto 0 );   --! øèíà äàííûõ - âûõîä
89 
                bp_data                         : in  std_logic_vector( 31 downto 0 );  --! øèíà äàííûõ - âõîä
90 
                bp_adr                          : out std_logic_vector( 19 downto 0 );   --! àäðåñ ðåãèñòðà
91 
                bp_we                           : out std_logic_vector( 3 downto 0 );    --! 1 - çàïèñü â ðåãèñòðû
92 
                bp_rd                           : out std_logic_vector( 3 downto 0 );   --! 1 - ÷òåíèå èç ðåãèñòðîâ áëîêà
93 
                bp_sel                          : out std_logic_vector( 1 downto 0 );    --! íîìåð áëîêà äëÿ ÷òåíèÿ
94 
                bp_reg_we                       : out std_logic;                        --! 1 - çàïèñü â ðåãèñòð ïî àäðåñàì   0x100000 - 0x1FFFFF
95 
                bp_reg_rd                       : out std_logic;                        --! 1 - ÷òåíèå èç ðåãèñòðà ïî àäðåñàì 0x100000 - 0x1FFFFF
96 
                bp_irq                          : in  std_logic                         --! 1 - çàïðîñ ïðåðûâàíèÿ
97 
        );
98 
 
99 
end core64_reg_access;
100 
 
101 
 
102 
architecture core64_reg_access of core64_reg_access is
103 
 
104 
signal  bar0_complete           : std_logic;
105 
signal  bar1_complete           : std_logic;
106 
signal  adr                                     : std_logic_vector( 31 downto 0 );
107 
 
108 
signal  bar0_write                      : std_logic;
109 
signal  bar0_read                       : std_logic;
110 
signal  bar1_read                       : std_logic;
111 
signal  bar0i_data                      : std_logic_vector( 31 downto 0 );
112 
signal  bar0_data                       : std_logic_vector( 31 downto 0 );
113 
 
114 
signal  bar1_data                       : std_logic_vector( 31 downto 0 );
115 
 
116 
type    stp_type        is ( s0, s1, s2 );
117 
signal  stp                                     : stp_type;
118 
signal  st1p                            : stp_type;
119 
 
120 
signal  disp_complete           : std_logic;
121 
 
122 
 
123 
begin
124 
 
125 
bp_adr <= reg_access.adr( 22 downto 3 );
126 
bp_sel <= reg_access.adr( 9 downto 8 );
127 
reg_disp.adr <= reg_access.adr( 31 downto 0 );
128 
reg_ext_fifo.adr <= reg_access.adr( 9 downto 3 );
129 
 
130 
bp_host_data            <= reg_access.data;
131 
reg_disp.data           <= reg_access.data;
132 
reg_ext_fifo.data       <= reg_access.data;
133 
 
134 
reg_access_back.complete <= bar0_complete or bar1_complete after 1 ns when rising_edge( clk );
135 
 
136 
adr <= reg_access.adr;
137 
 
138 
bp_reg_we <= bar0_write and adr(20) after 1 ns when rising_edge( clk );
139 
 
140 
bp_we(0) <= bar0_write and not adr(20) and not adr(10) and not adr(9) and not adr(8) after 1 ns when rising_edge( clk );
141 
bp_we(1) <= bar0_write and not adr(20) and not adr(10) and not adr(9) and     adr(8) after 1 ns when rising_edge( clk );
142 
bp_we(2) <= bar0_write and not adr(20) and not adr(10) and     adr(9) and not adr(8) after 1 ns when rising_edge( clk );
143 
bp_we(3) <= bar0_write and not adr(20) and not adr(10) and     adr(9) and     adr(8) after 1 ns when rising_edge( clk );
144 
 
145 
bp_reg_rd <= bar0_write and adr(20) after 1 ns when rising_edge( clk );
146 
 
147 
bp_rd(0) <= bar0_read and not adr(20) and not adr(10) and not adr(9) and not adr(8) after 1 ns when rising_edge( clk );
148 
bp_rd(1) <= bar0_read and not adr(20) and not adr(10) and not adr(9) and     adr(8) after 1 ns when rising_edge( clk );
149 
bp_rd(2) <= bar0_read and not adr(20) and not adr(10) and     adr(9) and not adr(8) after 1 ns when rising_edge( clk );
150 
bp_rd(3) <= bar0_read and not adr(20) and not adr(10) and     adr(9) and     adr(8) after 1 ns when rising_edge( clk );
151 
 
152 
 
153 
reg_ext_fifo.data_we <= bar0_write and not adr(20) and adr(10) after 1 ns when rising_edge( clk );
154 
 
155 
 
156 
bar0i_data <= bp_data when adr(20)='1' or adr(10)='0' else
157 
                          reg_ext_fifo_back.data;
158 
 
159 
bar0_data <= bar0i_data after 1 ns when rising_edge( clk ) and bar0_read='1';
160 
bar1_data <= reg_disp_back.data after 1 ns when rising_edge( clk ) and reg_disp_back.data_we='1';
161 
 
162 
reg_access_back.data <= bar0_data when reg_access.req_rd(0)='1' else bar1_data;
163 
reg_access_back.data_we <= bar0_read or bar1_read after 1 ns when rising_edge( clk );
164 
 
165 
 
166 
pr0_state: process( clk ) begin
167 
        if( rising_edge( clk ) ) then
168 
 
169 
                case( stp ) is
170 
 
171 
                        when s0 =>
172 
                                bar0_complete <= '0' after 1 ns;
173 
                                bar0_write <= '0' after 1 ns;
174 
                                bar0_read  <= '0' after 1 ns;
175 
 
176 
                                if( reg_access.req_wr(0)='1' or reg_access.req_rd(0)='1' ) then
177 
                                        stp <= s1 after 1 ns;
178 
                                end if;
179 
 
180 
                        when s1 =>
181 
                                bar0_write <= reg_access.req_wr(0) after 1 ns;
182 
                                bar0_read  <= reg_access.req_rd(0) after 1 ns;
183 
                                stp <= s2 after 1 ns;
184 
 
185 
 
186 
                        when s2 =>
187 
                                bar0_write <= '0' after 1 ns;
188 
                                bar0_read  <= '0' after 1 ns;
189 
                                bar0_complete <= '1' after 1 ns;
190 
                                if( reg_access.req_wr(0)='0' and reg_access.req_rd(0)='0' ) then
191 
                                        stp <= s0 after 1 ns;
192 
                                end if;
193 
 
194 
                end case;
195 
 
196 
                if( rstp='1' ) then
197 
                        stp <= s0 after 1 ns;
198 
                end if;
199 
 
200 
        end if;
201 
end process;
202 
 
203 
disp_complete <= reg_disp_back.complete after 1 ns when rising_edge( clk );
204 
 
205 
pr1_state: process( clk ) begin
206 
        if( rising_edge( clk ) ) then
207 
 
208 
                case( st1p ) is
209 
 
210 
                        when s0 =>
211 
                                bar1_complete <= '0' after 1 ns;
212 
                                bar1_read  <= '0' after 1 ns;
213 
                                reg_disp.request_reg_wr <= '0' after 1 ns;
214 
                                reg_disp.request_reg_rd <= '0' after 1 ns;
215 
 
216 
                                if( reg_access.req_wr(1)='1' or reg_access.req_rd(1)='1' ) then
217 
                                        st1p <= s1 after 1 ns;
218 
                                end if;
219 
 
220 
                        when s1 =>
221 
                                reg_disp.request_reg_wr <= reg_access.req_wr(1) after 1 ns;
222 
                                reg_disp.request_reg_rd <= reg_access.req_rd(1) after 1 ns;
223 
                                bar1_read  <= '1' after 1 ns;
224 
 
225 
                                if( disp_complete='1' ) then
226 
                                        st1p <= s2 after 1 ns;
227 
                                end if;
228 
 
229 
 
230 
                        when s2 =>
231 
                                reg_disp.request_reg_wr <= '0' after 1 ns;
232 
                                reg_disp.request_reg_rd <= '0' after 1 ns;
233 
                                bar1_read  <= '0' after 1 ns;
234 
                                bar1_complete <= '1' after 1 ns;
235 
                                if( reg_access.req_wr(1)='0' and reg_access.req_rd(1)='0' ) then
236 
                                        st1p <= s0 after 1 ns;
237 
                                end if;
238 
 
239 
                end case;
240 
 
241 
                if( rstp='1' ) then
242 
                        st1p <= s0 after 1 ns;
243 
                end if;
244 
 
245 
        end if;
246 
end process;
247 
 
248 
 
249 
 
250 
end core64_reg_access;

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