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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_ctrl/] [core64_rx_engine.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
--
-- Title       : core64_rx_engine
-- Author      : Dmitry Smekhov
-- Company     : Instrumental Systems
-- E-mail      : dsmv@insys.ru
--
-- Version     : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : ���������� �������� ������� 
--
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.core64_type_pkg.all;
 
package core64_rx_engine_pkg is
 
component core64_rx_engine is
        port(
 
                --- General ---
                rstp                    : in std_logic;         --! 1 - ����� 
                clk                             : in std_logic;         --! �������� ������� ���� - 250 MHz 
 
                trn_rx                  : in  type_trn_rx;                      --! ���� ������
                trn_rx_back             : out type_trn_rx_back;         --! ���������� � ����� ������
 
                reg_access              : out type_reg_access;          --! ������ �� ������ � ��������� 
 
                rx_tx_engine    : out type_rx_tx_engine;        --! ����� RX->TX 
                tx_rx_engine    : in  type_tx_rx_engine;        --! ����� TX->RX 
 
                rx_ext_fifo             : out type_rx_ext_fifo          --! ����� RX->EXT_FIFO 
 
 
 
        );
end component;
 
end package;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
use work.core64_type_pkg.all;
 
entity core64_rx_engine is
        port(
 
                --- General ---
                rstp                    : in std_logic;         --! 1 - ����� 
                clk                             : in std_logic;         --! �������� ������� ���� - 250 MHz 
 
                trn_rx                  : in  type_trn_rx;                      --! ���� ������
                trn_rx_back             : out type_trn_rx_back;         --! ���������� � ����� ������
 
                reg_access              : out type_reg_access;          --! ������ �� ������ � ��������� 
 
                rx_tx_engine    : out type_rx_tx_engine;        --! ����� RX->TX 
                tx_rx_engine    : in  type_tx_rx_engine;        --! ����� TX->RX 
 
                rx_ext_fifo             : out type_rx_ext_fifo          --! ����� RX->EXT_FIFO 
 
 
 
        );
end core64_rx_engine;
 
 
architecture core64_rx_engine of core64_rx_engine is
 
component ctrl_fifo64x70st is
  port (
    clk                 : in std_logic;
    rst                 : in std_logic;
    din                 : in std_logic_vector(69 downto 0);
    wr_en               : in std_logic;
    rd_en               : in std_logic;
    dout                : out std_logic_vector(69 downto 0);
    full                : out std_logic;
    empty               : out std_logic;
    valid               : out std_logic;
    prog_full   : out std_logic;
    prog_empty  : out std_logic
  );
end component;
 
 
signal  rstpz                   : std_logic;
 
type    stp_type                is ( s0, s1, s2, s3, s31, s32, s4, s5 );
signal  stp                             : stp_type;
 
type    stf_type                is ( s0, s1, s2, s3, s4, s5, s6 );
signal  stf                             : stf_type;
 
signal  trn_rdst_rdy_n                  : std_logic;
signal  trn_rnp_ok_n                    : std_logic;
signal  trn_rcpl_streaming_n    : std_logic;
 
signal  tlp_dw0                                 : std_logic_vector( 31 downto 0 );
signal  tlp_dw1                                 : std_logic_vector( 31 downto 0 );
signal  tlp_dw2                                 : std_logic_vector( 31 downto 0 );
signal  tlp_dw3                                 : std_logic_vector( 31 downto 0 );
 
signal  trn_data                                : std_logic_vector( 63 downto 0 );
signal  trn_data_we                             : std_logic;
 
signal  tlp_cnt                                 : std_logic_vector( 5 downto 0 );
 
signal  request_reg_wr                  : std_logic;
signal  request_reg_rd                  : std_logic;
signal  tlp_complete                    : std_logic;
signal  bar                                             : std_logic_vector( 1 downto 0 );
 
signal  fifo_wr                                 : std_logic;
signal  fifo_wr_z                               : std_logic;
signal  fifo_din                                : std_logic_vector( 69 downto 0 );
 
signal  fifo0_wr                                : std_logic;
signal  fifo0_wr_en                             : std_logic;
signal  fifo0_wr_en_z                   : std_logic;
signal  fifo0_rd                                : std_logic;
signal  fifo0_full                              : std_logic;
signal  fifo0_empty                             : std_logic;
signal  fifo0_valid                             : std_logic;
signal  fifo0_paf                               : std_logic;
signal  fifo0_pae                               : std_logic;
signal  fifo0_dout                              : std_logic_vector( 69 downto 0 );
 
signal  fifo1_wr                                : std_logic;
signal  fifo1_wr_en                             : std_logic;
signal  fifo1_wr_en_z                   : std_logic;
signal  fifo1_rd                                : std_logic;
signal  fifo1_rd_x                              : std_logic;
signal  fifo1_full                              : std_logic;
signal  fifo1_empty                             : std_logic;
signal  fifo1_valid                             : std_logic;
signal  fifo1_paf                               : std_logic;
signal  fifo1_pae                               : std_logic;
signal  fifo1_dout                              : std_logic_vector( 69 downto 0 );
 
signal  data_rx                                 : std_logic_vector( 63 downto 0 );
signal  data_rx_we                              : std_logic;
signal  data_rx_we_en                   : std_logic;
signal  data_lrx                                : std_logic_vector( 31 downto 0 );
signal  data_hrx                                : std_logic_vector( 31 downto 0 );
 
signal  tlp_cp_dw0                              : std_logic_vector( 31 downto 0 );
signal  tlp_cp_dw1                              : std_logic_vector( 31 downto 0 );
signal  tlp_cp_dw2                              : std_logic_vector( 31 downto 0 );
signal  tlp_cp_dw3                              : std_logic_vector( 31 downto 0 );
 
signal  adr_rx                                  : std_logic_vector( 8 downto 0 );
signal  adr_cnt                                 : std_logic_vector( 3 downto 0 );
 
signal  byte_count                              : std_logic_vector( 2 downto 0 );
 
begin
 
rstpz <= rstp after 1 ns when rising_edge( clk );
 
trn_rx_back.trn_rdst_rdy_n                        <= trn_rdst_rdy_n;
trn_rx_back.trn_rnp_ok_n                          <= trn_rnp_ok_n;
trn_rx_back.trn_rcpl_streaming_n      <= trn_rcpl_streaming_n;
 
trn_rnp_ok_n <= '0';
trn_rcpl_streaming_n <= '0';
 
trn_rdst_rdy_n <= fifo0_paf or fifo1_paf;
 
fifo_wr <= not ( trn_rx.trn_rsrc_rdy_n or trn_rdst_rdy_n );
fifo_wr_z <= fifo_wr after 1 ns when rising_edge( clk );
 
fifo_din  <= not trn_rx.trn_rbar_hit_n(1) & not trn_rx.trn_rbar_hit_n(0) &
                                  trn_rx.trn_rerrfwd_n & trn_rx.trn_rrem_n(0) & trn_rx.trn_reof_n & trn_rx.trn_rsof_n &
                                  trn_rx.trn_rd after 1 ns when rising_edge( clk );
 
pr_fifo0_wr: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( rstpz='1' or (fifo_wr='1' and trn_rx.trn_reof_n='0' ) ) then
                        fifo0_wr_en <= '0' after 1 ns;
                elsif( fifo_wr='1' and  trn_rx.trn_rd(63)='0' and trn_rx.trn_rd(61 downto 57)="00000" and trn_rx.trn_rsof_n='0' ) then
                        fifo0_wr_en <= '1' after 1 ns;
                end if;
        end if;
end process;
 
fifo0_wr_en_z <= fifo0_wr_en after 1 ns when rising_edge( clk );
 
fifo0_wr <= fifo_wr_z and (fifo0_wr_en or fifo0_wr_en_z);
 
fifo0_reg: ctrl_fifo64x70st
  port map(
    clk                 => clk,
    rst                 => rstpz,
    din                 => fifo_din,
    wr_en               => fifo0_wr,
    rd_en               => fifo0_rd,
    dout                => fifo0_dout,
    full                => fifo0_full,
    empty               => fifo0_empty,
    valid               => fifo0_valid,
    prog_full   => fifo0_paf,
    prog_empty  => fifo0_pae
  );
 
 
pr_fifo1_wr: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( rstpz='1' or (fifo_wr='1' and trn_rx.trn_reof_n='0' ) ) then
                        fifo1_wr_en <= '0' after 1 ns;
                elsif( fifo_wr='1' and  trn_rx.trn_rd(63 downto 57)="0100101" and trn_rx.trn_rsof_n='0' ) then
                        fifo1_wr_en <= '1' after 1 ns;
                end if;
        end if;
end process;
 
fifo1_wr_en_z <= fifo1_wr_en after 1 ns when rising_edge( clk );
 
fifo1_wr <= fifo_wr_z and (fifo1_wr_en or fifo1_wr_en_z);
 
fifo1_cmpl: ctrl_fifo64x70st
  port map(
    clk                 => clk,
    rst                 => rstpz,
    din                 => fifo_din,
    wr_en               => fifo1_wr,
    rd_en               => fifo1_rd_x,
    dout                => fifo1_dout,
    full                => fifo1_full,
    empty               => fifo1_empty,
    valid               => fifo1_valid,
    prog_full   => fifo1_paf,
    prog_empty  => fifo1_pae
  );
 
 
 
fifo1_rd_x <= fifo1_rd and ( not ( data_rx_we_en  and not fifo1_dout(65) ) );
 
reg_access.adr <= tlp_dw2;
 
reg_access.data( 7 downto 0 )   <= tlp_dw3( 31 downto 24 );
reg_access.data( 15 downto 8 )  <= tlp_dw3( 23 downto 16 );
reg_access.data( 23 downto 16 ) <= tlp_dw3( 15 downto 8 );
reg_access.data( 31 downto 24 ) <= tlp_dw3( 7 downto 0 );
 
reg_access.req_wr(0) <=request_reg_wr and bar(0);
reg_access.req_wr(1) <=request_reg_wr and bar(1);
reg_access.req_rd(0) <=request_reg_rd and ( bar(0) or ( not (bar(0) or bar(1)) ) );
reg_access.req_rd(1) <=request_reg_rd and bar(1);
 
bar(0) <= fifo0_dout(68);
bar(1) <= fifo0_dout(69);
 
rx_tx_engine.request_reg_wr <= request_reg_wr;
rx_tx_engine.request_reg_rd <= request_reg_rd;
rx_tx_engine.request_tag <= tlp_dw1( 15 downto 8 );
rx_tx_engine.request_tc  <= tlp_dw0( 22 downto 20 );
rx_tx_engine.request_attr <= tlp_dw0( 7 downto 4 );
rx_tx_engine.request_id <= tlp_dw1( 31 downto 16 );
rx_tx_engine.lower_adr <= tlp_dw2( 6 downto 2 );
rx_tx_engine.byte_count <= byte_count after 1 ns when rising_edge( clk );
 
byte_count <= "000" when request_reg_rd='0' else
                          "100" when tlp_dw1( 3 downto 0 )="1111" else
                          "010" when tlp_dw1( 3 downto 0 )="0011" or tlp_dw1( 3 downto 0 )="0110" or tlp_dw1( 3 downto 0 )="1100" else
                          "001";-- when tlp_dw1( 3 downto 0 )="0001" or tlp_dw1( 3 downto 0 )="0010" or tlp_dw1( 3 downto 0 )="0100" or tlp_dw1( 3 downto 0 )="1000" 
 
 
pr_stp: process( clk ) begin
        if( rising_edge( clk ) ) then
 
                case( stp ) is
                        when s0 =>
                                if( fifo0_empty='0' ) then
                                        stp <= s1 after 1 ns;
                                end if;
                                request_reg_wr <= '0' after 1 ns;
                                request_reg_rd <= '0' after 1 ns;
                                fifo0_rd <= '0' after 1 ns;
 
                        when s1 =>
                                        stp <= s2 after 1 ns;
                                        fifo0_rd <= '1' after 1 ns;
 
                        when s2 =>
                                        stp <= s3 after 1 ns;
                                        fifo0_rd <= '0' after 1 ns;
 
                        when s3 =>
                                        tlp_dw0 <= fifo0_dout( 63 downto 32 ) after 1 ns;
                                        tlp_dw1 <= fifo0_dout( 31 downto 0 ) after 1 ns;
                                        if( fifo0_empty='0' ) then
                                                stp <= s31 after 1 ns;
                                        end if;
 
                        when s31 =>
                                        fifo0_rd <= '1' after 1 ns;
                                        stp <= s32 after 1 ns;
 
                        when s32 =>
                                        fifo0_rd <= '0' after 1 ns;
                                        stp <= s4 after 1 ns;
 
                        when s4 =>
                                        tlp_dw2 <= fifo0_dout( 63 downto 32 ) after 1 ns;
                                        tlp_dw3 <= fifo0_dout( 31 downto 0 ) after 1 ns;
 
                                        if( tlp_dw0(30)='1' ) then
                                                request_reg_wr <= '1' after 1 ns;
                                        else
                                                request_reg_rd <= '1' after 1 ns;
                                        end if;
                                        stp <= s5 after 1 ns;
 
                        when s5 =>
                                        if( tx_rx_engine.complete_reg='1' ) then
                                                stp <= s0 after 1 ns;
                                        end if;
 
                end case;
 
 
 
                if( rstpz='1' ) then
                        stp <= s0 after 1 ns;
                end if;
 
        end if;
end process;
 
 
pr_stf: process( clk ) begin
 
        if( rising_edge( clk ) ) then
 
                case( stf ) is
 
                        when s0 =>
                        --if( fifo1_empty='0' ) then
                                if( fifo1_pae='0' ) then
                                        stf <= s1 after 1 ns;
                                end if;
                                fifo1_rd <= '0' after 1 ns;
                                data_rx_we_en   <= '0' after 1 ns;
 
                        when s1 =>
                                fifo1_rd <= '1' after 1 ns;
                                stf <= s2 after 1 ns;
 
                        when s2 =>
                                stf <= s3 after 1 ns;
 
                        when s3 =>
                                        tlp_cp_dw0   <= fifo1_dout( 63 downto 32 ) after 1 ns;
                                        tlp_cp_dw1 <= fifo1_dout( 31 downto 0 ) after 1 ns;
                                        fifo1_rd <= '0' after 1 ns;
                                        stf <= s4 after 1 ns;
 
                        when s4 =>
                                        tlp_cp_dw2 <= fifo1_dout( 63 downto 32 ) after 1 ns;
                                        tlp_cp_dw3 <= fifo1_dout( 31 downto 0 ) after 1 ns;
                                        if( tlp_cp_dw0( 30 )='1' ) then
                                                stf <= s5 after 1 ns;   -- ���� ������ --
                                        else
                                                stf <= s6 after 1 ns;   -- ��� ������ --
                                        end if;
 
 
                        when s5 =>
 
                                        if( fifo1_dout(65)='0' and fifo1_valid='1' ) then
                                                stf <= s6 after 1 ns;
                                                fifo1_rd <= '0' after 1 ns;
                                                data_rx_we_en   <= '0' after 1 ns;
                                        else
                                                fifo1_rd <= '1' after 1 ns;
                                                data_rx_we_en   <= '1' after 1 ns;
                                        end if;
 
                        when s6 =>
                                        stf <= s0 after 1 ns;
 
 
 
                end case;
 
                if( rstpz='1' ) then
                        stf <= s0 after 1 ns;
                end if;
 
        end if;
 
 
end process;
 
data_rx_we <= fifo1_valid and data_rx_we_en;
 
data_lrx <= fifo1_dout( 31 downto 0 ) after 1 ns when rising_edge( clk ) and fifo1_valid='1';
data_hrx <= fifo1_dout( 63 downto 32 );
 
data_rx( 32+31 downto 32+24 )  <= data_hrx( 7 downto 0 );
data_rx( 32+23 downto 32+16 )  <= data_hrx( 15 downto 8 );
data_rx( 32+15 downto 32+8 )   <= data_hrx( 23 downto 16 );
data_rx( 32+7 downto 32+0 )    <= data_hrx( 31 downto 24 );
 
 
data_rx( 31 downto 24 )  <= data_lrx( 7 downto 0 );
data_rx( 23 downto 16 )  <= data_lrx( 15 downto 8 );
data_rx( 15 downto 8 )   <= data_lrx( 23 downto 16 );
data_rx( 7 downto 0 )    <= data_lrx( 31 downto 24 );
 
pr_adr_cnt: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( stf/=s5 ) then
                        adr_cnt <= "0000" after 1 ns;
                elsif( data_rx_we='1' ) then
                        adr_cnt( 2 downto 0 ) <= adr_cnt( 2 downto 0 ) + 1 after 1 ns;
                        if( adr_cnt( 2 downto 0 )="111" ) then
                                adr_cnt( 3 ) <= '1' after 1 ns;
                        end if;
                end if;
        end if;
end process;
 
adr_rx( 2 downto 0 ) <= adr_cnt( 2 downto 0 );
adr_rx( 3 ) <=  tlp_cp_dw2(6) or adr_cnt( 3 );
adr_rx( 8 downto 4 ) <= tlp_cp_dw2( 12 downto 8 );
 
rx_ext_fifo.adr <= adr_rx after 1 ns when rising_edge( clk );
rx_ext_fifo.data <= data_rx after 1 ns when rising_edge( clk );
rx_ext_fifo.data_we <= data_rx_we after 1 ns when rising_edge( clk );
 
rx_tx_engine.complete_we <= data_rx_we after 1 ns when rising_edge( clk );
 
end core64_rx_engine;

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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_ctrl/] [core64_rx_engine.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dsmv	`-------------------------------------------------------------------------------`
2			`--`
3			`-- Title : core64_rx_engine`
4			`-- Author : Dmitry Smekhov`
5			`-- Company : Instrumental Systems`
6			`-- E-mail : dsmv@insys.ru`
7			`--`
8			`-- Version : 1.0`
9			`--`
10			`-------------------------------------------------------------------------------`
11			`--`
12			`-- Description : �� `
13			`--`
14			`-------------------------------------------------------------------------------`
15
16
17			`library ieee;`
18			`use ieee.std_logic_1164.all;`
19
20			`use work.core64_type_pkg.all;`
21
22			`package core64_rx_engine_pkg is`
23
24			`component core64_rx_engine is`
25			`port(`
26
27			`--- General ---`
28			`rstp : in std_logic; --! 1 - ��`
29			`clk : in std_logic; --! �� - 250 MHz`
30
31			`trn_rx : in type_trn_rx; --! �� `
32			`trn_rx_back : out type_trn_rx_back; --! �� `
33
34			`reg_access : out type_reg_access; --! �� `
35
36			`rx_tx_engine : out type_rx_tx_engine; --! �� RX->TX`
37			`tx_rx_engine : in type_tx_rx_engine; --! �� TX->RX`
38
39			`rx_ext_fifo : out type_rx_ext_fifo --! �� RX->EXT_FIFO`
40
41
42
43			`);`
44			`end component;`
45
46			`end package;`
47
48			`library ieee;`
49			`use ieee.std_logic_1164.all;`
50			`use ieee.std_logic_arith.all;`
51			`use ieee.std_logic_unsigned.all;`
52
53			`use work.core64_type_pkg.all;`
54
55			`entity core64_rx_engine is`
56			`port(`
57
58			`--- General ---`
59			`rstp : in std_logic; --! 1 - ��`
60			`clk : in std_logic; --! �� - 250 MHz`
61
62			`trn_rx : in type_trn_rx; --! �� `
63			`trn_rx_back : out type_trn_rx_back; --! �� `
64
65			`reg_access : out type_reg_access; --! �� `
66
67			`rx_tx_engine : out type_rx_tx_engine; --! �� RX->TX`
68			`tx_rx_engine : in type_tx_rx_engine; --! �� TX->RX`
69
70			`rx_ext_fifo : out type_rx_ext_fifo --! �� RX->EXT_FIFO`
71
72
73
74			`);`
75			`end core64_rx_engine;`
76
77
78			`architecture core64_rx_engine of core64_rx_engine is`
79
80			`component ctrl_fifo64x70st is`
81			`port (`
82			`clk : in std_logic;`
83			`rst : in std_logic;`
84			`din : in std_logic_vector(69 downto 0);`
85			`wr_en : in std_logic;`
86			`rd_en : in std_logic;`
87			`dout : out std_logic_vector(69 downto 0);`
88			`full : out std_logic;`
89			`empty : out std_logic;`
90			`valid : out std_logic;`
91			`prog_full : out std_logic;`
92			`prog_empty : out std_logic`
93			`);`
94			`end component;`
95
96
97			`signal rstpz : std_logic;`
98
99			`type stp_type is ( s0, s1, s2, s3, s31, s32, s4, s5 );`
100			`signal stp : stp_type;`
101
102			`type stf_type is ( s0, s1, s2, s3, s4, s5, s6 );`
103			`signal stf : stf_type;`
104
105			`signal trn_rdst_rdy_n : std_logic;`
106			`signal trn_rnp_ok_n : std_logic;`
107			`signal trn_rcpl_streaming_n : std_logic;`
108
109			`signal tlp_dw0 : std_logic_vector( 31 downto 0 );`
110			`signal tlp_dw1 : std_logic_vector( 31 downto 0 );`
111			`signal tlp_dw2 : std_logic_vector( 31 downto 0 );`
112			`signal tlp_dw3 : std_logic_vector( 31 downto 0 );`
113
114			`signal trn_data : std_logic_vector( 63 downto 0 );`
115			`signal trn_data_we : std_logic;`
116
117			`signal tlp_cnt : std_logic_vector( 5 downto 0 );`
118
119			`signal request_reg_wr : std_logic;`
120			`signal request_reg_rd : std_logic;`
121			`signal tlp_complete : std_logic;`
122			`signal bar : std_logic_vector( 1 downto 0 );`
123
124			`signal fifo_wr : std_logic;`
125			`signal fifo_wr_z : std_logic;`
126			`signal fifo_din : std_logic_vector( 69 downto 0 );`
127
128			`signal fifo0_wr : std_logic;`
129			`signal fifo0_wr_en : std_logic;`
130			`signal fifo0_wr_en_z : std_logic;`
131			`signal fifo0_rd : std_logic;`
132			`signal fifo0_full : std_logic;`
133			`signal fifo0_empty : std_logic;`
134			`signal fifo0_valid : std_logic;`
135			`signal fifo0_paf : std_logic;`
136			`signal fifo0_pae : std_logic;`
137			`signal fifo0_dout : std_logic_vector( 69 downto 0 );`
138
139			`signal fifo1_wr : std_logic;`
140			`signal fifo1_wr_en : std_logic;`
141			`signal fifo1_wr_en_z : std_logic;`
142			`signal fifo1_rd : std_logic;`
143			`signal fifo1_rd_x : std_logic;`
144			`signal fifo1_full : std_logic;`
145			`signal fifo1_empty : std_logic;`
146			`signal fifo1_valid : std_logic;`
147			`signal fifo1_paf : std_logic;`
148			`signal fifo1_pae : std_logic;`
149			`signal fifo1_dout : std_logic_vector( 69 downto 0 );`
150
151			`signal data_rx : std_logic_vector( 63 downto 0 );`
152			`signal data_rx_we : std_logic;`
153			`signal data_rx_we_en : std_logic;`
154			`signal data_lrx : std_logic_vector( 31 downto 0 );`
155			`signal data_hrx : std_logic_vector( 31 downto 0 );`
156
157			`signal tlp_cp_dw0 : std_logic_vector( 31 downto 0 );`
158			`signal tlp_cp_dw1 : std_logic_vector( 31 downto 0 );`
159			`signal tlp_cp_dw2 : std_logic_vector( 31 downto 0 );`
160			`signal tlp_cp_dw3 : std_logic_vector( 31 downto 0 );`
161
162			`signal adr_rx : std_logic_vector( 8 downto 0 );`
163			`signal adr_cnt : std_logic_vector( 3 downto 0 );`
164
165			`signal byte_count : std_logic_vector( 2 downto 0 );`
166
167			`begin`
168
169			`rstpz <= rstp after 1 ns when rising_edge( clk );`
170
171			`trn_rx_back.trn_rdst_rdy_n <= trn_rdst_rdy_n;`
172			`trn_rx_back.trn_rnp_ok_n <= trn_rnp_ok_n;`
173			`trn_rx_back.trn_rcpl_streaming_n <= trn_rcpl_streaming_n;`
174
175			`trn_rnp_ok_n <= '0';`
176			`trn_rcpl_streaming_n <= '0';`
177
178			`trn_rdst_rdy_n <= fifo0_paf or fifo1_paf;`
179
180			`fifo_wr <= not ( trn_rx.trn_rsrc_rdy_n or trn_rdst_rdy_n );`
181			`fifo_wr_z <= fifo_wr after 1 ns when rising_edge( clk );`
182
183			`fifo_din <= not trn_rx.trn_rbar_hit_n(1) & not trn_rx.trn_rbar_hit_n(0) &`
184			`trn_rx.trn_rerrfwd_n & trn_rx.trn_rrem_n(0) & trn_rx.trn_reof_n & trn_rx.trn_rsof_n &`
185			`trn_rx.trn_rd after 1 ns when rising_edge( clk );`
186
187			`pr_fifo0_wr: process( clk ) begin`
188			`if( rising_edge( clk ) ) then`
189			`if( rstpz='1' or (fifo_wr='1' and trn_rx.trn_reof_n='0' ) ) then`
190			`fifo0_wr_en <= '0' after 1 ns;`
191			`elsif( fifo_wr='1' and trn_rx.trn_rd(63)='0' and trn_rx.trn_rd(61 downto 57)="00000" and trn_rx.trn_rsof_n='0' ) then`
192			`fifo0_wr_en <= '1' after 1 ns;`
193			`end if;`
194			`end if;`
195			`end process;`
196
197			`fifo0_wr_en_z <= fifo0_wr_en after 1 ns when rising_edge( clk );`
198
199			`fifo0_wr <= fifo_wr_z and (fifo0_wr_en or fifo0_wr_en_z);`
200
201			`fifo0_reg: ctrl_fifo64x70st`
202			`port map(`
203			`clk => clk,`
204			`rst => rstpz,`
205			`din => fifo_din,`
206			`wr_en => fifo0_wr,`
207			`rd_en => fifo0_rd,`
208			`dout => fifo0_dout,`
209			`full => fifo0_full,`
210			`empty => fifo0_empty,`
211			`valid => fifo0_valid,`
212			`prog_full => fifo0_paf,`
213			`prog_empty => fifo0_pae`
214			`);`
215
216
217			`pr_fifo1_wr: process( clk ) begin`
218			`if( rising_edge( clk ) ) then`
219			`if( rstpz='1' or (fifo_wr='1' and trn_rx.trn_reof_n='0' ) ) then`
220			`fifo1_wr_en <= '0' after 1 ns;`
221			`elsif( fifo_wr='1' and trn_rx.trn_rd(63 downto 57)="0100101" and trn_rx.trn_rsof_n='0' ) then`
222			`fifo1_wr_en <= '1' after 1 ns;`
223			`end if;`
224			`end if;`
225			`end process;`
226
227			`fifo1_wr_en_z <= fifo1_wr_en after 1 ns when rising_edge( clk );`
228
229			`fifo1_wr <= fifo_wr_z and (fifo1_wr_en or fifo1_wr_en_z);`
230
231			`fifo1_cmpl: ctrl_fifo64x70st`
232			`port map(`
233			`clk => clk,`
234			`rst => rstpz,`
235			`din => fifo_din,`
236			`wr_en => fifo1_wr,`
237			`rd_en => fifo1_rd_x,`
238			`dout => fifo1_dout,`
239			`full => fifo1_full,`
240			`empty => fifo1_empty,`
241			`valid => fifo1_valid,`
242			`prog_full => fifo1_paf,`
243			`prog_empty => fifo1_pae`
244			`);`
245
246
247
248			`fifo1_rd_x <= fifo1_rd and ( not ( data_rx_we_en and not fifo1_dout(65) ) );`
249
250			`reg_access.adr <= tlp_dw2;`
251
252			`reg_access.data( 7 downto 0 ) <= tlp_dw3( 31 downto 24 );`
253			`reg_access.data( 15 downto 8 ) <= tlp_dw3( 23 downto 16 );`
254			`reg_access.data( 23 downto 16 ) <= tlp_dw3( 15 downto 8 );`
255			`reg_access.data( 31 downto 24 ) <= tlp_dw3( 7 downto 0 );`
256
257			`reg_access.req_wr(0) <=request_reg_wr and bar(0);`
258			`reg_access.req_wr(1) <=request_reg_wr and bar(1);`
259			`reg_access.req_rd(0) <=request_reg_rd and ( bar(0) or ( not (bar(0) or bar(1)) ) );`
260			`reg_access.req_rd(1) <=request_reg_rd and bar(1);`
261
262			`bar(0) <= fifo0_dout(68);`
263			`bar(1) <= fifo0_dout(69);`
264
265			`rx_tx_engine.request_reg_wr <= request_reg_wr;`
266			`rx_tx_engine.request_reg_rd <= request_reg_rd;`
267			`rx_tx_engine.request_tag <= tlp_dw1( 15 downto 8 );`
268			`rx_tx_engine.request_tc <= tlp_dw0( 22 downto 20 );`
269			`rx_tx_engine.request_attr <= tlp_dw0( 7 downto 4 );`
270			`rx_tx_engine.request_id <= tlp_dw1( 31 downto 16 );`
271			`rx_tx_engine.lower_adr <= tlp_dw2( 6 downto 2 );`
272			`rx_tx_engine.byte_count <= byte_count after 1 ns when rising_edge( clk );`
273
274			`byte_count <= "000" when request_reg_rd='0' else`
275			`"100" when tlp_dw1( 3 downto 0 )="1111" else`
276			`"010" when tlp_dw1( 3 downto 0 )="0011" or tlp_dw1( 3 downto 0 )="0110" or tlp_dw1( 3 downto 0 )="1100" else`
277			`"001";-- when tlp_dw1( 3 downto 0 )="0001" or tlp_dw1( 3 downto 0 )="0010" or tlp_dw1( 3 downto 0 )="0100" or tlp_dw1( 3 downto 0 )="1000"`
278
279
280			`pr_stp: process( clk ) begin`
281			`if( rising_edge( clk ) ) then`
282
283			`case( stp ) is`
284			`when s0 =>`
285			`if( fifo0_empty='0' ) then`
286			`stp <= s1 after 1 ns;`
287			`end if;`
288			`request_reg_wr <= '0' after 1 ns;`
289			`request_reg_rd <= '0' after 1 ns;`
290			`fifo0_rd <= '0' after 1 ns;`
291
292			`when s1 =>`
293			`stp <= s2 after 1 ns;`
294			`fifo0_rd <= '1' after 1 ns;`
295
296			`when s2 =>`
297			`stp <= s3 after 1 ns;`
298			`fifo0_rd <= '0' after 1 ns;`
299
300			`when s3 =>`
301			`tlp_dw0 <= fifo0_dout( 63 downto 32 ) after 1 ns;`
302			`tlp_dw1 <= fifo0_dout( 31 downto 0 ) after 1 ns;`
303			`if( fifo0_empty='0' ) then`
304			`stp <= s31 after 1 ns;`
305			`end if;`
306
307			`when s31 =>`
308			`fifo0_rd <= '1' after 1 ns;`
309			`stp <= s32 after 1 ns;`
310
311			`when s32 =>`
312			`fifo0_rd <= '0' after 1 ns;`
313			`stp <= s4 after 1 ns;`
314
315			`when s4 =>`
316			`tlp_dw2 <= fifo0_dout( 63 downto 32 ) after 1 ns;`
317			`tlp_dw3 <= fifo0_dout( 31 downto 0 ) after 1 ns;`
318
319			`if( tlp_dw0(30)='1' ) then`
320			`request_reg_wr <= '1' after 1 ns;`
321			`else`
322			`request_reg_rd <= '1' after 1 ns;`
323			`end if;`
324			`stp <= s5 after 1 ns;`
325
326			`when s5 =>`
327			`if( tx_rx_engine.complete_reg='1' ) then`
328			`stp <= s0 after 1 ns;`
329			`end if;`
330
331			`end case;`
332
333
334
335			`if( rstpz='1' ) then`
336			`stp <= s0 after 1 ns;`
337			`end if;`
338
339			`end if;`
340			`end process;`
341
342
343			`pr_stf: process( clk ) begin`
344
345			`if( rising_edge( clk ) ) then`
346
347			`case( stf ) is`
348
349			`when s0 =>`
350			`--if( fifo1_empty='0' ) then`
351			`if( fifo1_pae='0' ) then`
352			`stf <= s1 after 1 ns;`
353			`end if;`
354			`fifo1_rd <= '0' after 1 ns;`
355			`data_rx_we_en <= '0' after 1 ns;`
356
357			`when s1 =>`
358			`fifo1_rd <= '1' after 1 ns;`
359			`stf <= s2 after 1 ns;`
360
361			`when s2 =>`
362			`stf <= s3 after 1 ns;`
363
364			`when s3 =>`
365			`tlp_cp_dw0 <= fifo1_dout( 63 downto 32 ) after 1 ns;`
366			`tlp_cp_dw1 <= fifo1_dout( 31 downto 0 ) after 1 ns;`
367			`fifo1_rd <= '0' after 1 ns;`
368			`stf <= s4 after 1 ns;`
369
370			`when s4 =>`
371			`tlp_cp_dw2 <= fifo1_dout( 63 downto 32 ) after 1 ns;`
372			`tlp_cp_dw3 <= fifo1_dout( 31 downto 0 ) after 1 ns;`
373			`if( tlp_cp_dw0( 30 )='1' ) then`
374			`stf <= s5 after 1 ns; -- �� --`
375			`else`
376			`stf <= s6 after 1 ns; -- �� --`
377			`end if;`
378
379
380			`when s5 =>`
381
382			`if( fifo1_dout(65)='0' and fifo1_valid='1' ) then`
383			`stf <= s6 after 1 ns;`
384			`fifo1_rd <= '0' after 1 ns;`
385			`data_rx_we_en <= '0' after 1 ns;`
386			`else`
387			`fifo1_rd <= '1' after 1 ns;`
388			`data_rx_we_en <= '1' after 1 ns;`
389			`end if;`
390
391			`when s6 =>`
392			`stf <= s0 after 1 ns;`
393
394
395
396			`end case;`
397
398			`if( rstpz='1' ) then`
399			`stf <= s0 after 1 ns;`
400			`end if;`
401
402			`end if;`
403
404
405			`end process;`
406
407			`data_rx_we <= fifo1_valid and data_rx_we_en;`
408
409			`data_lrx <= fifo1_dout( 31 downto 0 ) after 1 ns when rising_edge( clk ) and fifo1_valid='1';`
410			`data_hrx <= fifo1_dout( 63 downto 32 );`
411
412			`data_rx( 32+31 downto 32+24 ) <= data_hrx( 7 downto 0 );`
413			`data_rx( 32+23 downto 32+16 ) <= data_hrx( 15 downto 8 );`
414			`data_rx( 32+15 downto 32+8 ) <= data_hrx( 23 downto 16 );`
415			`data_rx( 32+7 downto 32+0 ) <= data_hrx( 31 downto 24 );`
416
417
418			`data_rx( 31 downto 24 ) <= data_lrx( 7 downto 0 );`
419			`data_rx( 23 downto 16 ) <= data_lrx( 15 downto 8 );`
420			`data_rx( 15 downto 8 ) <= data_lrx( 23 downto 16 );`
421			`data_rx( 7 downto 0 ) <= data_lrx( 31 downto 24 );`
422
423			`pr_adr_cnt: process( clk ) begin`
424			`if( rising_edge( clk ) ) then`
425			`if( stf/=s5 ) then`
426			`adr_cnt <= "0000" after 1 ns;`
427			`elsif( data_rx_we='1' ) then`
428			`adr_cnt( 2 downto 0 ) <= adr_cnt( 2 downto 0 ) + 1 after 1 ns;`
429			`if( adr_cnt( 2 downto 0 )="111" ) then`
430			`adr_cnt( 3 ) <= '1' after 1 ns;`
431			`end if;`
432			`end if;`
433			`end if;`
434			`end process;`
435
436			`adr_rx( 2 downto 0 ) <= adr_cnt( 2 downto 0 );`
437			`adr_rx( 3 ) <= tlp_cp_dw2(6) or adr_cnt( 3 );`
438			`adr_rx( 8 downto 4 ) <= tlp_cp_dw2( 12 downto 8 );`
439
440			`rx_ext_fifo.adr <= adr_rx after 1 ns when rising_edge( clk );`
441			`rx_ext_fifo.data <= data_rx after 1 ns when rising_edge( clk );`
442			`rx_ext_fifo.data_we <= data_rx_we after 1 ns when rising_edge( clk );`
443
444			`rx_tx_engine.complete_we <= data_rx_we after 1 ns when rising_edge( clk );`
445
446			`end core64_rx_engine;`