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-------------------------------------------------------------------------------
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--
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-- Title : core64_rx_engine_m2
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.1
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Обработчик входящих пакетов
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-- Модификация 2 - используется интерфейс AXI
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.1 19.06.2012
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-- Добавлено формирование byte_count
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.0 16.08.2011
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-- Создан из core64_rx_engine v1.0
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.core64_type_pkg.all;
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package core64_rx_engine_m2_pkg is
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component core64_rx_engine_m2 is
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port(
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--- General ---
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rstp : in std_logic; --! 1 - сброс
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clk : in std_logic; --! тактовая частота ядра - 250 MHz
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trn_rx : in type_axi_rx; --! приём пакета
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trn_rx_back : out type_axi_rx_back; --! готовность к приёму пакета
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reg_access : out type_reg_access; --! запрос на доступ к регистрам
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rx_tx_engine : out type_rx_tx_engine; --! обмен RX->TX
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tx_rx_engine : in type_tx_rx_engine; --! обмен TX->RX
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rx_ext_fifo : out type_rx_ext_fifo --! обмен RX->EXT_FIFO
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);
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use work.core64_type_pkg.all;
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entity core64_rx_engine_m2 is
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port(
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--- General ---
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rstp : in std_logic; --! 1 - сброс
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clk : in std_logic; --! тактовая частота ядра - 250 MHz
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trn_rx : in type_axi_rx; --! приём пакета
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trn_rx_back : out type_axi_rx_back; --! готовность к приёму пакета
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reg_access : out type_reg_access; --! запрос на доступ к регистрам
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rx_tx_engine : out type_rx_tx_engine; --! обмен RX->TX
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tx_rx_engine : in type_tx_rx_engine; --! обмен TX->RX
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rx_ext_fifo : out type_rx_ext_fifo --! обмен RX->EXT_FIFO
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);
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end core64_rx_engine_m2;
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architecture core64_rx_engine_m2 of core64_rx_engine_m2 is
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component ctrl_fifo64x70st is
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port (
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clk : in std_logic;
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rst : in std_logic;
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din : in std_logic_vector(69 downto 0);
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wr_en : in std_logic;
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rd_en : in std_logic;
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dout : out std_logic_vector(69 downto 0);
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full : out std_logic;
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empty : out std_logic;
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valid : out std_logic;
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prog_full : out std_logic;
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prog_empty : out std_logic
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);
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end component;
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signal rstpz : std_logic;
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type stp_type is ( s0, s1, s2, s3, s31, s32, s4, s5 );
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signal stp : stp_type;
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type stf_type is ( s0, s1, s2, s3, s4, s5, s6 );
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signal stf : stf_type;
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signal trn_rdst_rdy_n : std_logic;
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signal trn_rnp_ok_n : std_logic;
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signal trn_rcpl_streaming_n : std_logic;
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signal tlp_dw0 : std_logic_vector( 31 downto 0 );
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signal tlp_dw1 : std_logic_vector( 31 downto 0 );
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signal tlp_dw2 : std_logic_vector( 31 downto 0 );
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signal tlp_dw3 : std_logic_vector( 31 downto 0 );
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signal trn_data : std_logic_vector( 63 downto 0 );
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signal trn_data_we : std_logic;
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signal tlp_cnt : std_logic_vector( 5 downto 0 );
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signal request_reg_wr : std_logic;
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signal request_reg_rd : std_logic;
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signal tlp_complete : std_logic;
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signal bar : std_logic_vector( 1 downto 0 );
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signal fifo_wr : std_logic;
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signal fifo_wr_z : std_logic;
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signal fifo_din : std_logic_vector( 69 downto 0 );
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signal fifo0_wr : std_logic;
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signal fifo0_wr_en : std_logic;
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signal fifo0_wr_en_z : std_logic;
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signal fifo0_rd : std_logic;
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signal fifo0_full : std_logic;
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signal fifo0_empty : std_logic;
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signal fifo0_valid : std_logic;
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signal fifo0_paf : std_logic;
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signal fifo0_pae : std_logic;
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signal fifo0_dout : std_logic_vector( 69 downto 0 );
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signal fifo1_wr : std_logic;
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signal fifo1_wr_en : std_logic;
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signal fifo1_wr_en_z : std_logic;
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signal fifo1_rd : std_logic;
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signal fifo1_rd_x : std_logic;
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signal fifo1_full : std_logic;
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signal fifo1_empty : std_logic;
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signal fifo1_valid : std_logic;
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signal fifo1_paf : std_logic;
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signal fifo1_pae : std_logic;
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signal fifo1_dout : std_logic_vector( 69 downto 0 );
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signal data_rx : std_logic_vector( 63 downto 0 );
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signal data_rx_we : std_logic;
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signal data_rx_we_en : std_logic;
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signal data_lrx : std_logic_vector( 31 downto 0 );
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signal data_hrx : std_logic_vector( 31 downto 0 );
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signal tlp_cp_dw0 : std_logic_vector( 31 downto 0 );
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signal tlp_cp_dw1 : std_logic_vector( 31 downto 0 );
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signal tlp_cp_dw2 : std_logic_vector( 31 downto 0 );
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signal tlp_cp_dw3 : std_logic_vector( 31 downto 0 );
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signal adr_rx : std_logic_vector( 8 downto 0 );
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signal adr_cnt : std_logic_vector( 3 downto 0 );
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signal axis_rx_tready : std_logic;
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signal rx_first : std_logic;
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signal byte_count : std_logic_vector( 2 downto 0 );
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begin
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rstpz <= rstp after 1 ns when rising_edge( clk );
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--trn_rx_back.trn_rdst_rdy_n <= trn_rdst_rdy_n;
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--trn_rx_back.trn_rnp_ok_n <= trn_rnp_ok_n;
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--trn_rx_back.trn_rcpl_streaming_n <= trn_rcpl_streaming_n;
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trn_rnp_ok_n <= '0';
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trn_rcpl_streaming_n <= '0';
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trn_rdst_rdy_n <= fifo0_paf or fifo1_paf;
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axis_rx_tready <= not( fifo0_paf or fifo1_paf ) after 1 ns when rising_edge( clk );
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fifo_wr <= trn_rx.m_axis_rx_tvalid and axis_rx_tready;
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fifo_wr_z <= fifo_wr after 1 ns when rising_edge( clk );
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--fifo_din <= not trn_rx.trn_rbar_hit_n(1) & not trn_rx.trn_rbar_hit_n(0) &
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-- trn_rx.trn_rerrfwd_n & trn_rx.trn_rrem_n(0) & trn_rx.trn_reof_n & trn_rx.trn_rsof_n &
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-- trn_rx.trn_rd after 1 ns when rising_edge( clk );
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fifo_din <= trn_rx.m_axis_rx_tuser(3) & trn_rx.m_axis_rx_tuser(2) &
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'0' & trn_rx.m_axis_rx_tstrb(0) & not trn_rx.m_axis_rx_tlast & '0' &
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trn_rx.m_axis_rx_tdata( 31 downto 0 ) & trn_rx.m_axis_rx_tdata( 63 downto 32 ) after 1 ns when rising_edge( clk );
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pr_rx_first: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( rstpz='1' or (fifo_wr='1' and trn_rx.m_axis_rx_tlast='1' ) ) then
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rx_first <= '1' after 1 ns;
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elsif( fifo_wr='1' and trn_rx.m_axis_rx_tlast='0' ) then
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rx_first <= '0' after 1 ns;
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end if;
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end if;
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end process;
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pr_fifo0_wr: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( rstpz='1' or (fifo_wr='1' and trn_rx.m_axis_rx_tlast='1' ) ) then
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fifo0_wr_en <= '0' after 1 ns;
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elsif( fifo_wr='1' and trn_rx.m_axis_rx_tdata(31)='0' and trn_rx.m_axis_rx_tdata(29 downto 25)="00000" and rx_first='1' ) then
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fifo0_wr_en <= '1' after 1 ns;
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end if;
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end if;
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end process;
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fifo0_wr_en_z <= fifo0_wr_en after 1 ns when rising_edge( clk );
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fifo0_wr <= fifo_wr_z and (fifo0_wr_en or fifo0_wr_en_z);
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fifo0_reg: ctrl_fifo64x70st
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port map(
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clk => clk,
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rst => rstpz,
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din => fifo_din,
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wr_en => fifo0_wr,
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rd_en => fifo0_rd,
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dout => fifo0_dout,
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full => fifo0_full,
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empty => fifo0_empty,
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valid => fifo0_valid,
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prog_full => fifo0_paf,
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prog_empty => fifo0_pae
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);
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pr_fifo1_wr: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( rstpz='1' or (fifo_wr='1' and trn_rx.m_axis_rx_tlast='1' ) ) then
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fifo1_wr_en <= '0' after 1 ns;
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elsif( fifo_wr='1' and trn_rx.m_axis_rx_tdata(31 downto 25)="0100101" and rx_first='1' ) then
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fifo1_wr_en <= '1' after 1 ns;
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end if;
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end if;
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end process;
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fifo1_wr_en_z <= fifo1_wr_en after 1 ns when rising_edge( clk );
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fifo1_wr <= fifo_wr_z and (fifo1_wr_en or fifo1_wr_en_z);
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fifo1_cmpl: ctrl_fifo64x70st
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port map(
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clk => clk,
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rst => rstpz,
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din => fifo_din,
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wr_en => fifo1_wr,
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rd_en => fifo1_rd_x,
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dout => fifo1_dout,
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full => fifo1_full,
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empty => fifo1_empty,
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valid => fifo1_valid,
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prog_full => fifo1_paf,
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prog_empty => fifo1_pae
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);
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fifo1_rd_x <= fifo1_rd and ( not ( data_rx_we_en and not fifo1_dout(65) ) );
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reg_access.adr <= tlp_dw2;
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reg_access.data( 7 downto 0 ) <= tlp_dw3( 31 downto 24 );
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reg_access.data( 15 downto 8 ) <= tlp_dw3( 23 downto 16 );
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reg_access.data( 23 downto 16 ) <= tlp_dw3( 15 downto 8 );
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reg_access.data( 31 downto 24 ) <= tlp_dw3( 7 downto 0 );
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reg_access.req_wr(0) <=request_reg_wr and bar(0);
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reg_access.req_wr(1) <=request_reg_wr and bar(1);
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reg_access.req_rd(0) <=request_reg_rd and ( bar(0) or ( not (bar(0) or bar(1)) ) );
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reg_access.req_rd(1) <=request_reg_rd and bar(1);
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bar(0) <= fifo0_dout(68);
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bar(1) <= fifo0_dout(69);
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rx_tx_engine.request_reg_wr <= request_reg_wr;
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rx_tx_engine.request_reg_rd <= request_reg_rd;
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rx_tx_engine.request_tag <= tlp_dw1( 15 downto 8 );
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rx_tx_engine.request_tc <= tlp_dw0( 22 downto 20 );
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rx_tx_engine.request_attr <= tlp_dw0( 7 downto 4 );
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rx_tx_engine.request_id <= tlp_dw1( 31 downto 16 );
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rx_tx_engine.lower_adr <= tlp_dw2( 6 downto 2 );
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rx_tx_engine.byte_count <= byte_count after 1 ns when rising_edge( clk );
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byte_count <= "000" when request_reg_rd='0' else
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"100" when tlp_dw1( 3 downto 0 )="1111" else
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"010" when tlp_dw1( 3 downto 0 )="0011" or tlp_dw1( 3 downto 0 )="0110" or tlp_dw1( 3 downto 0 )="1100" else
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"001";-- when tlp_dw1( 3 downto 0 )="0001" or tlp_dw1( 3 downto 0 )="0010" or tlp_dw1( 3 downto 0 )="0100" or tlp_dw1( 3 downto 0 )="1000"
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pr_stp: process( clk ) begin
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if( rising_edge( clk ) ) then
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case( stp ) is
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when s0 =>
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if( fifo0_empty='0' ) then
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stp <= s1 after 1 ns;
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end if;
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request_reg_wr <= '0' after 1 ns;
|
320 |
|
|
request_reg_rd <= '0' after 1 ns;
|
321 |
|
|
fifo0_rd <= '0' after 1 ns;
|
322 |
|
|
|
323 |
|
|
when s1 =>
|
324 |
|
|
stp <= s2 after 1 ns;
|
325 |
|
|
fifo0_rd <= '1' after 1 ns;
|
326 |
|
|
|
327 |
|
|
when s2 =>
|
328 |
|
|
stp <= s3 after 1 ns;
|
329 |
|
|
fifo0_rd <= '0' after 1 ns;
|
330 |
|
|
|
331 |
|
|
when s3 =>
|
332 |
|
|
tlp_dw0 <= fifo0_dout( 63 downto 32 ) after 1 ns;
|
333 |
|
|
tlp_dw1 <= fifo0_dout( 31 downto 0 ) after 1 ns;
|
334 |
|
|
if( fifo0_empty='0' ) then
|
335 |
|
|
stp <= s31 after 1 ns;
|
336 |
|
|
end if;
|
337 |
|
|
|
338 |
|
|
when s31 =>
|
339 |
|
|
fifo0_rd <= '1' after 1 ns;
|
340 |
|
|
stp <= s32 after 1 ns;
|
341 |
|
|
|
342 |
|
|
when s32 =>
|
343 |
|
|
fifo0_rd <= '0' after 1 ns;
|
344 |
|
|
stp <= s4 after 1 ns;
|
345 |
|
|
|
346 |
|
|
when s4 =>
|
347 |
|
|
tlp_dw2 <= fifo0_dout( 63 downto 32 ) after 1 ns;
|
348 |
|
|
tlp_dw3 <= fifo0_dout( 31 downto 0 ) after 1 ns;
|
349 |
|
|
|
350 |
|
|
if( tlp_dw0(30)='1' ) then
|
351 |
|
|
request_reg_wr <= '1' after 1 ns;
|
352 |
|
|
else
|
353 |
|
|
request_reg_rd <= '1' after 1 ns;
|
354 |
|
|
end if;
|
355 |
|
|
stp <= s5 after 1 ns;
|
356 |
|
|
|
357 |
|
|
when s5 =>
|
358 |
|
|
if( tx_rx_engine.complete_reg='1' ) then
|
359 |
|
|
stp <= s0 after 1 ns;
|
360 |
|
|
end if;
|
361 |
|
|
|
362 |
|
|
end case;
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
|
366 |
|
|
if( rstpz='1' ) then
|
367 |
|
|
stp <= s0 after 1 ns;
|
368 |
|
|
end if;
|
369 |
|
|
|
370 |
|
|
end if;
|
371 |
|
|
end process;
|
372 |
|
|
|
373 |
|
|
|
374 |
|
|
pr_stf: process( clk ) begin
|
375 |
|
|
|
376 |
|
|
if( rising_edge( clk ) ) then
|
377 |
|
|
|
378 |
|
|
case( stf ) is
|
379 |
|
|
|
380 |
|
|
when s0 =>
|
381 |
|
|
--if( fifo1_empty='0' ) then
|
382 |
|
|
if( fifo1_pae='0' ) then
|
383 |
|
|
stf <= s1 after 1 ns;
|
384 |
|
|
end if;
|
385 |
|
|
fifo1_rd <= '0' after 1 ns;
|
386 |
|
|
data_rx_we_en <= '0' after 1 ns;
|
387 |
|
|
|
388 |
|
|
when s1 =>
|
389 |
|
|
fifo1_rd <= '1' after 1 ns;
|
390 |
|
|
stf <= s2 after 1 ns;
|
391 |
|
|
|
392 |
|
|
when s2 =>
|
393 |
|
|
stf <= s3 after 1 ns;
|
394 |
|
|
|
395 |
|
|
when s3 =>
|
396 |
|
|
tlp_cp_dw0 <= fifo1_dout( 63 downto 32 ) after 1 ns;
|
397 |
|
|
tlp_cp_dw1 <= fifo1_dout( 31 downto 0 ) after 1 ns;
|
398 |
|
|
fifo1_rd <= '0' after 1 ns;
|
399 |
|
|
stf <= s4 after 1 ns;
|
400 |
|
|
|
401 |
|
|
when s4 =>
|
402 |
|
|
tlp_cp_dw2 <= fifo1_dout( 63 downto 32 ) after 1 ns;
|
403 |
|
|
tlp_cp_dw3 <= fifo1_dout( 31 downto 0 ) after 1 ns;
|
404 |
|
|
if( tlp_cp_dw0( 30 )='1' ) then
|
405 |
|
|
stf <= s5 after 1 ns; -- есть данные --
|
406 |
|
|
else
|
407 |
|
|
stf <= s6 after 1 ns; -- нет данных --
|
408 |
|
|
end if;
|
409 |
|
|
|
410 |
|
|
|
411 |
|
|
when s5 =>
|
412 |
|
|
|
413 |
|
|
if( fifo1_dout(65)='0' and fifo1_valid='1' ) then
|
414 |
|
|
stf <= s6 after 1 ns;
|
415 |
|
|
fifo1_rd <= '0' after 1 ns;
|
416 |
|
|
data_rx_we_en <= '0' after 1 ns;
|
417 |
|
|
else
|
418 |
|
|
fifo1_rd <= '1' after 1 ns;
|
419 |
|
|
data_rx_we_en <= '1' after 1 ns;
|
420 |
|
|
end if;
|
421 |
|
|
|
422 |
|
|
when s6 =>
|
423 |
|
|
stf <= s0 after 1 ns;
|
424 |
|
|
|
425 |
|
|
|
426 |
|
|
|
427 |
|
|
end case;
|
428 |
|
|
|
429 |
|
|
if( rstpz='1' ) then
|
430 |
|
|
stf <= s0 after 1 ns;
|
431 |
|
|
end if;
|
432 |
|
|
|
433 |
|
|
end if;
|
434 |
|
|
|
435 |
|
|
|
436 |
|
|
end process;
|
437 |
|
|
|
438 |
|
|
data_rx_we <= fifo1_valid and data_rx_we_en;
|
439 |
|
|
|
440 |
|
|
data_lrx <= fifo1_dout( 31 downto 0 ) after 1 ns when rising_edge( clk ) and fifo1_valid='1';
|
441 |
|
|
data_hrx <= fifo1_dout( 63 downto 32 );
|
442 |
|
|
|
443 |
|
|
data_rx( 32+31 downto 32+24 ) <= data_hrx( 7 downto 0 );
|
444 |
|
|
data_rx( 32+23 downto 32+16 ) <= data_hrx( 15 downto 8 );
|
445 |
|
|
data_rx( 32+15 downto 32+8 ) <= data_hrx( 23 downto 16 );
|
446 |
|
|
data_rx( 32+7 downto 32+0 ) <= data_hrx( 31 downto 24 );
|
447 |
|
|
|
448 |
|
|
|
449 |
|
|
data_rx( 31 downto 24 ) <= data_lrx( 7 downto 0 );
|
450 |
|
|
data_rx( 23 downto 16 ) <= data_lrx( 15 downto 8 );
|
451 |
|
|
data_rx( 15 downto 8 ) <= data_lrx( 23 downto 16 );
|
452 |
|
|
data_rx( 7 downto 0 ) <= data_lrx( 31 downto 24 );
|
453 |
|
|
|
454 |
|
|
pr_adr_cnt: process( clk ) begin
|
455 |
|
|
if( rising_edge( clk ) ) then
|
456 |
|
|
if( stf/=s5 ) then
|
457 |
|
|
adr_cnt <= "0000" after 1 ns;
|
458 |
|
|
elsif( data_rx_we='1' ) then
|
459 |
|
|
adr_cnt( 2 downto 0 ) <= adr_cnt( 2 downto 0 ) + 1 after 1 ns;
|
460 |
|
|
if( adr_cnt( 2 downto 0 )="111" ) then
|
461 |
|
|
adr_cnt( 3 ) <= '1' after 1 ns;
|
462 |
|
|
end if;
|
463 |
|
|
end if;
|
464 |
|
|
end if;
|
465 |
|
|
end process;
|
466 |
|
|
|
467 |
|
|
adr_rx( 2 downto 0 ) <= adr_cnt( 2 downto 0 );
|
468 |
|
|
adr_rx( 3 ) <= tlp_cp_dw2(6) or adr_cnt( 3 );
|
469 |
|
|
adr_rx( 8 downto 4 ) <= tlp_cp_dw2( 12 downto 8 );
|
470 |
|
|
|
471 |
|
|
rx_ext_fifo.adr <= adr_rx after 1 ns when rising_edge( clk );
|
472 |
|
|
rx_ext_fifo.data <= data_rx after 1 ns when rising_edge( clk );
|
473 |
|
|
rx_ext_fifo.data_we <= data_rx_we after 1 ns when rising_edge( clk );
|
474 |
|
|
|
475 |
|
|
rx_tx_engine.complete_we <= data_rx_we after 1 ns when rising_edge( clk );
|
476 |
|
|
|
477 |
|
|
trn_rx_back.m_axis_rx_tready <= axis_rx_tready;
|
478 |
|
|
trn_rx_back.rx_np_ok <= '1';
|
479 |
|
|
|
480 |
|
|
end core64_rx_engine_m2;
|