URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_ctrl/] [core64_rx_engine_m2.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
--
-- Title       : core64_rx_engine_m2
-- Author      : Dmitry Smekhov
-- Company     : Instrumental Systems
-- E-mail      : dsmv@insys.ru
--
-- Version     : 1.1
--
-------------------------------------------------------------------------------
--
-- Description : ���������� �������� ������� 
--                               ����������� 2 - ������������ ��������� AXI 
--
-------------------------------------------------------------------------------
--
--  Version 1.1         19.06.2012
--                                      ��������� ������������ byte_count
--
-------------------------------------------------------------------------------
--
--  Version 1.0         16.08.2011
--                                      ������ �� core64_rx_engine v1.0
--
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.core64_type_pkg.all;
 
package core64_rx_engine_m2_pkg is
 
component core64_rx_engine_m2 is
        port(
 
                --- General ---
                rstp                    : in std_logic;         --! 1 - ����� 
                clk                             : in std_logic;         --! �������� ������� ���� - 250 MHz 
 
                trn_rx                  : in  type_axi_rx;                      --! ���� ������
                trn_rx_back             : out type_axi_rx_back;         --! ���������� � ����� ������
 
                reg_access              : out type_reg_access;          --! ������ �� ������ � ��������� 
 
                rx_tx_engine    : out type_rx_tx_engine;        --! ����� RX->TX 
                tx_rx_engine    : in  type_tx_rx_engine;        --! ����� TX->RX 
 
                rx_ext_fifo             : out type_rx_ext_fifo          --! ����� RX->EXT_FIFO 
 
 
 
        );
end component;
 
end package;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
use work.core64_type_pkg.all;
 
entity core64_rx_engine_m2 is
        port(
 
                --- General ---
                rstp                    : in std_logic;         --! 1 - ����� 
                clk                             : in std_logic;         --! �������� ������� ���� - 250 MHz 
 
                trn_rx                  : in  type_axi_rx;                      --! ���� ������
                trn_rx_back             : out type_axi_rx_back;         --! ���������� � ����� ������
 
                reg_access              : out type_reg_access;          --! ������ �� ������ � ��������� 
 
                rx_tx_engine    : out type_rx_tx_engine;        --! ����� RX->TX 
                tx_rx_engine    : in  type_tx_rx_engine;        --! ����� TX->RX 
 
                rx_ext_fifo             : out type_rx_ext_fifo          --! ����� RX->EXT_FIFO 
 
 
 
        );
end core64_rx_engine_m2;
 
 
architecture core64_rx_engine_m2 of core64_rx_engine_m2 is
 
component ctrl_fifo64x70st is
  port (
    clk                 : in std_logic;
    rst                 : in std_logic;
    din                 : in std_logic_vector(69 downto 0);
    wr_en               : in std_logic;
    rd_en               : in std_logic;
    dout                : out std_logic_vector(69 downto 0);
    full                : out std_logic;
    empty               : out std_logic;
    valid               : out std_logic;
    prog_full   : out std_logic;
    prog_empty  : out std_logic
  );
end component;
 
 
signal  rstpz                   : std_logic;
 
type    stp_type                is ( s0, s1, s2, s3, s31, s32, s4, s5 );
signal  stp                             : stp_type;
 
type    stf_type                is ( s0, s1, s2, s3, s4, s5, s6 );
signal  stf                             : stf_type;
 
signal  trn_rdst_rdy_n                  : std_logic;
signal  trn_rnp_ok_n                    : std_logic;
signal  trn_rcpl_streaming_n    : std_logic;
 
signal  tlp_dw0                                 : std_logic_vector( 31 downto 0 );
signal  tlp_dw1                                 : std_logic_vector( 31 downto 0 );
signal  tlp_dw2                                 : std_logic_vector( 31 downto 0 );
signal  tlp_dw3                                 : std_logic_vector( 31 downto 0 );
 
signal  trn_data                                : std_logic_vector( 63 downto 0 );
signal  trn_data_we                             : std_logic;
 
signal  tlp_cnt                                 : std_logic_vector( 5 downto 0 );
 
signal  request_reg_wr                  : std_logic;
signal  request_reg_rd                  : std_logic;
signal  tlp_complete                    : std_logic;
signal  bar                                             : std_logic_vector( 1 downto 0 );
 
signal  fifo_wr                                 : std_logic;
signal  fifo_wr_z                               : std_logic;
signal  fifo_din                                : std_logic_vector( 69 downto 0 );
 
signal  fifo0_wr                                : std_logic;
signal  fifo0_wr_en                             : std_logic;
signal  fifo0_wr_en_z                   : std_logic;
signal  fifo0_rd                                : std_logic;
signal  fifo0_full                              : std_logic;
signal  fifo0_empty                             : std_logic;
signal  fifo0_valid                             : std_logic;
signal  fifo0_paf                               : std_logic;
signal  fifo0_pae                               : std_logic;
signal  fifo0_dout                              : std_logic_vector( 69 downto 0 );
 
signal  fifo1_wr                                : std_logic;
signal  fifo1_wr_en                             : std_logic;
signal  fifo1_wr_en_z                   : std_logic;
signal  fifo1_rd                                : std_logic;
signal  fifo1_rd_x                              : std_logic;
signal  fifo1_full                              : std_logic;
signal  fifo1_empty                             : std_logic;
signal  fifo1_valid                             : std_logic;
signal  fifo1_paf                               : std_logic;
signal  fifo1_pae                               : std_logic;
signal  fifo1_dout                              : std_logic_vector( 69 downto 0 );
 
signal  data_rx                                 : std_logic_vector( 63 downto 0 );
signal  data_rx_we                              : std_logic;
signal  data_rx_we_en                   : std_logic;
signal  data_lrx                                : std_logic_vector( 31 downto 0 );
signal  data_hrx                                : std_logic_vector( 31 downto 0 );
 
signal  tlp_cp_dw0                              : std_logic_vector( 31 downto 0 );
signal  tlp_cp_dw1                              : std_logic_vector( 31 downto 0 );
signal  tlp_cp_dw2                              : std_logic_vector( 31 downto 0 );
signal  tlp_cp_dw3                              : std_logic_vector( 31 downto 0 );
 
signal  adr_rx                                  : std_logic_vector( 8 downto 0 );
signal  adr_cnt                                 : std_logic_vector( 3 downto 0 );
 
signal  axis_rx_tready                  : std_logic;
signal  rx_first                                : std_logic;
 
signal  byte_count                              : std_logic_vector( 2 downto 0 );
 
 
begin
 
rstpz <= rstp after 1 ns when rising_edge( clk );
 
--trn_rx_back.trn_rdst_rdy_n                      <= trn_rdst_rdy_n;
--trn_rx_back.trn_rnp_ok_n                        <= trn_rnp_ok_n;                      
--trn_rx_back.trn_rcpl_streaming_n      <= trn_rcpl_streaming_n;    
 
trn_rnp_ok_n <= '0';
trn_rcpl_streaming_n <= '0';
 
trn_rdst_rdy_n <= fifo0_paf or fifo1_paf;
 
axis_rx_tready <= not( fifo0_paf or fifo1_paf ) after 1 ns when rising_edge( clk );
 
fifo_wr <= trn_rx.m_axis_rx_tvalid and axis_rx_tready;
fifo_wr_z <= fifo_wr after 1 ns when rising_edge( clk );
 
--fifo_din  <= not trn_rx.trn_rbar_hit_n(1) & not trn_rx.trn_rbar_hit_n(0) & 
--                                trn_rx.trn_rerrfwd_n & trn_rx.trn_rrem_n(0) & trn_rx.trn_reof_n & trn_rx.trn_rsof_n & 
--                                trn_rx.trn_rd after 1 ns when rising_edge( clk );
 
fifo_din  <=  trn_rx.m_axis_rx_tuser(3) & trn_rx.m_axis_rx_tuser(2) &
                                  '0' & trn_rx.m_axis_rx_tstrb(0) & not trn_rx.m_axis_rx_tlast & '0' &
                                  trn_rx.m_axis_rx_tdata( 31 downto 0 ) & trn_rx.m_axis_rx_tdata( 63 downto 32 ) after 1 ns when rising_edge( clk );
 
pr_rx_first: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( rstpz='1' or (fifo_wr='1' and trn_rx.m_axis_rx_tlast='1' ) ) then
                        rx_first <= '1' after 1 ns;
                elsif( fifo_wr='1' and trn_rx.m_axis_rx_tlast='0' ) then
                        rx_first <= '0' after 1 ns;
                end if;
        end if;
end process;
 
pr_fifo0_wr: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( rstpz='1' or (fifo_wr='1' and trn_rx.m_axis_rx_tlast='1' ) ) then
                        fifo0_wr_en <= '0' after 1 ns;
                elsif( fifo_wr='1' and  trn_rx.m_axis_rx_tdata(31)='0' and trn_rx.m_axis_rx_tdata(29 downto 25)="00000" and rx_first='1' ) then
                        fifo0_wr_en <= '1' after 1 ns;
                end if;
        end if;
end process;
 
fifo0_wr_en_z <= fifo0_wr_en after 1 ns when rising_edge( clk );
 
fifo0_wr <= fifo_wr_z and (fifo0_wr_en or fifo0_wr_en_z);
 
fifo0_reg: ctrl_fifo64x70st
  port map(
    clk                 => clk,
    rst                 => rstpz,
    din                 => fifo_din,
    wr_en               => fifo0_wr,
    rd_en               => fifo0_rd,
    dout                => fifo0_dout,
    full                => fifo0_full,
    empty               => fifo0_empty,
    valid               => fifo0_valid,
    prog_full   => fifo0_paf,
    prog_empty  => fifo0_pae
  );
 
 
pr_fifo1_wr: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( rstpz='1' or (fifo_wr='1' and trn_rx.m_axis_rx_tlast='1' ) ) then
                        fifo1_wr_en <= '0' after 1 ns;
                elsif( fifo_wr='1' and  trn_rx.m_axis_rx_tdata(31 downto 25)="0100101" and rx_first='1' ) then
                        fifo1_wr_en <= '1' after 1 ns;
                end if;
        end if;
end process;
 
fifo1_wr_en_z <= fifo1_wr_en after 1 ns when rising_edge( clk );
 
fifo1_wr <= fifo_wr_z and (fifo1_wr_en or fifo1_wr_en_z);
 
fifo1_cmpl: ctrl_fifo64x70st
  port map(
    clk                 => clk,
    rst                 => rstpz,
    din                 => fifo_din,
    wr_en               => fifo1_wr,
    rd_en               => fifo1_rd_x,
    dout                => fifo1_dout,
    full                => fifo1_full,
    empty               => fifo1_empty,
    valid               => fifo1_valid,
    prog_full   => fifo1_paf,
    prog_empty  => fifo1_pae
  );
 
 
 
fifo1_rd_x <= fifo1_rd and ( not ( data_rx_we_en  and not fifo1_dout(65) ) );
 
reg_access.adr <= tlp_dw2;
 
reg_access.data( 7 downto 0 )   <= tlp_dw3( 31 downto 24 );
reg_access.data( 15 downto 8 )  <= tlp_dw3( 23 downto 16 );
reg_access.data( 23 downto 16 ) <= tlp_dw3( 15 downto 8 );
reg_access.data( 31 downto 24 ) <= tlp_dw3( 7 downto 0 );
 
reg_access.req_wr(0) <=request_reg_wr and bar(0);
reg_access.req_wr(1) <=request_reg_wr and bar(1);
reg_access.req_rd(0) <=request_reg_rd and ( bar(0) or ( not (bar(0) or bar(1)) ) );
reg_access.req_rd(1) <=request_reg_rd and bar(1);
 
bar(0) <= fifo0_dout(68);
bar(1) <= fifo0_dout(69);
 
rx_tx_engine.request_reg_wr <= request_reg_wr;
rx_tx_engine.request_reg_rd <= request_reg_rd;
rx_tx_engine.request_tag <= tlp_dw1( 15 downto 8 );
rx_tx_engine.request_tc  <= tlp_dw0( 22 downto 20 );
rx_tx_engine.request_attr <= tlp_dw0( 7 downto 4 );
rx_tx_engine.request_id <= tlp_dw1( 31 downto 16 );
rx_tx_engine.lower_adr <= tlp_dw2( 6 downto 2 );
rx_tx_engine.byte_count <= byte_count after 1 ns when rising_edge( clk );
 
byte_count <= "000" when request_reg_rd='0' else
                          "100" when tlp_dw1( 3 downto 0 )="1111" else
                          "010" when tlp_dw1( 3 downto 0 )="0011" or tlp_dw1( 3 downto 0 )="0110" or tlp_dw1( 3 downto 0 )="1100" else
                          "001";-- when tlp_dw1( 3 downto 0 )="0001" or tlp_dw1( 3 downto 0 )="0010" or tlp_dw1( 3 downto 0 )="0100" or tlp_dw1( 3 downto 0 )="1000" 
 
 
pr_stp: process( clk ) begin
        if( rising_edge( clk ) ) then
 
                case( stp ) is
                        when s0 =>
                                if( fifo0_empty='0' ) then
                                        stp <= s1 after 1 ns;
                                end if;
                                request_reg_wr <= '0' after 1 ns;
                                request_reg_rd <= '0' after 1 ns;
                                fifo0_rd <= '0' after 1 ns;
 
                        when s1 =>
                                        stp <= s2 after 1 ns;
                                        fifo0_rd <= '1' after 1 ns;
 
                        when s2 =>
                                        stp <= s3 after 1 ns;
                                        fifo0_rd <= '0' after 1 ns;
 
                        when s3 =>
                                        tlp_dw0 <= fifo0_dout( 63 downto 32 ) after 1 ns;
                                        tlp_dw1 <= fifo0_dout( 31 downto 0 ) after 1 ns;
                                        if( fifo0_empty='0' ) then
                                                stp <= s31 after 1 ns;
                                        end if;
 
                        when s31 =>
                                        fifo0_rd <= '1' after 1 ns;
                                        stp <= s32 after 1 ns;
 
                        when s32 =>
                                        fifo0_rd <= '0' after 1 ns;
                                        stp <= s4 after 1 ns;
 
                        when s4 =>
                                        tlp_dw2 <= fifo0_dout( 63 downto 32 ) after 1 ns;
                                        tlp_dw3 <= fifo0_dout( 31 downto 0 ) after 1 ns;
 
                                        if( tlp_dw0(30)='1' ) then
                                                request_reg_wr <= '1' after 1 ns;
                                        else
                                                request_reg_rd <= '1' after 1 ns;
                                        end if;
                                        stp <= s5 after 1 ns;
 
                        when s5 =>
                                        if( tx_rx_engine.complete_reg='1' ) then
                                                stp <= s0 after 1 ns;
                                        end if;
 
                end case;
 
 
 
                if( rstpz='1' ) then
                        stp <= s0 after 1 ns;
                end if;
 
        end if;
end process;
 
 
pr_stf: process( clk ) begin
 
        if( rising_edge( clk ) ) then
 
                case( stf ) is
 
                        when s0 =>
                        --if( fifo1_empty='0' ) then
                                if( fifo1_pae='0' ) then
                                        stf <= s1 after 1 ns;
                                end if;
                                fifo1_rd <= '0' after 1 ns;
                                data_rx_we_en   <= '0' after 1 ns;
 
                        when s1 =>
                                fifo1_rd <= '1' after 1 ns;
                                stf <= s2 after 1 ns;
 
                        when s2 =>
                                stf <= s3 after 1 ns;
 
                        when s3 =>
                                        tlp_cp_dw0   <= fifo1_dout( 63 downto 32 ) after 1 ns;
                                        tlp_cp_dw1 <= fifo1_dout( 31 downto 0 ) after 1 ns;
                                        fifo1_rd <= '0' after 1 ns;
                                        stf <= s4 after 1 ns;
 
                        when s4 =>
                                        tlp_cp_dw2 <= fifo1_dout( 63 downto 32 ) after 1 ns;
                                        tlp_cp_dw3 <= fifo1_dout( 31 downto 0 ) after 1 ns;
                                        if( tlp_cp_dw0( 30 )='1' ) then
                                                stf <= s5 after 1 ns;   -- ���� ������ --
                                        else
                                                stf <= s6 after 1 ns;   -- ��� ������ --
                                        end if;
 
 
                        when s5 =>
 
                                        if( fifo1_dout(65)='0' and fifo1_valid='1' ) then
                                                stf <= s6 after 1 ns;
                                                fifo1_rd <= '0' after 1 ns;
                                                data_rx_we_en   <= '0' after 1 ns;
                                        else
                                                fifo1_rd <= '1' after 1 ns;
                                                data_rx_we_en   <= '1' after 1 ns;
                                        end if;
 
                        when s6 =>
                                        stf <= s0 after 1 ns;
 
 
 
                end case;
 
                if( rstpz='1' ) then
                        stf <= s0 after 1 ns;
                end if;
 
        end if;
 
 
end process;
 
data_rx_we <= fifo1_valid and data_rx_we_en;
 
data_lrx <= fifo1_dout( 31 downto 0 ) after 1 ns when rising_edge( clk ) and fifo1_valid='1';
data_hrx <= fifo1_dout( 63 downto 32 );
 
data_rx( 32+31 downto 32+24 )  <= data_hrx( 7 downto 0 );
data_rx( 32+23 downto 32+16 )  <= data_hrx( 15 downto 8 );
data_rx( 32+15 downto 32+8 )   <= data_hrx( 23 downto 16 );
data_rx( 32+7 downto 32+0 )    <= data_hrx( 31 downto 24 );
 
 
data_rx( 31 downto 24 )  <= data_lrx( 7 downto 0 );
data_rx( 23 downto 16 )  <= data_lrx( 15 downto 8 );
data_rx( 15 downto 8 )   <= data_lrx( 23 downto 16 );
data_rx( 7 downto 0 )    <= data_lrx( 31 downto 24 );
 
pr_adr_cnt: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( stf/=s5 ) then
                        adr_cnt <= "0000" after 1 ns;
                elsif( data_rx_we='1' ) then
                        adr_cnt( 2 downto 0 ) <= adr_cnt( 2 downto 0 ) + 1 after 1 ns;
                        if( adr_cnt( 2 downto 0 )="111" ) then
                                adr_cnt( 3 ) <= '1' after 1 ns;
                        end if;
                end if;
        end if;
end process;
 
adr_rx( 2 downto 0 ) <= adr_cnt( 2 downto 0 );
adr_rx( 3 ) <=  tlp_cp_dw2(6) or adr_cnt( 3 );
adr_rx( 8 downto 4 ) <= tlp_cp_dw2( 12 downto 8 );
 
rx_ext_fifo.adr <= adr_rx after 1 ns when rising_edge( clk );
rx_ext_fifo.data <= data_rx after 1 ns when rising_edge( clk );
rx_ext_fifo.data_we <= data_rx_we after 1 ns when rising_edge( clk );
 
rx_tx_engine.complete_we <= data_rx_we after 1 ns when rising_edge( clk );
 
trn_rx_back.m_axis_rx_tready     <= axis_rx_tready;
trn_rx_back.rx_np_ok             <= '1';
 
end core64_rx_engine_m2;

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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_ctrl/] [core64_rx_engine_m2.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dsmv	`-------------------------------------------------------------------------------`
2			`--`
3			`-- Title : core64_rx_engine_m2`
4			`-- Author : Dmitry Smekhov`
5			`-- Company : Instrumental Systems`
6			`-- E-mail : dsmv@insys.ru`
7			`--`
8			`-- Version : 1.1`
9			`--`
10			`-------------------------------------------------------------------------------`
11			`--`
12			`-- Description : �� `
13			`-- �� 2 - �� AXI`
14			`--`
15			`-------------------------------------------------------------------------------`
16			`--`
17			`-- Version 1.1 19.06.2012`
18			`-- �� byte_count`
19			`--`
20			`-------------------------------------------------------------------------------`
21			`--`
22			`-- Version 1.0 16.08.2011`
23			`-- �� core64_rx_engine v1.0`
24			`--`
25			`-------------------------------------------------------------------------------`
26
27
28			`library ieee;`
29			`use ieee.std_logic_1164.all;`
30
31			`use work.core64_type_pkg.all;`
32
33			`package core64_rx_engine_m2_pkg is`
34
35			`component core64_rx_engine_m2 is`
36			`port(`
37
38			`--- General ---`
39			`rstp : in std_logic; --! 1 - ��`
40			`clk : in std_logic; --! �� - 250 MHz`
41
42			`trn_rx : in type_axi_rx; --! �� `
43			`trn_rx_back : out type_axi_rx_back; --! �� `
44
45			`reg_access : out type_reg_access; --! �� `
46
47			`rx_tx_engine : out type_rx_tx_engine; --! �� RX->TX`
48			`tx_rx_engine : in type_tx_rx_engine; --! �� TX->RX`
49
50			`rx_ext_fifo : out type_rx_ext_fifo --! �� RX->EXT_FIFO`
51
52
53
54			`);`
55			`end component;`
56
57			`end package;`
58
59			`library ieee;`
60			`use ieee.std_logic_1164.all;`
61			`use ieee.std_logic_arith.all;`
62			`use ieee.std_logic_unsigned.all;`
63
64			`use work.core64_type_pkg.all;`
65
66			`entity core64_rx_engine_m2 is`
67			`port(`
68
69			`--- General ---`
70			`rstp : in std_logic; --! 1 - ��`
71			`clk : in std_logic; --! �� - 250 MHz`
72
73			`trn_rx : in type_axi_rx; --! �� `
74			`trn_rx_back : out type_axi_rx_back; --! �� `
75
76			`reg_access : out type_reg_access; --! �� `
77
78			`rx_tx_engine : out type_rx_tx_engine; --! �� RX->TX`
79			`tx_rx_engine : in type_tx_rx_engine; --! �� TX->RX`
80
81			`rx_ext_fifo : out type_rx_ext_fifo --! �� RX->EXT_FIFO`
82
83
84
85			`);`
86			`end core64_rx_engine_m2;`
87
88
89			`architecture core64_rx_engine_m2 of core64_rx_engine_m2 is`
90
91			`component ctrl_fifo64x70st is`
92			`port (`
93			`clk : in std_logic;`
94			`rst : in std_logic;`
95			`din : in std_logic_vector(69 downto 0);`
96			`wr_en : in std_logic;`
97			`rd_en : in std_logic;`
98			`dout : out std_logic_vector(69 downto 0);`
99			`full : out std_logic;`
100			`empty : out std_logic;`
101			`valid : out std_logic;`
102			`prog_full : out std_logic;`
103			`prog_empty : out std_logic`
104			`);`
105			`end component;`
106
107
108			`signal rstpz : std_logic;`
109
110			`type stp_type is ( s0, s1, s2, s3, s31, s32, s4, s5 );`
111			`signal stp : stp_type;`
112
113			`type stf_type is ( s0, s1, s2, s3, s4, s5, s6 );`
114			`signal stf : stf_type;`
115
116			`signal trn_rdst_rdy_n : std_logic;`
117			`signal trn_rnp_ok_n : std_logic;`
118			`signal trn_rcpl_streaming_n : std_logic;`
119
120			`signal tlp_dw0 : std_logic_vector( 31 downto 0 );`
121			`signal tlp_dw1 : std_logic_vector( 31 downto 0 );`
122			`signal tlp_dw2 : std_logic_vector( 31 downto 0 );`
123			`signal tlp_dw3 : std_logic_vector( 31 downto 0 );`
124
125			`signal trn_data : std_logic_vector( 63 downto 0 );`
126			`signal trn_data_we : std_logic;`
127
128			`signal tlp_cnt : std_logic_vector( 5 downto 0 );`
129
130			`signal request_reg_wr : std_logic;`
131			`signal request_reg_rd : std_logic;`
132			`signal tlp_complete : std_logic;`
133			`signal bar : std_logic_vector( 1 downto 0 );`
134
135			`signal fifo_wr : std_logic;`
136			`signal fifo_wr_z : std_logic;`
137			`signal fifo_din : std_logic_vector( 69 downto 0 );`
138
139			`signal fifo0_wr : std_logic;`
140			`signal fifo0_wr_en : std_logic;`
141			`signal fifo0_wr_en_z : std_logic;`
142			`signal fifo0_rd : std_logic;`
143			`signal fifo0_full : std_logic;`
144			`signal fifo0_empty : std_logic;`
145			`signal fifo0_valid : std_logic;`
146			`signal fifo0_paf : std_logic;`
147			`signal fifo0_pae : std_logic;`
148			`signal fifo0_dout : std_logic_vector( 69 downto 0 );`
149
150			`signal fifo1_wr : std_logic;`
151			`signal fifo1_wr_en : std_logic;`
152			`signal fifo1_wr_en_z : std_logic;`
153			`signal fifo1_rd : std_logic;`
154			`signal fifo1_rd_x : std_logic;`
155			`signal fifo1_full : std_logic;`
156			`signal fifo1_empty : std_logic;`
157			`signal fifo1_valid : std_logic;`
158			`signal fifo1_paf : std_logic;`
159			`signal fifo1_pae : std_logic;`
160			`signal fifo1_dout : std_logic_vector( 69 downto 0 );`
161
162			`signal data_rx : std_logic_vector( 63 downto 0 );`
163			`signal data_rx_we : std_logic;`
164			`signal data_rx_we_en : std_logic;`
165			`signal data_lrx : std_logic_vector( 31 downto 0 );`
166			`signal data_hrx : std_logic_vector( 31 downto 0 );`
167
168			`signal tlp_cp_dw0 : std_logic_vector( 31 downto 0 );`
169			`signal tlp_cp_dw1 : std_logic_vector( 31 downto 0 );`
170			`signal tlp_cp_dw2 : std_logic_vector( 31 downto 0 );`
171			`signal tlp_cp_dw3 : std_logic_vector( 31 downto 0 );`
172
173			`signal adr_rx : std_logic_vector( 8 downto 0 );`
174			`signal adr_cnt : std_logic_vector( 3 downto 0 );`
175
176			`signal axis_rx_tready : std_logic;`
177			`signal rx_first : std_logic;`
178
179			`signal byte_count : std_logic_vector( 2 downto 0 );`
180
181
182			`begin`
183
184			`rstpz <= rstp after 1 ns when rising_edge( clk );`
185
186			`--trn_rx_back.trn_rdst_rdy_n <= trn_rdst_rdy_n;`
187			`--trn_rx_back.trn_rnp_ok_n <= trn_rnp_ok_n;`
188			`--trn_rx_back.trn_rcpl_streaming_n <= trn_rcpl_streaming_n;`
189
190			`trn_rnp_ok_n <= '0';`
191			`trn_rcpl_streaming_n <= '0';`
192
193			`trn_rdst_rdy_n <= fifo0_paf or fifo1_paf;`
194
195			`axis_rx_tready <= not( fifo0_paf or fifo1_paf ) after 1 ns when rising_edge( clk );`
196
197			`fifo_wr <= trn_rx.m_axis_rx_tvalid and axis_rx_tready;`
198			`fifo_wr_z <= fifo_wr after 1 ns when rising_edge( clk );`
199
200			`--fifo_din <= not trn_rx.trn_rbar_hit_n(1) & not trn_rx.trn_rbar_hit_n(0) &`
201			`-- trn_rx.trn_rerrfwd_n & trn_rx.trn_rrem_n(0) & trn_rx.trn_reof_n & trn_rx.trn_rsof_n &`
202			`-- trn_rx.trn_rd after 1 ns when rising_edge( clk );`
203
204			`fifo_din <= trn_rx.m_axis_rx_tuser(3) & trn_rx.m_axis_rx_tuser(2) &`
205			`'0' & trn_rx.m_axis_rx_tstrb(0) & not trn_rx.m_axis_rx_tlast & '0' &`
206			`trn_rx.m_axis_rx_tdata( 31 downto 0 ) & trn_rx.m_axis_rx_tdata( 63 downto 32 ) after 1 ns when rising_edge( clk );`
207
208			`pr_rx_first: process( clk ) begin`
209			`if( rising_edge( clk ) ) then`
210			`if( rstpz='1' or (fifo_wr='1' and trn_rx.m_axis_rx_tlast='1' ) ) then`
211			`rx_first <= '1' after 1 ns;`
212			`elsif( fifo_wr='1' and trn_rx.m_axis_rx_tlast='0' ) then`
213			`rx_first <= '0' after 1 ns;`
214			`end if;`
215			`end if;`
216			`end process;`
217
218			`pr_fifo0_wr: process( clk ) begin`
219			`if( rising_edge( clk ) ) then`
220			`if( rstpz='1' or (fifo_wr='1' and trn_rx.m_axis_rx_tlast='1' ) ) then`
221			`fifo0_wr_en <= '0' after 1 ns;`
222			`elsif( fifo_wr='1' and trn_rx.m_axis_rx_tdata(31)='0' and trn_rx.m_axis_rx_tdata(29 downto 25)="00000" and rx_first='1' ) then`
223			`fifo0_wr_en <= '1' after 1 ns;`
224			`end if;`
225			`end if;`
226			`end process;`
227
228			`fifo0_wr_en_z <= fifo0_wr_en after 1 ns when rising_edge( clk );`
229
230			`fifo0_wr <= fifo_wr_z and (fifo0_wr_en or fifo0_wr_en_z);`
231
232			`fifo0_reg: ctrl_fifo64x70st`
233			`port map(`
234			`clk => clk,`
235			`rst => rstpz,`
236			`din => fifo_din,`
237			`wr_en => fifo0_wr,`
238			`rd_en => fifo0_rd,`
239			`dout => fifo0_dout,`
240			`full => fifo0_full,`
241			`empty => fifo0_empty,`
242			`valid => fifo0_valid,`
243			`prog_full => fifo0_paf,`
244			`prog_empty => fifo0_pae`
245			`);`
246
247
248			`pr_fifo1_wr: process( clk ) begin`
249			`if( rising_edge( clk ) ) then`
250			`if( rstpz='1' or (fifo_wr='1' and trn_rx.m_axis_rx_tlast='1' ) ) then`
251			`fifo1_wr_en <= '0' after 1 ns;`
252			`elsif( fifo_wr='1' and trn_rx.m_axis_rx_tdata(31 downto 25)="0100101" and rx_first='1' ) then`
253			`fifo1_wr_en <= '1' after 1 ns;`
254			`end if;`
255			`end if;`
256			`end process;`
257
258			`fifo1_wr_en_z <= fifo1_wr_en after 1 ns when rising_edge( clk );`
259
260			`fifo1_wr <= fifo_wr_z and (fifo1_wr_en or fifo1_wr_en_z);`
261
262			`fifo1_cmpl: ctrl_fifo64x70st`
263			`port map(`
264			`clk => clk,`
265			`rst => rstpz,`
266			`din => fifo_din,`
267			`wr_en => fifo1_wr,`
268			`rd_en => fifo1_rd_x,`
269			`dout => fifo1_dout,`
270			`full => fifo1_full,`
271			`empty => fifo1_empty,`
272			`valid => fifo1_valid,`
273			`prog_full => fifo1_paf,`
274			`prog_empty => fifo1_pae`
275			`);`
276
277
278
279			`fifo1_rd_x <= fifo1_rd and ( not ( data_rx_we_en and not fifo1_dout(65) ) );`
280
281			`reg_access.adr <= tlp_dw2;`
282
283			`reg_access.data( 7 downto 0 ) <= tlp_dw3( 31 downto 24 );`
284			`reg_access.data( 15 downto 8 ) <= tlp_dw3( 23 downto 16 );`
285			`reg_access.data( 23 downto 16 ) <= tlp_dw3( 15 downto 8 );`
286			`reg_access.data( 31 downto 24 ) <= tlp_dw3( 7 downto 0 );`
287
288			`reg_access.req_wr(0) <=request_reg_wr and bar(0);`
289			`reg_access.req_wr(1) <=request_reg_wr and bar(1);`
290			`reg_access.req_rd(0) <=request_reg_rd and ( bar(0) or ( not (bar(0) or bar(1)) ) );`
291			`reg_access.req_rd(1) <=request_reg_rd and bar(1);`
292
293			`bar(0) <= fifo0_dout(68);`
294			`bar(1) <= fifo0_dout(69);`
295
296			`rx_tx_engine.request_reg_wr <= request_reg_wr;`
297			`rx_tx_engine.request_reg_rd <= request_reg_rd;`
298			`rx_tx_engine.request_tag <= tlp_dw1( 15 downto 8 );`
299			`rx_tx_engine.request_tc <= tlp_dw0( 22 downto 20 );`
300			`rx_tx_engine.request_attr <= tlp_dw0( 7 downto 4 );`
301			`rx_tx_engine.request_id <= tlp_dw1( 31 downto 16 );`
302			`rx_tx_engine.lower_adr <= tlp_dw2( 6 downto 2 );`
303			`rx_tx_engine.byte_count <= byte_count after 1 ns when rising_edge( clk );`
304
305			`byte_count <= "000" when request_reg_rd='0' else`
306			`"100" when tlp_dw1( 3 downto 0 )="1111" else`
307			`"010" when tlp_dw1( 3 downto 0 )="0011" or tlp_dw1( 3 downto 0 )="0110" or tlp_dw1( 3 downto 0 )="1100" else`
308			`"001";-- when tlp_dw1( 3 downto 0 )="0001" or tlp_dw1( 3 downto 0 )="0010" or tlp_dw1( 3 downto 0 )="0100" or tlp_dw1( 3 downto 0 )="1000"`
309
310
311			`pr_stp: process( clk ) begin`
312			`if( rising_edge( clk ) ) then`
313
314			`case( stp ) is`
315			`when s0 =>`
316			`if( fifo0_empty='0' ) then`
317			`stp <= s1 after 1 ns;`
318			`end if;`
319			`request_reg_wr <= '0' after 1 ns;`
320			`request_reg_rd <= '0' after 1 ns;`
321			`fifo0_rd <= '0' after 1 ns;`
322
323			`when s1 =>`
324			`stp <= s2 after 1 ns;`
325			`fifo0_rd <= '1' after 1 ns;`
326
327			`when s2 =>`
328			`stp <= s3 after 1 ns;`
329			`fifo0_rd <= '0' after 1 ns;`
330
331			`when s3 =>`
332			`tlp_dw0 <= fifo0_dout( 63 downto 32 ) after 1 ns;`
333			`tlp_dw1 <= fifo0_dout( 31 downto 0 ) after 1 ns;`
334			`if( fifo0_empty='0' ) then`
335			`stp <= s31 after 1 ns;`
336			`end if;`
337
338			`when s31 =>`
339			`fifo0_rd <= '1' after 1 ns;`
340			`stp <= s32 after 1 ns;`
341
342			`when s32 =>`
343			`fifo0_rd <= '0' after 1 ns;`
344			`stp <= s4 after 1 ns;`
345
346			`when s4 =>`
347			`tlp_dw2 <= fifo0_dout( 63 downto 32 ) after 1 ns;`
348			`tlp_dw3 <= fifo0_dout( 31 downto 0 ) after 1 ns;`
349
350			`if( tlp_dw0(30)='1' ) then`
351			`request_reg_wr <= '1' after 1 ns;`
352			`else`
353			`request_reg_rd <= '1' after 1 ns;`
354			`end if;`
355			`stp <= s5 after 1 ns;`
356
357			`when s5 =>`
358			`if( tx_rx_engine.complete_reg='1' ) then`
359			`stp <= s0 after 1 ns;`
360			`end if;`
361
362			`end case;`
363
364
365
366			`if( rstpz='1' ) then`
367			`stp <= s0 after 1 ns;`
368			`end if;`
369
370			`end if;`
371			`end process;`
372
373
374			`pr_stf: process( clk ) begin`
375
376			`if( rising_edge( clk ) ) then`
377
378			`case( stf ) is`
379
380			`when s0 =>`
381			`--if( fifo1_empty='0' ) then`
382			`if( fifo1_pae='0' ) then`
383			`stf <= s1 after 1 ns;`
384			`end if;`
385			`fifo1_rd <= '0' after 1 ns;`
386			`data_rx_we_en <= '0' after 1 ns;`
387
388			`when s1 =>`
389			`fifo1_rd <= '1' after 1 ns;`
390			`stf <= s2 after 1 ns;`
391
392			`when s2 =>`
393			`stf <= s3 after 1 ns;`
394
395			`when s3 =>`
396			`tlp_cp_dw0 <= fifo1_dout( 63 downto 32 ) after 1 ns;`
397			`tlp_cp_dw1 <= fifo1_dout( 31 downto 0 ) after 1 ns;`
398			`fifo1_rd <= '0' after 1 ns;`
399			`stf <= s4 after 1 ns;`
400
401			`when s4 =>`
402			`tlp_cp_dw2 <= fifo1_dout( 63 downto 32 ) after 1 ns;`
403			`tlp_cp_dw3 <= fifo1_dout( 31 downto 0 ) after 1 ns;`
404			`if( tlp_cp_dw0( 30 )='1' ) then`
405			`stf <= s5 after 1 ns; -- �� --`
406			`else`
407			`stf <= s6 after 1 ns; -- �� --`
408			`end if;`
409
410
411			`when s5 =>`
412
413			`if( fifo1_dout(65)='0' and fifo1_valid='1' ) then`
414			`stf <= s6 after 1 ns;`
415			`fifo1_rd <= '0' after 1 ns;`
416			`data_rx_we_en <= '0' after 1 ns;`
417			`else`
418			`fifo1_rd <= '1' after 1 ns;`
419			`data_rx_we_en <= '1' after 1 ns;`
420			`end if;`
421
422			`when s6 =>`
423			`stf <= s0 after 1 ns;`
424
425
426
427			`end case;`
428
429			`if( rstpz='1' ) then`
430			`stf <= s0 after 1 ns;`
431			`end if;`
432
433			`end if;`
434
435
436			`end process;`
437
438			`data_rx_we <= fifo1_valid and data_rx_we_en;`
439
440			`data_lrx <= fifo1_dout( 31 downto 0 ) after 1 ns when rising_edge( clk ) and fifo1_valid='1';`
441			`data_hrx <= fifo1_dout( 63 downto 32 );`
442
443			`data_rx( 32+31 downto 32+24 ) <= data_hrx( 7 downto 0 );`
444			`data_rx( 32+23 downto 32+16 ) <= data_hrx( 15 downto 8 );`
445			`data_rx( 32+15 downto 32+8 ) <= data_hrx( 23 downto 16 );`
446			`data_rx( 32+7 downto 32+0 ) <= data_hrx( 31 downto 24 );`
447
448
449			`data_rx( 31 downto 24 ) <= data_lrx( 7 downto 0 );`
450			`data_rx( 23 downto 16 ) <= data_lrx( 15 downto 8 );`
451			`data_rx( 15 downto 8 ) <= data_lrx( 23 downto 16 );`
452			`data_rx( 7 downto 0 ) <= data_lrx( 31 downto 24 );`
453
454			`pr_adr_cnt: process( clk ) begin`
455			`if( rising_edge( clk ) ) then`
456			`if( stf/=s5 ) then`
457			`adr_cnt <= "0000" after 1 ns;`
458			`elsif( data_rx_we='1' ) then`
459			`adr_cnt( 2 downto 0 ) <= adr_cnt( 2 downto 0 ) + 1 after 1 ns;`
460			`if( adr_cnt( 2 downto 0 )="111" ) then`
461			`adr_cnt( 3 ) <= '1' after 1 ns;`
462			`end if;`
463			`end if;`
464			`end if;`
465			`end process;`
466
467			`adr_rx( 2 downto 0 ) <= adr_cnt( 2 downto 0 );`
468			`adr_rx( 3 ) <= tlp_cp_dw2(6) or adr_cnt( 3 );`
469			`adr_rx( 8 downto 4 ) <= tlp_cp_dw2( 12 downto 8 );`
470
471			`rx_ext_fifo.adr <= adr_rx after 1 ns when rising_edge( clk );`
472			`rx_ext_fifo.data <= data_rx after 1 ns when rising_edge( clk );`
473			`rx_ext_fifo.data_we <= data_rx_we after 1 ns when rising_edge( clk );`
474
475			`rx_tx_engine.complete_we <= data_rx_we after 1 ns when rising_edge( clk );`
476
477			`trn_rx_back.m_axis_rx_tready <= axis_rx_tready;`
478			`trn_rx_back.rx_np_ok <= '1';`
479
480			`end core64_rx_engine_m2;`