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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_ctrl/] [core64_rx_engine_m4.vhd] - Blame information for rev 2

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1 2 dsmv
-------------------------------------------------------------------------------
2
--
3
-- Title       : core64_rx_engine_m4
4
-- Author      : Dmitry Smekhov
5
-- Company     : Instrumental Systems
6
-- E-mail      : dsmv@insys.ru
7
--
8
-- Version     : 1.1
9
--
10
-------------------------------------------------------------------------------
11
--
12
-- Description : Обработчик входящих пакетов 
13
--                               Модификация 4 - Spartan-6 
14
--
15
-------------------------------------------------------------------------------
16
--
17
--  Version 1.1         19.06.2012
18
--                                      Добавлено формирование byte_count
19
--
20
-------------------------------------------------------------------------------
21
 
22
 
23
library ieee;
24
use ieee.std_logic_1164.all;
25
 
26
use work.core64_type_pkg.all;
27
 
28
package core64_rx_engine_m4_pkg is
29
 
30
component core64_rx_engine_m4 is
31
        port(
32
 
33
                --- General ---
34
                rstp                    : in std_logic;         --! 1 - сброс 
35
                clk                             : in std_logic;         --! тактовая частота ядра - 250 MHz 
36
 
37
                trn_rx                  : in  type_trn_rx;                      --! приём пакета
38
                trn_rx_back             : out type_trn_rx_back;         --! готовность к приёму пакета
39
 
40
                reg_access              : out type_reg_access;          --! запрос на доступ к регистрам 
41
 
42
                rx_tx_engine    : out type_rx_tx_engine;        --! обмен RX->TX 
43
                tx_rx_engine    : in  type_tx_rx_engine;        --! обмен TX->RX 
44
 
45
                rx_ext_fifo             : out type_rx_ext_fifo          --! обмен RX->EXT_FIFO 
46
 
47
 
48
 
49
        );
50
end component;
51
 
52
end package;
53
 
54
library ieee;
55
use ieee.std_logic_1164.all;
56
use ieee.std_logic_arith.all;
57
use ieee.std_logic_unsigned.all;
58
 
59
use work.core64_type_pkg.all;
60
 
61
entity core64_rx_engine_m4 is
62
        port(
63
 
64
                --- General ---
65
                rstp                    : in std_logic;         --! 1 - сброс 
66
                clk                             : in std_logic;         --! тактовая частота ядра - 250 MHz 
67
 
68
                trn_rx                  : in  type_trn_rx;                      --! приём пакета
69
                trn_rx_back             : out type_trn_rx_back;         --! готовность к приёму пакета
70
 
71
                reg_access              : out type_reg_access;          --! запрос на доступ к регистрам 
72
 
73
                rx_tx_engine    : out type_rx_tx_engine;        --! обмен RX->TX 
74
                tx_rx_engine    : in  type_tx_rx_engine;        --! обмен TX->RX 
75
 
76
                rx_ext_fifo             : out type_rx_ext_fifo          --! обмен RX->EXT_FIFO 
77
 
78
 
79
 
80
        );
81
end core64_rx_engine_m4;
82
 
83
 
84
architecture core64_rx_engine_m4 of core64_rx_engine_m4 is
85
 
86
 
87
component ctrl_fifo64x37st is
88
  port (
89
    clk : in std_logic;
90
    rst : in std_logic;
91
    din : in std_logic_vector(36 downto 0);
92
    wr_en : in std_logic;
93
    rd_en : in std_logic;
94
    dout : out std_logic_vector(36 downto 0);
95
    full : out std_logic;
96
    empty : out std_logic;
97
    valid : out std_logic;
98
    prog_full : out std_logic;
99
    prog_empty : out std_logic
100
  );
101
end component;
102
 
103
 
104
signal  rstpz                   : std_logic;
105
 
106
type    stp_type                is ( s0, s1, s2, s3, s31, s32, s33, s34, s35, s36, s37, s38, s39, s4, s5 );
107
signal  stp                             : stp_type;
108
 
109
type    stf_type                is ( s0, s1, s2, s3, s31, s4, s5, s6 );
110
signal  stf                             : stf_type;
111
 
112
signal  trn_rdst_rdy_n                  : std_logic;
113
signal  trn_rnp_ok_n                    : std_logic;
114
signal  trn_rcpl_streaming_n    : std_logic;
115
 
116
signal  tlp_dw0                                 : std_logic_vector( 31 downto 0 );
117
signal  tlp_dw1                                 : std_logic_vector( 31 downto 0 );
118
signal  tlp_dw2                                 : std_logic_vector( 31 downto 0 );
119
signal  tlp_dw3                                 : std_logic_vector( 31 downto 0 );
120
 
121
signal  trn_data                                : std_logic_vector( 63 downto 0 );
122
signal  trn_data_we                             : std_logic;
123
 
124
signal  tlp_cnt                                 : std_logic_vector( 5 downto 0 );
125
 
126
signal  request_reg_wr                  : std_logic;
127
signal  request_reg_rd                  : std_logic;
128
signal  tlp_complete                    : std_logic;
129
signal  bar                                             : std_logic_vector( 1 downto 0 );
130
 
131
signal  fifo_wr                                 : std_logic;
132
signal  fifo_wr_z                               : std_logic;
133
signal  fifo_din                                : std_logic_vector( 36 downto 0 );
134
 
135
signal  fifo0_wr                                : std_logic;
136
signal  fifo0_wr_en                             : std_logic;
137
signal  fifo0_wr_en_z                   : std_logic;
138
signal  fifo0_rd                                : std_logic;
139
signal  fifo0_full                              : std_logic;
140
signal  fifo0_empty                             : std_logic;
141
signal  fifo0_valid                             : std_logic;
142
signal  fifo0_paf                               : std_logic;
143
signal  fifo0_pae                               : std_logic;
144
signal  fifo0_dout                              : std_logic_vector( 36 downto 0 );
145
 
146
signal  fifo1_wr                                : std_logic;
147
signal  fifo1_wr_en                             : std_logic;
148
signal  fifo1_wr_en_z                   : std_logic;
149
signal  fifo1_rd                                : std_logic;
150
signal  fifo1_rd_x                              : std_logic;
151
signal  fifo1_full                              : std_logic;
152
signal  fifo1_empty                             : std_logic;
153
signal  fifo1_valid                             : std_logic;
154
signal  fifo1_paf                               : std_logic;
155
signal  fifo1_pae                               : std_logic;
156
signal  fifo1_dout                              : std_logic_vector( 36 downto 0 );
157
 
158
signal  data_rx                                 : std_logic_vector( 63 downto 0 );
159
signal  data_rx_we                              : std_logic;
160
signal  data_rx_we_en                   : std_logic;
161
signal  data_lrx                                : std_logic_vector( 31 downto 0 );
162
signal  data_hrx                                : std_logic_vector( 31 downto 0 );
163
 
164
signal  tlp_cp_dw0                              : std_logic_vector( 31 downto 0 );
165
signal  tlp_cp_dw1                              : std_logic_vector( 31 downto 0 );
166
signal  tlp_cp_dw2                              : std_logic_vector( 31 downto 0 );
167
signal  tlp_cp_dw3                              : std_logic_vector( 31 downto 0 );
168
 
169
signal  adr_rx                                  : std_logic_vector( 8 downto 0 );
170
signal  adr_cnt                                 : std_logic_vector( 3 downto 0 );
171
 
172
signal  flag_rx_we                              : std_logic;
173
 
174
signal  byte_count                              : std_logic_vector( 2 downto 0 );
175
 
176
begin
177
 
178
rstpz <= rstp after 1 ns when rising_edge( clk );
179
 
180
trn_rx_back.trn_rdst_rdy_n                        <= trn_rdst_rdy_n;
181
trn_rx_back.trn_rnp_ok_n                          <= trn_rnp_ok_n;
182
trn_rx_back.trn_rcpl_streaming_n      <= trn_rcpl_streaming_n;
183
 
184
trn_rnp_ok_n <= '0';
185
trn_rcpl_streaming_n <= '0';
186
 
187
trn_rdst_rdy_n <= fifo0_paf or fifo1_paf;
188
 
189
fifo_wr <= not ( trn_rx.trn_rsrc_rdy_n or trn_rdst_rdy_n );
190
fifo_wr_z <= fifo_wr after 1 ns when rising_edge( clk );
191
 
192
fifo_din  <= not trn_rx.trn_rbar_hit_n(1) & not trn_rx.trn_rbar_hit_n(0) &
193
                                  trn_rx.trn_rerrfwd_n & trn_rx.trn_reof_n & trn_rx.trn_rsof_n &
194
                                  trn_rx.trn_rd( 31 downto 0 ) after 1 ns when rising_edge( clk );
195
 
196
pr_fifo0_wr: process( clk ) begin
197
        if( rising_edge( clk ) ) then
198
                if( rstpz='1' or (fifo_wr='1' and trn_rx.trn_reof_n='0' ) ) then
199
                        fifo0_wr_en <= '0' after 1 ns;
200
                elsif( fifo_wr='1' and  trn_rx.trn_rd(31)='0' and trn_rx.trn_rd(29 downto 25)="00000" and trn_rx.trn_rsof_n='0' ) then
201
                        fifo0_wr_en <= '1' after 1 ns;
202
                end if;
203
        end if;
204
end process;
205
 
206
fifo0_wr_en_z <= fifo0_wr_en after 1 ns when rising_edge( clk );
207
 
208
fifo0_wr <= fifo_wr_z and (fifo0_wr_en or fifo0_wr_en_z);
209
 
210
fifo0_reg: ctrl_fifo64x37st
211
  port map(
212
    clk                 => clk,
213
    rst                 => rstpz,
214
    din                 => fifo_din,
215
    wr_en               => fifo0_wr,
216
    rd_en               => fifo0_rd,
217
    dout                => fifo0_dout,
218
    full                => fifo0_full,
219
    empty               => fifo0_empty,
220
    valid               => fifo0_valid,
221
    prog_full   => fifo0_paf,
222
    prog_empty  => fifo0_pae
223
  );
224
 
225
 
226
pr_fifo1_wr: process( clk ) begin
227
        if( rising_edge( clk ) ) then
228
                if( rstpz='1' or (fifo_wr='1' and trn_rx.trn_reof_n='0' ) ) then
229
                        fifo1_wr_en <= '0' after 1 ns;
230
                elsif( fifo_wr='1' and  trn_rx.trn_rd(31 downto 25)="0100101" and trn_rx.trn_rsof_n='0' ) then
231
                        fifo1_wr_en <= '1' after 1 ns;
232
                end if;
233
        end if;
234
end process;
235
 
236
fifo1_wr_en_z <= fifo1_wr_en after 1 ns when rising_edge( clk );
237
 
238
fifo1_wr <= fifo_wr_z and (fifo1_wr_en or fifo1_wr_en_z);
239
 
240
fifo1_cmpl: ctrl_fifo64x37st
241
  port map(
242
    clk                 => clk,
243
    rst                 => rstpz,
244
    din                 => fifo_din,
245
    wr_en               => fifo1_wr,
246
    rd_en               => fifo1_rd_x,
247
    dout                => fifo1_dout,
248
    full                => fifo1_full,
249
    empty               => fifo1_empty,
250
    valid               => fifo1_valid,
251
    prog_full   => fifo1_paf,
252
    prog_empty  => fifo1_pae
253
  );
254
 
255
 
256
 
257
fifo1_rd_x <= fifo1_rd and ( not ( data_rx_we_en  and not fifo1_dout(33) ) );
258
 
259
reg_access.adr <= tlp_dw2;
260
 
261
reg_access.data( 7 downto 0 )   <= tlp_dw3( 31 downto 24 );
262
reg_access.data( 15 downto 8 )  <= tlp_dw3( 23 downto 16 );
263
reg_access.data( 23 downto 16 ) <= tlp_dw3( 15 downto 8 );
264
reg_access.data( 31 downto 24 ) <= tlp_dw3( 7 downto 0 );
265
 
266
reg_access.req_wr(0) <=request_reg_wr and bar(0);
267
reg_access.req_wr(1) <=request_reg_wr and bar(1);
268
reg_access.req_rd(0) <=request_reg_rd and ( bar(0) or ( not (bar(0) or bar(1)) ) );
269
reg_access.req_rd(1) <=request_reg_rd and bar(1);
270
 
271
bar(0) <= fifo0_dout(35);
272
bar(1) <= fifo0_dout(36);
273
 
274
rx_tx_engine.request_reg_wr <= request_reg_wr;
275
rx_tx_engine.request_reg_rd <= request_reg_rd;
276
rx_tx_engine.request_tag <= tlp_dw1( 15 downto 8 );
277
rx_tx_engine.request_tc  <= tlp_dw0( 22 downto 20 );
278
rx_tx_engine.request_attr <= tlp_dw0( 7 downto 4 );
279
rx_tx_engine.request_id <= tlp_dw1( 31 downto 16 );
280
rx_tx_engine.lower_adr <= tlp_dw2( 6 downto 2 );
281
 
282
rx_tx_engine.byte_count <= byte_count after 1 ns when rising_edge( clk );
283
 
284
byte_count <= "000" when request_reg_rd='0' else
285
                          "100" when tlp_dw1( 3 downto 0 )="1111" else
286
                          "010" when tlp_dw1( 3 downto 0 )="0011" or tlp_dw1( 3 downto 0 )="0110" or tlp_dw1( 3 downto 0 )="1100" else
287
                          "001";-- when tlp_dw1( 3 downto 0 )="0001" or tlp_dw1( 3 downto 0 )="0010" or tlp_dw1( 3 downto 0 )="0100" or tlp_dw1( 3 downto 0 )="1000" 
288
 
289
 
290
 
291
pr_stp: process( clk ) begin
292
        if( rising_edge( clk ) ) then
293
 
294
                case( stp ) is
295
                        when s0 =>
296
                                if( fifo0_empty='0' ) then
297
                                        stp <= s1 after 1 ns;
298
                                end if;
299
                                request_reg_wr <= '0' after 1 ns;
300
                                request_reg_rd <= '0' after 1 ns;
301
                                fifo0_rd <= '0' after 1 ns;
302
 
303
                        when s1 =>
304
                                        stp <= s2 after 1 ns;
305
                                        fifo0_rd <= '1' after 1 ns;
306
 
307
                        when s2 =>
308
                                        stp <= s3 after 1 ns;
309
                                        fifo0_rd <= '0' after 1 ns;
310
 
311
                        when s3 =>
312
                                        tlp_dw0 <= fifo0_dout( 31 downto 0 ) after 1 ns;
313
                                        if( fifo0_empty='0' ) then
314
                                                stp <= s31 after 1 ns;
315
                                        end if;
316
 
317
                        when s31 =>
318
                                        fifo0_rd <= '1' after 1 ns;
319
                                        stp <= s32 after 1 ns;
320
 
321
                        when s32 =>
322
                                        fifo0_rd <= '0' after 1 ns;
323
                                        stp <= s33 after 1 ns;
324
 
325
 
326
                        when s33 =>
327
                                        tlp_dw1 <= fifo0_dout( 31 downto 0 ) after 1 ns;
328
                                        if( fifo0_empty='0' ) then
329
                                                stp <= s34 after 1 ns;
330
                                        end if;
331
 
332
                        when s34 =>
333
                                        fifo0_rd <= '1' after 1 ns;
334
                                        stp <= s35 after 1 ns;
335
 
336
                        when s35 =>
337
                                        fifo0_rd <= '0' after 1 ns;
338
                                        if( tlp_dw0(30)='1' ) then
339
                                                stp <= s36 after 1 ns;
340
                                        else
341
                                                stp <= s4 after 1 ns;
342
                                        end if;
343
 
344
                        when s36 =>
345
                                        tlp_dw2 <= fifo0_dout( 31 downto 0 ) after 1 ns;
346
                                        if( fifo0_empty='0' ) then
347
                                                stp <= s37 after 1 ns;
348
                                        end if;
349
 
350
                        when s37 =>
351
                                        fifo0_rd <= '1' after 1 ns;
352
                                        stp <= s38 after 1 ns;
353
 
354
                        when s38 =>
355
                                        fifo0_rd <= '0' after 1 ns;
356
                                        stp <= s39 after 1 ns;
357
 
358
                        when s39 =>
359
                                        tlp_dw3 <= fifo0_dout( 31 downto 0 ) after 1 ns;
360
                                        request_reg_wr <= '1' after 1 ns;
361
                                        stp <= s5 after 1 ns;
362
 
363
                        when s4 =>
364
                                        tlp_dw2 <= fifo0_dout( 31 downto 0 ) after 1 ns;
365
                                        request_reg_rd <= '1' after 1 ns;
366
                                        stp <= s5 after 1 ns;
367
 
368
                        when s5 =>
369
                                        if( tx_rx_engine.complete_reg='1' ) then
370
                                                stp <= s0 after 1 ns;
371
                                        end if;
372
 
373
                end case;
374
 
375
 
376
 
377
                if( rstpz='1' ) then
378
                        stp <= s0 after 1 ns;
379
                end if;
380
 
381
        end if;
382
end process;
383
 
384
 
385
pr_stf: process( clk ) begin
386
 
387
        if( rising_edge( clk ) ) then
388
 
389
                case( stf ) is
390
 
391
                        when s0 =>
392
                        --if( fifo1_empty='0' ) then
393
                                if( fifo1_pae='0' ) then
394
                                        stf <= s1 after 1 ns;
395
                                end if;
396
                                fifo1_rd <= '0' after 1 ns;
397
                                data_rx_we_en   <= '0' after 1 ns;
398
 
399
                        when s1 =>
400
                                fifo1_rd <= '1' after 1 ns;
401
                                stf <= s2 after 1 ns;
402
 
403
                        when s2 =>
404
                                stf <= s3 after 1 ns;
405
 
406
                        when s3 =>
407
                                        tlp_cp_dw0   <= fifo1_dout( 31 downto 0 ) after 1 ns;
408
                                        stf <= s31 after 1 ns;
409
 
410
                        when s31 =>
411
                                        tlp_cp_dw1 <= fifo1_dout( 31 downto 0 ) after 1 ns;
412
                                        fifo1_rd <= '0' after 1 ns;
413
                                        stf <= s4 after 1 ns;
414
 
415
                        when s4 =>
416
                                        tlp_cp_dw2 <= fifo1_dout( 31 downto 0 ) after 1 ns;
417
                                        if( tlp_cp_dw0( 30 )='1' ) then
418
                                                stf <= s5 after 1 ns;   -- есть данные --
419
                                        else
420
                                                stf <= s6 after 1 ns;   -- нет данных --
421
                                        end if;
422
 
423
 
424
                        when s5 =>
425
 
426
                                        if( fifo1_dout(33)='0' and fifo1_valid='1' ) then
427
                                                stf <= s6 after 1 ns;
428
                                                fifo1_rd <= '0' after 1 ns;
429
                                                data_rx_we_en   <= '0' after 1 ns;
430
                                        else
431
                                                fifo1_rd <= '1' after 1 ns;
432
                                                data_rx_we_en   <= '1' after 1 ns;
433
                                        end if;
434
 
435
                        when s6 =>
436
                                        stf <= s0 after 1 ns;
437
 
438
 
439
 
440
                end case;
441
 
442
                if( rstpz='1' ) then
443
                        stf <= s0 after 1 ns;
444
                end if;
445
 
446
        end if;
447
 
448
 
449
end process;
450
 
451
pr_flag_rx_we: process( clk ) begin
452
        if( rising_edge( clk ) ) then
453
                if( stf=s0 ) then
454
                        flag_rx_we <= '0' after 1 ns;
455
                elsif( data_rx_we='1' ) then
456
                        flag_rx_we <= not flag_rx_we after 1 ns;
457
                end if;
458
        end if;
459
end process;
460
 
461
 
462
data_rx_we <= fifo1_valid and data_rx_we_en;
463
 
464
data_lrx <= fifo1_dout( 31 downto 0 ) after 1 ns when rising_edge( clk ) and fifo1_valid='1';
465
data_hrx <= fifo1_dout( 31 downto 0 );
466
 
467
data_rx( 32+31 downto 32+24 )  <= data_hrx( 7 downto 0 );
468
data_rx( 32+23 downto 32+16 )  <= data_hrx( 15 downto 8 );
469
data_rx( 32+15 downto 32+8 )   <= data_hrx( 23 downto 16 );
470
data_rx( 32+7 downto 32+0 )    <= data_hrx( 31 downto 24 );
471
 
472
 
473
data_rx( 31 downto 24 )  <= data_lrx( 7 downto 0 );
474
data_rx( 23 downto 16 )  <= data_lrx( 15 downto 8 );
475
data_rx( 15 downto 8 )   <= data_lrx( 23 downto 16 );
476
data_rx( 7 downto 0 )    <= data_lrx( 31 downto 24 );
477
 
478
pr_adr_cnt: process( clk ) begin
479
        if( rising_edge( clk ) ) then
480
                if( stf/=s5 ) then
481
                        adr_cnt <= "0000" after 1 ns;
482
                elsif( data_rx_we='1' and flag_rx_we='1' ) then
483
                        adr_cnt( 2 downto 0 ) <= adr_cnt( 2 downto 0 ) + 1 after 1 ns;
484
                        if( adr_cnt( 2 downto 0 )="111" ) then
485
                                adr_cnt( 3 ) <= '1' after 1 ns;
486
                        end if;
487
                end if;
488
        end if;
489
end process;
490
 
491
adr_rx( 2 downto 0 ) <= adr_cnt( 2 downto 0 );
492
adr_rx( 3 ) <=  tlp_cp_dw2(6) or adr_cnt( 3 );
493
adr_rx( 8 downto 4 ) <= tlp_cp_dw2( 12 downto 8 );
494
 
495
rx_ext_fifo.adr <= adr_rx after 1 ns when rising_edge( clk );
496
rx_ext_fifo.data <= data_rx after 1 ns when rising_edge( clk );
497
rx_ext_fifo.data_we <= data_rx_we and flag_rx_we after 1 ns when rising_edge( clk );
498
 
499
rx_tx_engine.complete_we <= data_rx_we and flag_rx_we after 1 ns when rising_edge( clk );
500
 
501
end core64_rx_engine_m4;

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