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-------------------------------------------------------------------------------
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--
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-- Title : core64_tx_engine
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.0
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Формирователь пакетов
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.core64_type_pkg.all;
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package core64_tx_engine_pkg is
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component core64_tx_engine is
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port(
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--- General ---
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rstp : in std_logic; --! 1 - сброс
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clk : in std_logic; --! тактовая частота ядра - 250 MHz
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trn_tx : out type_trn_tx; --! передача пакета
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trn_tx_back : in type_trn_tx_back; --! готовность к передаче пакета
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completer_id : in std_logic_vector( 15 downto 0 ); --! идентификатор устройства
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reg_access_back : in type_reg_access_back; --! запрос на доступ к регистрам
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rx_tx_engine : in type_rx_tx_engine; --! обмен RX->TX
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tx_rx_engine : out type_tx_rx_engine; --! обмен TX->RX
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tx_ext_fifo : out type_tx_ext_fifo; --! обмен TX->EXT_FIFO
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tx_ext_fifo_back: in type_tx_ext_fifo_back --! обмен TX->EXT_FIFO
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);
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use work.core64_type_pkg.all;
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library unisim;
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use unisim.vcomponents.all;
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entity core64_tx_engine is
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port(
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--- General ---
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rstp : in std_logic; --! 1 - сброс
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clk : in std_logic; --! тактовая частота ядра - 250 MHz
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trn_tx : out type_trn_tx; --! передача пакета
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trn_tx_back : in type_trn_tx_back; --! готовность к передаче пакета
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completer_id : in std_logic_vector( 15 downto 0 ); --! идентификатор устройства
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reg_access_back : in type_reg_access_back; --! запрос на доступ к регистрам
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rx_tx_engine : in type_rx_tx_engine; --! обмен RX->TX
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tx_rx_engine : out type_tx_rx_engine; --! обмен TX->RX
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tx_ext_fifo : out type_tx_ext_fifo; --! обмен TX->EXT_FIFO
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tx_ext_fifo_back: in type_tx_ext_fifo_back --! обмен TX->EXT_FIFO
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);
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end core64_tx_engine;
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architecture core64_tx_engine of core64_tx_engine is
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component ctrl_fifo64x67fw is
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port (
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clk : in std_logic;
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rst : in std_logic;
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din : in std_logic_vector(66 downto 0);
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wr_en : in std_logic;
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rd_en : in std_logic;
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dout : out std_logic_vector(66 downto 0);
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full : out std_logic;
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empty : out std_logic;
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valid : out std_logic;
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prog_full : out std_logic;
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prog_empty : out std_logic
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);
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end component;
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function set_data( data_in : in std_logic_vector( 63 downto 0 ) ) return std_logic_vector is
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variable ret : std_logic_vector( 63 downto 0 );
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begin
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for ii in 0 to 63 loop
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if( data_in(ii)='1' ) then
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ret(ii):='1';
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else
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ret(ii):='0';
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end if;
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end loop;
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return ret;
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end set_data;
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signal rstpz : std_logic;
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type stp_type is ( s0, s1, s2, s3, s4, sr1, sr2, sr3, sr4, sr5,
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sw1, sw01, sw2, sw3, sw5, sw6 );
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signal stp : stp_type;
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signal fifo_din : std_logic_vector( 66 downto 0 );
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signal fifo_wr : std_logic;
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signal fifo_rd : std_logic;
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signal fifo_dout : std_logic_vector( 66 downto 0 );
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signal fifo_full : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_valid : std_logic;
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signal fifo_paf : std_logic;
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signal fifo_pae : std_logic;
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signal fifo_sof : std_logic;
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signal fifo_eof : std_logic;
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signal fifo_rrem : std_logic;
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signal fifo_data : std_logic_vector( 63 downto 0 );
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signal reg_data : std_logic_vector( 31 downto 0 );
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signal tlp_dw0 : std_logic_vector( 31 downto 0 );
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signal tlp_dw1 : std_logic_vector( 31 downto 0 );
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signal tlp_dw2 : std_logic_vector( 31 downto 0 );
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signal tlp_dw3 : std_logic_vector( 31 downto 0 );
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signal cpl_status : std_logic_vector( 2 downto 0 ):="000";
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signal cpl_byte_count : std_logic_vector( 11 downto 0 ) :=x"000";
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signal tlp_read_dw0 : std_logic_vector( 31 downto 0 );
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signal tlp_read_dw1 : std_logic_vector( 31 downto 0 );
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signal tlp_read_dw2 : std_logic_vector( 31 downto 0 );
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signal tlp_read_dw3 : std_logic_vector( 31 downto 0 );
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signal max_read_size : std_logic_vector( 7 downto 0 );
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signal read_tag : std_logic_vector( 7 downto 0 );
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signal req_cnt : std_logic_vector( 5 downto 0 ); --! счётчик запросов
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signal req_complete : std_logic; --! 1 - получены все ответы
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signal wait_complete : std_logic;
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signal complete_cnt : std_logic_vector( 9 downto 0 ); --! счётчик принятых слов
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signal timeout_cnt : std_logic_vector( 10 downto 0 ); --! ожидание ответа
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signal timeout_cnt_en : std_logic;
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signal timeout_error : std_logic;
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signal timeout_st0 : std_logic;
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signal rstpz1 : std_logic;
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signal write_cnt_en : std_logic;
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signal write_cnt : std_logic_vector( 5 downto 0 ); --! счётчик слов в пакете
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signal write_cnt_pkg : std_logic_vector( 4 downto 0 ); --! счётчик пакетов
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signal write_cnt_eq : std_logic;
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signal write_cnt_pkg_eq: std_logic;
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signal write_state : std_logic;
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signal write_size : std_logic; --! 1 - пакет 256 байт, 0 - пакет 128 байт
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signal write_cnt_pkg_add : std_logic_vector( 1 downto 0 );
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signal tlp_write_dw0 : std_logic_vector( 31 downto 0 );
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signal tlp_write_dw1 : std_logic_vector( 31 downto 0 );
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signal tlp_write_dw2 : std_logic_vector( 31 downto 0 );
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signal tlp_write_dw3 : std_logic_vector( 31 downto 0 );
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signal tlp_write_data : std_logic_vector( 63 downto 0 );
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signal tlp_write_data_z: std_logic_vector( 31 downto 0 );
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signal adr_cnt : std_logic_vector( 5 downto 0 );
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signal adr64 : std_logic;
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begin
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trn_tx.trn_td <= fifo_dout( 63 downto 0 );
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trn_tx.trn_tsof_n <= fifo_dout( 64 );
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trn_tx.trn_teof_n <= fifo_dout( 65 );
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trn_tx.trn_trem_n( 7 downto 4 ) <= "0000";
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trn_tx.trn_trem_n( 3 downto 0 ) <= (others=>fifo_dout( 66 ) );
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trn_tx.trn_tsrc_dsc_n <= '1';
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trn_tx.trn_terrfwd_n <= '1';
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trn_tx.trn_tsrc_rdy_n <= fifo_empty or trn_tx_back.trn_tdst_rdy_n;
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fifo_rd <= not ( fifo_empty or trn_tx_back.trn_tdst_rdy_n );
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fifo0_reg: ctrl_fifo64x67fw
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port map(
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clk => clk,
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rst => rstpz,
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din => fifo_din,
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wr_en => fifo_wr,
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rd_en => fifo_rd,
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dout => fifo_dout,
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full => fifo_full,
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empty => fifo_empty,
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valid => fifo_valid,
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prog_full => fifo_paf,
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prog_empty => fifo_pae
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);
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rstpz <= rstp after 1 ns when rising_edge( clk );
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fifo_din <= fifo_rrem & fifo_eof & fifo_sof & set_data( fifo_data );
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pr_state: process( clk ) begin
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if( rising_edge( clk ) ) then
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case( stp ) is
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when s0 =>
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if( fifo_paf='0' ) then
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if( (rx_tx_engine.request_reg_wr='1' or rx_tx_engine.request_reg_rd='1') and trn_tx_back.trn_tbuf_av(2)='1' ) then
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stp <= s1 after 1 ns;
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elsif( tx_ext_fifo_back.req_rd='1' and trn_tx_back.trn_tbuf_av(0)='1' ) then
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stp <= sr1 after 1 ns;
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elsif( tx_ext_fifo_back.req_wr='1' and trn_tx_back.trn_tbuf_av(1)='1' ) then
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stp <= sw1 after 1 ns;
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end if;
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end if;
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fifo_wr <= '0';
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tx_rx_engine.complete_reg <= '0' after 1 ns;
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tx_ext_fifo.complete_ok <= '0' after 1 ns;
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tx_ext_fifo.complete_error <= '0' after 1 ns;
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write_cnt_en <= '0' after 1 ns;
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when s1 =>
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if( reg_access_back.complete='1' ) then
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if( rx_tx_engine.request_reg_wr='1' ) then
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stp <= s4 after 1 ns; -- не отправляется при операции записи
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else
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stp <= s2 after 1 ns;
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end if;
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end if;
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when s2 =>
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fifo_sof <= '0' after 1 ns;
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fifo_eof <= '1' after 1 ns;
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fifo_rrem <= rx_tx_engine.request_reg_wr after 1 ns;
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fifo_data <= tlp_dw0 & tlp_dw1 after 1 ns;
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fifo_wr <= '1' after 1 ns;
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stp <= s3 after 1 ns;
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when s3 =>
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fifo_sof <= '1' after 1 ns;
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fifo_eof <= '0' after 1 ns;
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fifo_rrem <= rx_tx_engine.request_reg_wr after 1 ns;
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fifo_data <= tlp_dw2 & tlp_dw3 after 1 ns;
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fifo_wr <= '1' after 1 ns;
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stp <= s4 after 1 ns;
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when s4 =>
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fifo_wr <= '0' after 1 ns;
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tx_rx_engine.complete_reg <= '1' after 1 ns;
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if( rx_tx_engine.request_reg_wr='0' and rx_tx_engine.request_reg_rd='0' ) then
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stp <= s0 after 1 ns;
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end if;
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when sr1 => ---- Запрос на чтение данных из памяти ----
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if( req_cnt(5)='1' or (req_cnt(2)='1' and tx_ext_fifo_back.rd_size='0' ) ) then
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stp <= sr4 after 1 ns;
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else
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stp <= sr2 after 1 ns;
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end if;
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when sr2 =>
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wait_complete <= '1' after 1 ns;
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fifo_sof <= '0' after 1 ns;
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fifo_eof <= '1' after 1 ns;
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fifo_rrem <= '0' after 1 ns;
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fifo_data <= tlp_read_dw0 & tlp_read_dw1 after 1 ns;
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fifo_wr <= '1' after 1 ns;
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stp <= sr3 after 1 ns;
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when sr3 =>
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fifo_sof <= '1' after 1 ns;
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fifo_eof <= '0' after 1 ns;
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if( adr64='1' ) then
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fifo_data <= tlp_read_dw2 & tlp_read_dw3 after 1 ns;
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else
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fifo_data <= tlp_read_dw3 & tlp_read_dw3 after 1 ns;
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end if;
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fifo_wr <= '1' after 1 ns;
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stp <= s0 after 1 ns;
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-- when sr3 => ---- Ожидание завершения запроса ----
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-- fifo_wr <= '0' after 1 ns;
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-- stp <= sr0 after 1 ns;
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when sr4 => --- Проверка завершения запроса ----
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if( req_complete='1' or timeout_error='1' ) then
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stp <= sr5 after 1 ns;
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else
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stp <= s0 after 1 ns;
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end if;
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when sr5 =>
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wait_complete <= '0' after 1 ns;
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tx_ext_fifo.complete_ok <= req_complete after 1 ns;
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tx_ext_fifo.complete_error <= timeout_error after 1 ns;
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if( tx_ext_fifo_back.req_rd='0' ) then
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stp <= s0 after 1 ns;
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end if;
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when sw1 => --- Запись 4 кБ ---
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write_cnt_en <= not adr64 after 1 ns;
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|
|
stp <= sw01 after 1 ns;
|
330 |
|
|
|
331 |
|
|
when sw01 => --- Запись 4 кБ ---
|
332 |
|
|
|
333 |
|
|
|
334 |
|
|
write_state <= '1' after 1 ns;
|
335 |
|
|
|
336 |
|
|
|
337 |
|
|
fifo_sof <= '0' after 1 ns;
|
338 |
|
|
fifo_eof <= '1' after 1 ns;
|
339 |
|
|
fifo_rrem <= not adr64 after 1 ns;
|
340 |
|
|
fifo_data <= tlp_write_dw0 & tlp_write_dw1 after 1 ns;
|
341 |
|
|
fifo_wr <= '1' after 1 ns;
|
342 |
|
|
|
343 |
|
|
write_cnt_en <= '1' after 1 ns;
|
344 |
|
|
stp <= sw2 after 1 ns;
|
345 |
|
|
|
346 |
|
|
|
347 |
|
|
when sw2 =>
|
348 |
|
|
fifo_sof <= '1' after 1 ns;
|
349 |
|
|
if( adr64='1' ) then
|
350 |
|
|
fifo_data <= tlp_write_dw2 & tlp_write_dw3 after 1 ns;
|
351 |
|
|
else
|
352 |
|
|
fifo_data <= tlp_write_dw3 & tlp_write_data( 63 downto 32 ) after 1 ns;
|
353 |
|
|
end if;
|
354 |
|
|
|
355 |
|
|
stp <= sw3 after 1 ns;
|
356 |
|
|
|
357 |
|
|
when sw3 =>
|
358 |
|
|
if( adr64='1' ) then
|
359 |
|
|
fifo_data <= tlp_write_data after 1 ns;
|
360 |
|
|
else
|
361 |
|
|
fifo_data( 31 downto 0 ) <= tlp_write_data( 63 downto 32 ) after 1 ns;
|
362 |
|
|
fifo_data( 63 downto 32 ) <= tlp_write_data_z( 31 downto 0 ) after 1 ns;
|
363 |
|
|
end if;
|
364 |
|
|
|
365 |
|
|
|
366 |
|
|
fifo_wr <= '1' after 1 ns;
|
367 |
|
|
if( write_cnt_eq='1' ) then
|
368 |
|
|
stp <= sw5 after 1 ns;
|
369 |
|
|
-- elsif( fifo_paf='1' ) then
|
370 |
|
|
-- stp <= sw4 after 1 ns;
|
371 |
|
|
end if;
|
372 |
|
|
|
373 |
|
|
-- when sw4 =>
|
374 |
|
|
-- write_cnt_en <= '0' after 1 ns;
|
375 |
|
|
-- fifo_wr <= '0' after 1 ns;
|
376 |
|
|
-- if( fifo_paf='0' ) then
|
377 |
|
|
-- stp <= sw3 after 1 ns;
|
378 |
|
|
-- end if;
|
379 |
|
|
|
380 |
|
|
when sw5 =>
|
381 |
|
|
if( adr64='1' ) then
|
382 |
|
|
fifo_data <= tlp_write_data after 1 ns;
|
383 |
|
|
else
|
384 |
|
|
fifo_data( 31 downto 0 ) <= tlp_write_data( 63 downto 32 ) after 1 ns;
|
385 |
|
|
fifo_data( 63 downto 32 ) <= tlp_write_data_z( 31 downto 0 ) after 1 ns;
|
386 |
|
|
end if;
|
387 |
|
|
|
388 |
|
|
fifo_eof <= '0' after 1 ns;
|
389 |
|
|
write_cnt_en <= '0' after 1 ns;
|
390 |
|
|
if( write_cnt_pkg_eq='1' ) then
|
391 |
|
|
stp <= sw6 after 1 ns;
|
392 |
|
|
else
|
393 |
|
|
stp <= s0 after 1 ns;
|
394 |
|
|
end if;
|
395 |
|
|
|
396 |
|
|
when sw6 =>
|
397 |
|
|
fifo_wr <= '0' after 1 ns;
|
398 |
|
|
tx_ext_fifo.complete_ok <= '1' after 1 ns;
|
399 |
|
|
tx_ext_fifo.complete_error <= '0' after 1 ns;
|
400 |
|
|
write_state <= '0' after 1 ns;
|
401 |
|
|
if( tx_ext_fifo_back.req_wr='0' ) then
|
402 |
|
|
stp <= s0 after 1 ns;
|
403 |
|
|
end if;
|
404 |
|
|
|
405 |
|
|
|
406 |
|
|
|
407 |
|
|
|
408 |
|
|
|
409 |
|
|
end case;
|
410 |
|
|
|
411 |
|
|
|
412 |
|
|
|
413 |
|
|
|
414 |
|
|
|
415 |
|
|
if( rstpz='1' ) then
|
416 |
|
|
stp <= s0 after 1 ns;
|
417 |
|
|
wait_complete <= '0' after 1 ns;
|
418 |
|
|
write_state <= '0' after 1 ns;
|
419 |
|
|
end if;
|
420 |
|
|
|
421 |
|
|
end if;
|
422 |
|
|
end process;
|
423 |
|
|
|
424 |
|
|
|
425 |
|
|
tlp_dw0 <= "0" & rx_tx_engine.request_reg_rd & "0010100" & rx_tx_engine.request_tc & "0000" & rx_tx_engine.request_attr & "0000" & "0000000" & rx_tx_engine.request_reg_rd;
|
426 |
|
|
tlp_dw1 <= completer_id & cpl_status & '0' & cpl_byte_count;
|
427 |
|
|
tlp_dw2 <= rx_tx_engine.request_id & rx_tx_engine.request_tag & '0' & rx_tx_engine.lower_adr & "00";
|
428 |
|
|
|
429 |
|
|
--cpl_byte_count <= "0000" & "0000" & "0" & rx_tx_engine.request_reg_rd & "00";
|
430 |
|
|
cpl_byte_count <= "0000" & "0000" & "0" & rx_tx_engine.byte_count;
|
431 |
|
|
|
432 |
|
|
reg_data <= reg_access_back.data after 1 ns when rising_edge( clk ) and reg_access_back.data_we='1';
|
433 |
|
|
tlp_dw3( 7 downto 0 ) <= reg_data( 31 downto 24 );
|
434 |
|
|
tlp_dw3( 15 downto 8 ) <= reg_data( 23 downto 16 );
|
435 |
|
|
tlp_dw3( 23 downto 16 ) <= reg_data( 15 downto 8 );
|
436 |
|
|
tlp_dw3( 31 downto 24 ) <= reg_data( 7 downto 0 );
|
437 |
|
|
|
438 |
|
|
max_read_size <= x"20"; -- 128 байт
|
439 |
|
|
read_tag <= "000" & req_cnt( 4 downto 0 );
|
440 |
|
|
|
441 |
|
|
adr64 <= tx_ext_fifo_back.pci_adr( 39 ) or
|
442 |
|
|
tx_ext_fifo_back.pci_adr( 38 ) or
|
443 |
|
|
tx_ext_fifo_back.pci_adr( 37 ) or
|
444 |
|
|
tx_ext_fifo_back.pci_adr( 36 ) or
|
445 |
|
|
tx_ext_fifo_back.pci_adr( 35 ) or
|
446 |
|
|
tx_ext_fifo_back.pci_adr( 34 ) or
|
447 |
|
|
tx_ext_fifo_back.pci_adr( 33 ) or
|
448 |
|
|
tx_ext_fifo_back.pci_adr( 32 );
|
449 |
|
|
|
450 |
|
|
tlp_read_dw0 <= "00" & adr64 & '0' & x"000" & "00000000" & max_read_size;
|
451 |
|
|
tlp_read_dw1 <= completer_id & read_tag & x"FF";
|
452 |
|
|
tlp_read_dw2 <= x"000000" & tx_ext_fifo_back.pci_adr( 39 downto 32 );
|
453 |
|
|
tlp_read_dw3( 6 downto 0 ) <= "0000000";
|
454 |
|
|
tlp_read_dw3( 8 downto 7 ) <= req_cnt( 1 downto 0 );
|
455 |
|
|
tlp_read_dw3( 11 downto 9 ) <= req_cnt( 4 downto 2 ) when tx_ext_fifo_back.rd_size='1'
|
456 |
|
|
else tx_ext_fifo_back.pci_adr( 11 downto 9 );
|
457 |
|
|
|
458 |
|
|
tlp_read_dw3( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 );
|
459 |
|
|
|
460 |
|
|
|
461 |
|
|
--tlp_read_dw0 <= x"0000" & "00000000" & max_read_size;
|
462 |
|
|
--tlp_read_dw1 <= completer_id & read_tag & x"FF";
|
463 |
|
|
--
|
464 |
|
|
--tlp_read_dw2( 6 downto 0 ) <= "0000000";
|
465 |
|
|
--tlp_read_dw2( 8 downto 7 ) <= req_cnt( 1 downto 0 );
|
466 |
|
|
--tlp_read_dw2( 11 downto 9 ) <= req_cnt( 4 downto 2 ) when tx_ext_fifo_back.rd_size='1'
|
467 |
|
|
-- else tx_ext_fifo_back.pci_adr( 11 downto 9 );
|
468 |
|
|
--
|
469 |
|
|
--tlp_read_dw2( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 );
|
470 |
|
|
--
|
471 |
|
|
--tlp_read_dw3 <= (others=>'0');
|
472 |
|
|
|
473 |
|
|
|
474 |
|
|
|
475 |
|
|
pr_req_cnt: process( clk ) begin
|
476 |
|
|
if( rising_edge( clk ) ) then
|
477 |
|
|
if( stp=s0 and wait_complete='0' ) then
|
478 |
|
|
req_cnt <= (others=>'0') after 1 ns;
|
479 |
|
|
elsif( stp=sr3 ) then
|
480 |
|
|
req_cnt <= req_cnt + 1 after 1 ns;
|
481 |
|
|
end if;
|
482 |
|
|
end if;
|
483 |
|
|
end process;
|
484 |
|
|
|
485 |
|
|
|
486 |
|
|
|
487 |
|
|
rstpz1 <= rstpz after 1 ns when rising_edge( clk );
|
488 |
|
|
timeout_st0 <= ( not rstpz ) and (rstpz1 or timeout_cnt_en ) after 1 ns when rising_edge( clk );
|
489 |
|
|
|
490 |
|
|
xtcnt: srlc32e port map( q31=>timeout_cnt_en, clk=>clk, d=>timeout_st0, a=>"11111", ce=>'1' );
|
491 |
|
|
|
492 |
|
|
pr_timeout_cnt: process( clk ) begin
|
493 |
|
|
if( rising_edge( clk ) ) then
|
494 |
|
|
if( wait_complete='0' ) then
|
495 |
|
|
timeout_cnt <= (others=>'0') after 1 ns;
|
496 |
|
|
elsif( timeout_cnt_en='1' ) then
|
497 |
|
|
timeout_cnt <= timeout_cnt + 1 after 1 ns;
|
498 |
|
|
end if;
|
499 |
|
|
end if;
|
500 |
|
|
end process;
|
501 |
|
|
|
502 |
|
|
timeout_error <= timeout_cnt(10);
|
503 |
|
|
|
504 |
|
|
pr_complete_cnt: process( clk ) begin
|
505 |
|
|
if( rising_edge( clk ) ) then
|
506 |
|
|
if( wait_complete='0' ) then
|
507 |
|
|
if( tx_ext_fifo_back.rd_size='0' ) then
|
508 |
|
|
complete_cnt <= "0111000000" after 1 ns; -- 513-64 -- ожидается 512 байт
|
509 |
|
|
else
|
510 |
|
|
complete_cnt <= "0000000000" after 1 ns; -- ожидается 4096 байт (512 слов по 8 байт)
|
511 |
|
|
end if;
|
512 |
|
|
elsif( rx_tx_engine.complete_we='1' ) then
|
513 |
|
|
complete_cnt <= complete_cnt + 1 after 1 ns;
|
514 |
|
|
end if;
|
515 |
|
|
end if;
|
516 |
|
|
end process;
|
517 |
|
|
|
518 |
|
|
req_complete <= complete_cnt(9);
|
519 |
|
|
|
520 |
|
|
write_size <= trn_tx_back.cfg_dcommand(5);
|
521 |
|
|
|
522 |
|
|
pr_write_cnt: process( clk ) begin
|
523 |
|
|
if( rising_edge( clk ) ) then
|
524 |
|
|
if( stp=s0 ) then
|
525 |
|
|
write_cnt <= '0' & not write_size & "000" & adr64 after 1 ns;
|
526 |
|
|
elsif( write_cnt_en='1' ) then
|
527 |
|
|
write_cnt <= write_cnt + 1 after 1 ns;
|
528 |
|
|
end if;
|
529 |
|
|
end if;
|
530 |
|
|
end process;
|
531 |
|
|
|
532 |
|
|
write_cnt_eq <= write_cnt(5);
|
533 |
|
|
|
534 |
|
|
write_cnt_pkg_add <= write_size & not write_size;
|
535 |
|
|
|
536 |
|
|
pr_write_cnt_pkg: process( clk ) begin
|
537 |
|
|
if( rising_edge( clk ) ) then
|
538 |
|
|
if( stp=s0 and write_state='0' ) then
|
539 |
|
|
write_cnt_pkg <= "00000" after 1 ns;
|
540 |
|
|
elsif( stp=sw5 ) then
|
541 |
|
|
write_cnt_pkg <= write_cnt_pkg + write_cnt_pkg_add after 1 ns;
|
542 |
|
|
end if;
|
543 |
|
|
end if;
|
544 |
|
|
end process;
|
545 |
|
|
|
546 |
|
|
write_cnt_pkg_eq <= write_cnt_pkg(4) and write_cnt_pkg(3) and write_cnt_pkg(2) and write_cnt_pkg(1) and (write_cnt_pkg(0) or write_size);
|
547 |
|
|
|
548 |
|
|
|
549 |
|
|
tlp_write_dw0 <= "01" & adr64 & '0' & x"000" & "00000000" & "0" & write_size & not write_size & "00000";
|
550 |
|
|
tlp_write_dw1 <= tlp_read_dw1;
|
551 |
|
|
tlp_write_dw2 <= tlp_read_dw2; --x"000000" & tx_ext_fifo_back.pci_adr( 39 downto 32 );
|
552 |
|
|
tlp_write_dw3( 6 downto 0 ) <= "0000000";
|
553 |
|
|
tlp_write_dw3( 11 downto 7 ) <= write_cnt_pkg( 4 downto 0 );
|
554 |
|
|
tlp_write_dw3( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 );
|
555 |
|
|
|
556 |
|
|
|
557 |
|
|
--tlp_write_data <= x"00000000" & x"0000" & "0000000000" & write_cnt;
|
558 |
|
|
gen_repack: for ii in 0 to 7 generate
|
559 |
|
|
tlp_write_data( ii*8+7 downto ii*8 ) <= tx_ext_fifo_back.data( (7-ii)*8+7 downto (7-ii)*8 );
|
560 |
|
|
end generate;
|
561 |
|
|
|
562 |
|
|
tlp_write_data_z <= tlp_write_data( 31 downto 0 ) after 1 ns when rising_edge( clk );
|
563 |
|
|
|
564 |
|
|
pr_adr_cnt: process( clk ) begin
|
565 |
|
|
if( rising_edge( clk ) ) then
|
566 |
|
|
if( write_cnt_en='0' ) then
|
567 |
|
|
adr_cnt <= (others=>'0') after 1 ns;
|
568 |
|
|
else
|
569 |
|
|
adr_cnt <= adr_cnt + 1 after 1 ns;
|
570 |
|
|
end if;
|
571 |
|
|
end if;
|
572 |
|
|
end process;
|
573 |
|
|
|
574 |
|
|
tx_ext_fifo.adr( 3 downto 0 ) <= adr_cnt( 3 downto 0 );
|
575 |
|
|
tx_ext_fifo.adr( 4 ) <= adr_cnt(4) or write_cnt_pkg(0);
|
576 |
|
|
tx_ext_fifo.adr( 8 downto 5 ) <= write_cnt_pkg( 4 downto 1 );
|
577 |
|
|
|
578 |
|
|
end core64_tx_engine;
|