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-------------------------------------------------------------------------------
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--
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-- Title : core64_tx_engine_m2
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.2
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Формирователь пакетов
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-- Модификация 2 - используется интерфейс AXI
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.2 27.06.2012
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-- Добавлена возможность формирования INTA - INTD
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.1 19.06.2012
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-- Исправлено формирование cpl_byte_count
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.0 16.08.2011
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-- Создан из core64_tx_engine v1.0
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.core64_type_pkg.all;
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package core64_tx_engine_m2_pkg is
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component core64_tx_engine_m2 is
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generic(
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interrupt_number : in std_logic_vector( 1 downto 0 ):="00" -- номер INTx: 0 - INTA, 1 - INTB, 2 - INTC, 3 - INTD
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);
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port(
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--- General ---
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rstp : in std_logic; --! 1 - сброс
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clk : in std_logic; --! тактовая частота ядра - 250 MHz
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trn_tx : out type_axi_tx; --! передача пакета
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trn_tx_back : in type_axi_tx_back; --! готовность к передаче пакета
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completer_id : in std_logic_vector( 15 downto 0 ); --! идентификатор устройства
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cfg_interrupt : in std_logic:='1'; --! 0 - изменение состояния прерывания
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cfg_interrupt_assert : in std_logic:='1'; --! 0 - формирование прерывания, 1 - сниятие прерывания
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cfg_interrupt_rdy : out std_logic; --! 0 - подтверждение изменения прерывания
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reg_access_back : in type_reg_access_back; --! запрос на доступ к регистрам
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rx_tx_engine : in type_rx_tx_engine; --! обмен RX->TX
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tx_rx_engine : out type_tx_rx_engine; --! обмен TX->RX
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tx_ext_fifo : out type_tx_ext_fifo; --! обмен TX->EXT_FIFO
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tx_ext_fifo_back: in type_tx_ext_fifo_back --! обмен TX->EXT_FIFO
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);
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use work.core64_type_pkg.all;
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library unisim;
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use unisim.vcomponents.all;
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entity core64_tx_engine_m2 is
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generic(
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interrupt_number : in std_logic_vector( 1 downto 0 ):="00" -- номер INTx: 0 - INTA, 1 - INTB, 2 - INTC, 3 - INTD
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);
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port(
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--- General ---
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rstp : in std_logic; --! 1 - сброс
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clk : in std_logic; --! тактовая частота ядра - 250 MHz
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trn_tx : out type_axi_tx; --! передача пакета
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trn_tx_back : in type_axi_tx_back; --! готовность к передаче пакета
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completer_id : in std_logic_vector( 15 downto 0 ); --! идентификатор устройства
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cfg_interrupt : in std_logic:='1'; --! 0 - изменение состояния прерывания
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cfg_interrupt_assert : in std_logic:='1'; --! 0 - формирование прерывания, 1 - сниятие прерывания
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cfg_interrupt_rdy : out std_logic; --! 0 - подтверждение изменения прерывания
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reg_access_back : in type_reg_access_back; --! запрос на доступ к регистрам
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rx_tx_engine : in type_rx_tx_engine; --! обмен RX->TX
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tx_rx_engine : out type_tx_rx_engine; --! обмен TX->RX
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tx_ext_fifo : out type_tx_ext_fifo; --! обмен TX->EXT_FIFO
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tx_ext_fifo_back: in type_tx_ext_fifo_back --! обмен TX->EXT_FIFO
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);
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end core64_tx_engine_m2;
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architecture core64_tx_engine_m2 of core64_tx_engine_m2 is
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component ctrl_fifo64x67fw is
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port (
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clk : in std_logic;
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rst : in std_logic;
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din : in std_logic_vector(66 downto 0);
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wr_en : in std_logic;
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rd_en : in std_logic;
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dout : out std_logic_vector(66 downto 0);
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full : out std_logic;
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empty : out std_logic;
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valid : out std_logic;
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prog_full : out std_logic;
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prog_empty : out std_logic
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);
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end component;
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function set_data( data_in : in std_logic_vector( 63 downto 0 ) ) return std_logic_vector is
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variable ret : std_logic_vector( 63 downto 0 );
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begin
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for ii in 0 to 63 loop
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if( data_in(ii)='1' ) then
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ret(ii):='1';
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else
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ret(ii):='0';
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end if;
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end loop;
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return ret;
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end set_data;
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signal rstpz : std_logic;
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type stp_type is ( s0, si1, si2, si3, s1, s2, s3, s4, sr1, sr2, sr3, sr4, sr5,
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sw1, sw01, sw2, sw3, sw5, sw6 );
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signal stp : stp_type;
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signal fifo_din : std_logic_vector( 66 downto 0 );
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signal fifo_wr : std_logic;
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signal fifo_rd : std_logic;
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signal fifo_dout : std_logic_vector( 66 downto 0 );
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signal fifo_full : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_valid : std_logic;
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signal fifo_paf : std_logic;
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signal fifo_pae : std_logic;
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signal fifo_sof : std_logic;
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signal fifo_eof : std_logic;
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signal fifo_rrem : std_logic;
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signal fifo_data : std_logic_vector( 63 downto 0 );
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signal reg_data : std_logic_vector( 31 downto 0 );
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signal tlp_dw0 : std_logic_vector( 31 downto 0 );
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signal tlp_dw1 : std_logic_vector( 31 downto 0 );
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signal tlp_dw2 : std_logic_vector( 31 downto 0 );
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signal tlp_dw3 : std_logic_vector( 31 downto 0 );
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signal cpl_status : std_logic_vector( 2 downto 0 ):="000";
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signal cpl_byte_count : std_logic_vector( 11 downto 0 ) :=x"000";
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signal tlp_read_dw0 : std_logic_vector( 31 downto 0 );
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signal tlp_read_dw1 : std_logic_vector( 31 downto 0 );
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signal tlp_read_dw2 : std_logic_vector( 31 downto 0 );
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signal tlp_read_dw3 : std_logic_vector( 31 downto 0 );
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signal max_read_size : std_logic_vector( 7 downto 0 );
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signal read_tag : std_logic_vector( 7 downto 0 );
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signal req_cnt : std_logic_vector( 5 downto 0 ); --! счётчик запросов
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signal req_complete : std_logic; --! 1 - получены все ответы
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signal wait_complete : std_logic;
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signal complete_cnt : std_logic_vector( 9 downto 0 ); --! счётчик принятых слов
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signal timeout_cnt : std_logic_vector( 10 downto 0 ); --! ожидание ответа
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signal timeout_cnt_en : std_logic;
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signal timeout_error : std_logic;
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signal timeout_st0 : std_logic;
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signal rstpz1 : std_logic;
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signal write_cnt_en : std_logic;
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signal write_cnt : std_logic_vector( 5 downto 0 ); --! счётчик слов в пакете
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signal write_cnt_pkg : std_logic_vector( 4 downto 0 ); --! счётчик пакетов
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signal write_cnt_eq : std_logic;
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signal write_cnt_pkg_eq: std_logic;
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signal write_state : std_logic;
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signal write_size : std_logic; --! 1 - пакет 256 байт, 0 - пакет 128 байт
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signal write_cnt_pkg_add : std_logic_vector( 1 downto 0 );
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signal tlp_write_dw0 : std_logic_vector( 31 downto 0 );
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signal tlp_write_dw1 : std_logic_vector( 31 downto 0 );
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signal tlp_write_dw2 : std_logic_vector( 31 downto 0 );
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signal tlp_write_dw3 : std_logic_vector( 31 downto 0 );
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signal tlp_write_data : std_logic_vector( 63 downto 0 );
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signal tlp_write_data_z: std_logic_vector( 31 downto 0 );
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signal adr_cnt : std_logic_vector( 5 downto 0 );
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signal adr64 : std_logic;
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signal axis_tx_tstrb_h : std_logic;
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signal allow_wr : std_logic;
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signal allow_cpl : std_logic;
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signal tbuf_av : std_logic_vector( 5 downto 0 );
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signal tlp_irq_dw0 : std_logic_vector( 31 downto 0 );
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signal tlp_irq_dw1 : std_logic_vector( 31 downto 0 );
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signal tlp_irq_dw2 : std_logic_vector( 31 downto 0 );
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signal tlp_irq_dw3 : std_logic_vector( 31 downto 0 );
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begin
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trn_tx.s_axis_tx_tdata <= fifo_dout( 31 downto 0 ) & fifo_dout( 63 downto 32 );
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trn_tx.s_axis_tx_tstrb( 3 downto 0 ) <= "1111";
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axis_tx_tstrb_h <= fifo_dout( 65 ) or fifo_dout(66);
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trn_tx.s_axis_tx_tstrb( 7 downto 4 ) <= (others=> axis_tx_tstrb_h );
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trn_tx.s_axis_tx_tvalid <= fifo_valid;
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trn_tx.s_axis_tx_tlast <= not fifo_dout( 65 );
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trn_tx.s_axis_tx_tuser <= "0000";
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--trn_tx.trn_tsof_n <= fifo_dout( 64 );
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--trn_tx.trn_teof_n <= fifo_dout( 65 );
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--trn_tx.trn_trem_n( 7 downto 4 ) <= "0000";
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--trn_tx.trn_trem_n( 3 downto 0 ) <= (others=>fifo_dout( 66 ) );
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--
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--trn_tx.trn_tsrc_dsc_n <= '1';
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--trn_tx.trn_terrfwd_n <= '1';
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--
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--trn_tx.trn_tsrc_rdy_n <= fifo_empty or trn_tx_back.trn_tdst_rdy_n;
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fifo_rd <= (not fifo_empty) and trn_tx_back.s_axis_tx_tready;
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fifo0_reg: ctrl_fifo64x67fw
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port map(
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clk => clk,
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rst => rstpz,
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din => fifo_din,
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wr_en => fifo_wr,
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rd_en => fifo_rd,
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dout => fifo_dout,
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full => fifo_full,
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empty => fifo_empty,
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valid => fifo_valid,
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prog_full => fifo_paf,
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prog_empty => fifo_pae
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);
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rstpz <= rstp after 1 ns when rising_edge( clk );
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fifo_din <= fifo_rrem & fifo_eof & fifo_sof & set_data( fifo_data );
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tbuf_av <= trn_tx_back.trn_tbuf_av;
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allow_cpl <= tbuf_av(4) or tbuf_av(3) or tbuf_av(2) or tbuf_av(1) or tbuf_av(0) after 1 ns when rising_edge( clk );
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allow_wr <= tbuf_av(4) or tbuf_av(3) or tbuf_av(2) after 1 ns when rising_edge( clk );
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pr_state: process( clk ) begin
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if( rising_edge( clk ) ) then
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case( stp ) is
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when s0 =>
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if( fifo_paf='0' ) then
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if( cfg_interrupt='0' and allow_wr='1' ) then
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stp <= si1 after 1 ns;
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elsif( (rx_tx_engine.request_reg_wr='1' or rx_tx_engine.request_reg_rd='1') and allow_cpl='1' ) then
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stp <= s1 after 1 ns;
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elsif( tx_ext_fifo_back.req_rd='1' and allow_wr='1' ) then
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stp <= sr1 after 1 ns;
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elsif( tx_ext_fifo_back.req_wr='1' and allow_wr='1' ) then
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stp <= sw1 after 1 ns;
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end if;
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end if;
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fifo_wr <= '0';
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tx_rx_engine.complete_reg <= '0' after 1 ns;
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tx_ext_fifo.complete_ok <= '0' after 1 ns;
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tx_ext_fifo.complete_error <= '0' after 1 ns;
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write_cnt_en <= '0' after 1 ns;
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cfg_interrupt_rdy <= '1' after 1 ns;
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when si1 =>
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fifo_sof <= '0' after 1 ns;
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| 306 |
|
|
fifo_eof <= '1' after 1 ns;
|
| 307 |
|
|
fifo_rrem <= '1' after 1 ns;
|
| 308 |
|
|
fifo_data <= tlp_irq_dw0 & tlp_irq_dw1 after 1 ns;
|
| 309 |
|
|
fifo_wr <= '1' after 1 ns;
|
| 310 |
|
|
stp <= si2 after 1 ns;
|
| 311 |
|
|
|
| 312 |
|
|
when si2 =>
|
| 313 |
|
|
|
| 314 |
|
|
fifo_sof <= '1' after 1 ns;
|
| 315 |
|
|
fifo_eof <= '0' after 1 ns;
|
| 316 |
|
|
fifo_rrem <= '1' after 1 ns;
|
| 317 |
|
|
fifo_data <= tlp_irq_dw2 & tlp_irq_dw3 after 1 ns;
|
| 318 |
|
|
fifo_wr <= '1' after 1 ns;
|
| 319 |
|
|
stp <= si3 after 1 ns;
|
| 320 |
|
|
|
| 321 |
|
|
when si3 =>
|
| 322 |
|
|
fifo_wr <= '0' after 1 ns;
|
| 323 |
|
|
cfg_interrupt_rdy <= '0' after 1 ns;
|
| 324 |
|
|
if( cfg_interrupt='1' ) then
|
| 325 |
|
|
stp <= s0 after 1 ns;
|
| 326 |
|
|
end if;
|
| 327 |
|
|
|
| 328 |
|
|
|
| 329 |
|
|
when s1 =>
|
| 330 |
|
|
if( reg_access_back.complete='1' ) then
|
| 331 |
|
|
if( rx_tx_engine.request_reg_wr='1' ) then
|
| 332 |
|
|
stp <= s4 after 1 ns; -- не отправляется при операции записи
|
| 333 |
|
|
else
|
| 334 |
|
|
stp <= s2 after 1 ns;
|
| 335 |
|
|
end if;
|
| 336 |
|
|
end if;
|
| 337 |
|
|
|
| 338 |
|
|
when s2 =>
|
| 339 |
|
|
fifo_sof <= '0' after 1 ns;
|
| 340 |
|
|
fifo_eof <= '1' after 1 ns;
|
| 341 |
|
|
fifo_rrem <= '1' after 1 ns;
|
| 342 |
|
|
fifo_data <= tlp_dw0 & tlp_dw1 after 1 ns;
|
| 343 |
|
|
fifo_wr <= '1' after 1 ns;
|
| 344 |
|
|
stp <= s3 after 1 ns;
|
| 345 |
|
|
|
| 346 |
|
|
when s3 =>
|
| 347 |
|
|
|
| 348 |
|
|
fifo_sof <= '1' after 1 ns;
|
| 349 |
|
|
fifo_eof <= '0' after 1 ns;
|
| 350 |
|
|
fifo_rrem <= '1' after 1 ns;
|
| 351 |
|
|
fifo_data <= tlp_dw2 & tlp_dw3 after 1 ns;
|
| 352 |
|
|
fifo_wr <= '1' after 1 ns;
|
| 353 |
|
|
stp <= s4 after 1 ns;
|
| 354 |
|
|
|
| 355 |
|
|
when s4 =>
|
| 356 |
|
|
fifo_wr <= '0' after 1 ns;
|
| 357 |
|
|
tx_rx_engine.complete_reg <= '1' after 1 ns;
|
| 358 |
|
|
if( rx_tx_engine.request_reg_wr='0' and rx_tx_engine.request_reg_rd='0' ) then
|
| 359 |
|
|
stp <= s0 after 1 ns;
|
| 360 |
|
|
end if;
|
| 361 |
|
|
|
| 362 |
|
|
when sr1 => ---- Запрос на чтение данных из памяти ----
|
| 363 |
|
|
|
| 364 |
|
|
if( req_cnt(5)='1' or (req_cnt(2)='1' and tx_ext_fifo_back.rd_size='0' ) ) then
|
| 365 |
|
|
stp <= sr4 after 1 ns;
|
| 366 |
|
|
else
|
| 367 |
|
|
stp <= sr2 after 1 ns;
|
| 368 |
|
|
end if;
|
| 369 |
|
|
|
| 370 |
|
|
when sr2 =>
|
| 371 |
|
|
wait_complete <= '1' after 1 ns;
|
| 372 |
|
|
fifo_sof <= '0' after 1 ns;
|
| 373 |
|
|
fifo_eof <= '1' after 1 ns;
|
| 374 |
|
|
fifo_rrem <= adr64 after 1 ns;
|
| 375 |
|
|
fifo_data <= tlp_read_dw0 & tlp_read_dw1 after 1 ns;
|
| 376 |
|
|
fifo_wr <= '1' after 1 ns;
|
| 377 |
|
|
stp <= sr3 after 1 ns;
|
| 378 |
|
|
|
| 379 |
|
|
when sr3 =>
|
| 380 |
|
|
fifo_sof <= '1' after 1 ns;
|
| 381 |
|
|
fifo_eof <= '0' after 1 ns;
|
| 382 |
|
|
if( adr64='1' ) then
|
| 383 |
|
|
fifo_data <= tlp_read_dw2 & tlp_read_dw3 after 1 ns;
|
| 384 |
|
|
else
|
| 385 |
|
|
fifo_data <= tlp_read_dw3 & tlp_read_dw3 after 1 ns;
|
| 386 |
|
|
end if;
|
| 387 |
|
|
|
| 388 |
|
|
fifo_wr <= '1' after 1 ns;
|
| 389 |
|
|
stp <= s0 after 1 ns;
|
| 390 |
|
|
|
| 391 |
|
|
-- when sr3 => ---- Ожидание завершения запроса ----
|
| 392 |
|
|
-- fifo_wr <= '0' after 1 ns;
|
| 393 |
|
|
-- stp <= sr0 after 1 ns;
|
| 394 |
|
|
|
| 395 |
|
|
when sr4 => --- Проверка завершения запроса ----
|
| 396 |
|
|
if( req_complete='1' or timeout_error='1' ) then
|
| 397 |
|
|
stp <= sr5 after 1 ns;
|
| 398 |
|
|
else
|
| 399 |
|
|
stp <= s0 after 1 ns;
|
| 400 |
|
|
end if;
|
| 401 |
|
|
|
| 402 |
|
|
when sr5 =>
|
| 403 |
|
|
wait_complete <= '0' after 1 ns;
|
| 404 |
|
|
tx_ext_fifo.complete_ok <= req_complete after 1 ns;
|
| 405 |
|
|
tx_ext_fifo.complete_error <= timeout_error after 1 ns;
|
| 406 |
|
|
if( tx_ext_fifo_back.req_rd='0' ) then
|
| 407 |
|
|
stp <= s0 after 1 ns;
|
| 408 |
|
|
end if;
|
| 409 |
|
|
|
| 410 |
|
|
|
| 411 |
|
|
when sw1 => --- Запись 4 кБ ---
|
| 412 |
|
|
|
| 413 |
|
|
write_cnt_en <= not adr64 after 1 ns;
|
| 414 |
|
|
stp <= sw01 after 1 ns;
|
| 415 |
|
|
|
| 416 |
|
|
when sw01 => --- Запись 4 кБ ---
|
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
write_state <= '1' after 1 ns;
|
| 420 |
|
|
|
| 421 |
|
|
|
| 422 |
|
|
fifo_sof <= '0' after 1 ns;
|
| 423 |
|
|
fifo_eof <= '1' after 1 ns;
|
| 424 |
|
|
fifo_rrem <= adr64 after 1 ns;
|
| 425 |
|
|
fifo_data <= tlp_write_dw0 & tlp_write_dw1 after 1 ns;
|
| 426 |
|
|
fifo_wr <= '1' after 1 ns;
|
| 427 |
|
|
|
| 428 |
|
|
write_cnt_en <= '1' after 1 ns;
|
| 429 |
|
|
stp <= sw2 after 1 ns;
|
| 430 |
|
|
|
| 431 |
|
|
|
| 432 |
|
|
when sw2 =>
|
| 433 |
|
|
fifo_sof <= '1' after 1 ns;
|
| 434 |
|
|
if( adr64='1' ) then
|
| 435 |
|
|
fifo_data <= tlp_write_dw2 & tlp_write_dw3 after 1 ns;
|
| 436 |
|
|
else
|
| 437 |
|
|
fifo_data <= tlp_write_dw3 & tlp_write_data( 63 downto 32 ) after 1 ns;
|
| 438 |
|
|
end if;
|
| 439 |
|
|
|
| 440 |
|
|
stp <= sw3 after 1 ns;
|
| 441 |
|
|
|
| 442 |
|
|
when sw3 =>
|
| 443 |
|
|
if( adr64='1' ) then
|
| 444 |
|
|
fifo_data <= tlp_write_data after 1 ns;
|
| 445 |
|
|
else
|
| 446 |
|
|
fifo_data( 31 downto 0 ) <= tlp_write_data( 63 downto 32 ) after 1 ns;
|
| 447 |
|
|
fifo_data( 63 downto 32 ) <= tlp_write_data_z( 31 downto 0 ) after 1 ns;
|
| 448 |
|
|
end if;
|
| 449 |
|
|
|
| 450 |
|
|
|
| 451 |
|
|
fifo_wr <= '1' after 1 ns;
|
| 452 |
|
|
if( write_cnt_eq='1' ) then
|
| 453 |
|
|
stp <= sw5 after 1 ns;
|
| 454 |
|
|
-- elsif( fifo_paf='1' ) then
|
| 455 |
|
|
-- stp <= sw4 after 1 ns;
|
| 456 |
|
|
end if;
|
| 457 |
|
|
|
| 458 |
|
|
-- when sw4 =>
|
| 459 |
|
|
-- write_cnt_en <= '0' after 1 ns;
|
| 460 |
|
|
-- fifo_wr <= '0' after 1 ns;
|
| 461 |
|
|
-- if( fifo_paf='0' ) then
|
| 462 |
|
|
-- stp <= sw3 after 1 ns;
|
| 463 |
|
|
-- end if;
|
| 464 |
|
|
|
| 465 |
|
|
when sw5 =>
|
| 466 |
|
|
if( adr64='1' ) then
|
| 467 |
|
|
fifo_data <= tlp_write_data after 1 ns;
|
| 468 |
|
|
else
|
| 469 |
|
|
fifo_data( 31 downto 0 ) <= tlp_write_data( 63 downto 32 ) after 1 ns;
|
| 470 |
|
|
fifo_data( 63 downto 32 ) <= tlp_write_data_z( 31 downto 0 ) after 1 ns;
|
| 471 |
|
|
end if;
|
| 472 |
|
|
|
| 473 |
|
|
fifo_eof <= '0' after 1 ns;
|
| 474 |
|
|
write_cnt_en <= '0' after 1 ns;
|
| 475 |
|
|
if( write_cnt_pkg_eq='1' ) then
|
| 476 |
|
|
stp <= sw6 after 1 ns;
|
| 477 |
|
|
else
|
| 478 |
|
|
stp <= s0 after 1 ns;
|
| 479 |
|
|
end if;
|
| 480 |
|
|
|
| 481 |
|
|
when sw6 =>
|
| 482 |
|
|
fifo_wr <= '0' after 1 ns;
|
| 483 |
|
|
tx_ext_fifo.complete_ok <= '1' after 1 ns;
|
| 484 |
|
|
tx_ext_fifo.complete_error <= '0' after 1 ns;
|
| 485 |
|
|
write_state <= '0' after 1 ns;
|
| 486 |
|
|
if( tx_ext_fifo_back.req_wr='0' ) then
|
| 487 |
|
|
stp <= s0 after 1 ns;
|
| 488 |
|
|
end if;
|
| 489 |
|
|
|
| 490 |
|
|
|
| 491 |
|
|
|
| 492 |
|
|
|
| 493 |
|
|
|
| 494 |
|
|
end case;
|
| 495 |
|
|
|
| 496 |
|
|
|
| 497 |
|
|
|
| 498 |
|
|
|
| 499 |
|
|
|
| 500 |
|
|
if( rstpz='1' ) then
|
| 501 |
|
|
stp <= s0 after 1 ns;
|
| 502 |
|
|
wait_complete <= '0' after 1 ns;
|
| 503 |
|
|
write_state <= '0' after 1 ns;
|
| 504 |
|
|
end if;
|
| 505 |
|
|
|
| 506 |
|
|
end if;
|
| 507 |
|
|
end process;
|
| 508 |
|
|
|
| 509 |
|
|
|
| 510 |
|
|
tlp_dw0 <= "0" & rx_tx_engine.request_reg_rd & "0010100" & rx_tx_engine.request_tc & "0000" & rx_tx_engine.request_attr & "0000" & "0000000" & rx_tx_engine.request_reg_rd;
|
| 511 |
|
|
tlp_dw1 <= completer_id & cpl_status & '0' & cpl_byte_count;
|
| 512 |
|
|
tlp_dw2 <= rx_tx_engine.request_id & rx_tx_engine.request_tag & '0' & rx_tx_engine.lower_adr & "00";
|
| 513 |
|
|
|
| 514 |
|
|
--cpl_byte_count <= "0000" & "0000" & "0" & rx_tx_engine.request_reg_rd & "00";
|
| 515 |
|
|
cpl_byte_count <= "0000" & "0000" & "0" & rx_tx_engine.byte_count;
|
| 516 |
|
|
|
| 517 |
|
|
reg_data <= reg_access_back.data after 1 ns when rising_edge( clk ) and reg_access_back.data_we='1';
|
| 518 |
|
|
tlp_dw3( 7 downto 0 ) <= reg_data( 31 downto 24 );
|
| 519 |
|
|
tlp_dw3( 15 downto 8 ) <= reg_data( 23 downto 16 );
|
| 520 |
|
|
tlp_dw3( 23 downto 16 ) <= reg_data( 15 downto 8 );
|
| 521 |
|
|
tlp_dw3( 31 downto 24 ) <= reg_data( 7 downto 0 );
|
| 522 |
|
|
|
| 523 |
|
|
max_read_size <= x"20"; -- 128 байт
|
| 524 |
|
|
read_tag <= "000" & req_cnt( 4 downto 0 );
|
| 525 |
|
|
|
| 526 |
|
|
adr64 <= tx_ext_fifo_back.pci_adr( 39 ) or
|
| 527 |
|
|
tx_ext_fifo_back.pci_adr( 38 ) or
|
| 528 |
|
|
tx_ext_fifo_back.pci_adr( 37 ) or
|
| 529 |
|
|
tx_ext_fifo_back.pci_adr( 36 ) or
|
| 530 |
|
|
tx_ext_fifo_back.pci_adr( 35 ) or
|
| 531 |
|
|
tx_ext_fifo_back.pci_adr( 34 ) or
|
| 532 |
|
|
tx_ext_fifo_back.pci_adr( 33 ) or
|
| 533 |
|
|
tx_ext_fifo_back.pci_adr( 32 );
|
| 534 |
|
|
|
| 535 |
|
|
tlp_read_dw0 <= "00" & adr64 & '0' & x"000" & "00000000" & max_read_size;
|
| 536 |
|
|
tlp_read_dw1 <= completer_id & read_tag & x"FF";
|
| 537 |
|
|
tlp_read_dw2 <= x"000000" & tx_ext_fifo_back.pci_adr( 39 downto 32 );
|
| 538 |
|
|
tlp_read_dw3( 6 downto 0 ) <= "0000000";
|
| 539 |
|
|
tlp_read_dw3( 8 downto 7 ) <= req_cnt( 1 downto 0 );
|
| 540 |
|
|
tlp_read_dw3( 11 downto 9 ) <= req_cnt( 4 downto 2 ) when tx_ext_fifo_back.rd_size='1'
|
| 541 |
|
|
else tx_ext_fifo_back.pci_adr( 11 downto 9 );
|
| 542 |
|
|
|
| 543 |
|
|
tlp_read_dw3( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 );
|
| 544 |
|
|
|
| 545 |
|
|
|
| 546 |
|
|
--tlp_read_dw0 <= x"0000" & "00000000" & max_read_size;
|
| 547 |
|
|
--tlp_read_dw1 <= completer_id & read_tag & x"FF";
|
| 548 |
|
|
--
|
| 549 |
|
|
--tlp_read_dw2( 6 downto 0 ) <= "0000000";
|
| 550 |
|
|
--tlp_read_dw2( 8 downto 7 ) <= req_cnt( 1 downto 0 );
|
| 551 |
|
|
--tlp_read_dw2( 11 downto 9 ) <= req_cnt( 4 downto 2 ) when tx_ext_fifo_back.rd_size='1'
|
| 552 |
|
|
-- else tx_ext_fifo_back.pci_adr( 11 downto 9 );
|
| 553 |
|
|
--
|
| 554 |
|
|
--tlp_read_dw2( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 );
|
| 555 |
|
|
--
|
| 556 |
|
|
--tlp_read_dw3 <= (others=>'0');
|
| 557 |
|
|
|
| 558 |
|
|
|
| 559 |
|
|
|
| 560 |
|
|
pr_req_cnt: process( clk ) begin
|
| 561 |
|
|
if( rising_edge( clk ) ) then
|
| 562 |
|
|
if( stp=s0 and wait_complete='0' ) then
|
| 563 |
|
|
req_cnt <= (others=>'0') after 1 ns;
|
| 564 |
|
|
elsif( stp=sr3 ) then
|
| 565 |
|
|
req_cnt <= req_cnt + 1 after 1 ns;
|
| 566 |
|
|
end if;
|
| 567 |
|
|
end if;
|
| 568 |
|
|
end process;
|
| 569 |
|
|
|
| 570 |
|
|
|
| 571 |
|
|
|
| 572 |
|
|
rstpz1 <= rstpz after 1 ns when rising_edge( clk );
|
| 573 |
|
|
timeout_st0 <= ( not rstpz ) and (rstpz1 or timeout_cnt_en ) after 1 ns when rising_edge( clk );
|
| 574 |
|
|
|
| 575 |
|
|
xtcnt: srlc32e port map( q31=>timeout_cnt_en, clk=>clk, d=>timeout_st0, a=>"11111", ce=>'1' );
|
| 576 |
|
|
|
| 577 |
|
|
pr_timeout_cnt: process( clk ) begin
|
| 578 |
|
|
if( rising_edge( clk ) ) then
|
| 579 |
|
|
if( wait_complete='0' ) then
|
| 580 |
|
|
timeout_cnt <= (others=>'0') after 1 ns;
|
| 581 |
|
|
elsif( timeout_cnt_en='1' ) then
|
| 582 |
|
|
timeout_cnt <= timeout_cnt + 1 after 1 ns;
|
| 583 |
|
|
end if;
|
| 584 |
|
|
end if;
|
| 585 |
|
|
end process;
|
| 586 |
|
|
|
| 587 |
|
|
timeout_error <= timeout_cnt(10);
|
| 588 |
|
|
|
| 589 |
|
|
pr_complete_cnt: process( clk ) begin
|
| 590 |
|
|
if( rising_edge( clk ) ) then
|
| 591 |
|
|
if( wait_complete='0' ) then
|
| 592 |
|
|
if( tx_ext_fifo_back.rd_size='0' ) then
|
| 593 |
|
|
complete_cnt <= "0111000000" after 1 ns; -- 513-64 -- ожидается 512 байт
|
| 594 |
|
|
else
|
| 595 |
|
|
complete_cnt <= "0000000000" after 1 ns; -- ожидается 4096 байт (512 слов по 8 байт)
|
| 596 |
|
|
end if;
|
| 597 |
|
|
elsif( rx_tx_engine.complete_we='1' ) then
|
| 598 |
|
|
complete_cnt <= complete_cnt + 1 after 1 ns;
|
| 599 |
|
|
end if;
|
| 600 |
|
|
end if;
|
| 601 |
|
|
end process;
|
| 602 |
|
|
|
| 603 |
|
|
req_complete <= complete_cnt(9);
|
| 604 |
|
|
|
| 605 |
|
|
write_size <= trn_tx_back.cfg_dcommand(5);
|
| 606 |
|
|
|
| 607 |
|
|
pr_write_cnt: process( clk ) begin
|
| 608 |
|
|
if( rising_edge( clk ) ) then
|
| 609 |
|
|
if( stp=s0 ) then
|
| 610 |
|
|
write_cnt <= '0' & not write_size & "000" & adr64 after 1 ns;
|
| 611 |
|
|
elsif( write_cnt_en='1' ) then
|
| 612 |
|
|
write_cnt <= write_cnt + 1 after 1 ns;
|
| 613 |
|
|
end if;
|
| 614 |
|
|
end if;
|
| 615 |
|
|
end process;
|
| 616 |
|
|
|
| 617 |
|
|
write_cnt_eq <= write_cnt(5);
|
| 618 |
|
|
|
| 619 |
|
|
write_cnt_pkg_add <= write_size & not write_size;
|
| 620 |
|
|
|
| 621 |
|
|
pr_write_cnt_pkg: process( clk ) begin
|
| 622 |
|
|
if( rising_edge( clk ) ) then
|
| 623 |
|
|
if( stp=s0 and write_state='0' ) then
|
| 624 |
|
|
write_cnt_pkg <= "00000" after 1 ns;
|
| 625 |
|
|
elsif( stp=sw5 ) then
|
| 626 |
|
|
write_cnt_pkg <= write_cnt_pkg + write_cnt_pkg_add after 1 ns;
|
| 627 |
|
|
end if;
|
| 628 |
|
|
end if;
|
| 629 |
|
|
end process;
|
| 630 |
|
|
|
| 631 |
|
|
write_cnt_pkg_eq <= write_cnt_pkg(4) and write_cnt_pkg(3) and write_cnt_pkg(2) and write_cnt_pkg(1) and (write_cnt_pkg(0) or write_size);
|
| 632 |
|
|
|
| 633 |
|
|
|
| 634 |
|
|
tlp_write_dw0 <= "01" & adr64 & '0' & x"000" & "00000000" & "0" & write_size & not write_size & "00000";
|
| 635 |
|
|
tlp_write_dw1 <= tlp_read_dw1;
|
| 636 |
|
|
tlp_write_dw2 <= tlp_read_dw2; --x"000000" & tx_ext_fifo_back.pci_adr( 39 downto 32 );
|
| 637 |
|
|
tlp_write_dw3( 6 downto 0 ) <= "0000000";
|
| 638 |
|
|
tlp_write_dw3( 11 downto 7 ) <= write_cnt_pkg( 4 downto 0 );
|
| 639 |
|
|
tlp_write_dw3( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 );
|
| 640 |
|
|
|
| 641 |
|
|
tlp_irq_dw0 <= "00110100" & x"00" & x"00" & x"00";
|
| 642 |
|
|
tlp_irq_dw1 <= completer_id( 15 downto 3 ) & "000" & x"00" & "00100" & cfg_interrupt_assert & interrupt_number;
|
| 643 |
|
|
tlp_irq_dw2 <= (others=>'0');
|
| 644 |
|
|
tlp_irq_dw3 <= (others=>'0');
|
| 645 |
|
|
|
| 646 |
|
|
--tlp_write_data <= x"00000000" & x"0000" & "0000000000" & write_cnt;
|
| 647 |
|
|
gen_repack: for ii in 0 to 7 generate
|
| 648 |
|
|
tlp_write_data( ii*8+7 downto ii*8 ) <= tx_ext_fifo_back.data( (7-ii)*8+7 downto (7-ii)*8 );
|
| 649 |
|
|
end generate;
|
| 650 |
|
|
|
| 651 |
|
|
tlp_write_data_z <= tlp_write_data( 31 downto 0 ) after 1 ns when rising_edge( clk );
|
| 652 |
|
|
|
| 653 |
|
|
pr_adr_cnt: process( clk ) begin
|
| 654 |
|
|
if( rising_edge( clk ) ) then
|
| 655 |
|
|
if( write_cnt_en='0' ) then
|
| 656 |
|
|
adr_cnt <= (others=>'0') after 1 ns;
|
| 657 |
|
|
else
|
| 658 |
|
|
adr_cnt <= adr_cnt + 1 after 1 ns;
|
| 659 |
|
|
end if;
|
| 660 |
|
|
end if;
|
| 661 |
|
|
end process;
|
| 662 |
|
|
|
| 663 |
|
|
tx_ext_fifo.adr( 3 downto 0 ) <= adr_cnt( 3 downto 0 );
|
| 664 |
|
|
tx_ext_fifo.adr( 4 ) <= adr_cnt(4) or write_cnt_pkg(0);
|
| 665 |
|
|
tx_ext_fifo.adr( 8 downto 5 ) <= write_cnt_pkg( 4 downto 1 );
|
| 666 |
|
|
|
| 667 |
|
|
|
| 668 |
|
|
trn_tx.fc_sel <= "000";
|
| 669 |
|
|
trn_tx.tx_cfg_gnt <= '1';
|
| 670 |
|
|
--trn_tx.s_axis_tx_tvalid <= '0';
|
| 671 |
|
|
--
|
| 672 |
|
|
--trn_tx.s_axis_tx_tstrb <= (others=>'0');
|
| 673 |
|
|
--trn_tx.s_axis_tx_tuser <= (others=>'0');
|
| 674 |
|
|
--trn_tx.s_axis_tx_tlast <= '0';
|
| 675 |
|
|
|
| 676 |
|
|
end core64_tx_engine_m2;
|
