URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_fifo_ext/] [ctrl_dma_adr.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
--
-- Title       : ctrl_dma_adr
-- Author      : Dmitry Smekhov
-- Company     : Instrumental Systems
-- E-mail      : dsmv@insys.ru
--
-- Version     : 1.2
--
-------------------------------------------------------------------------------
--
-- Description :   ���� ������������ ������ � ������� ��� ������� ��������
--
-------------------------------------------------------------------------------
--
--  Version 1.2  21.01.2011
--                               ����� �������� �� 40 ��������
--
-------------------------------------------------------------------------------
--
--  Version 1.1  05.04.2010
--                               �������� �������� is_dsp48 - ���������� �������������
--                               ������ DSP48
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.all;
 
 
package ctrl_dma_adr_pkg is
 
component ctrl_dma_adr is
        generic(
                is_dsp48                : in integer:=1         -- 1 - ������������ DSP48, 0 - �� ������������ DSP48
        );
        port(
                ---- Global ----
                clk                             : in std_logic; -- �������� �������
 
                ---- ������ � PICOBLAZE ----
                dma_chn                 : in std_logic;                                                 -- ����� ������ DMA       
                reg0                    : in std_logic_vector( 2 downto 0 );     -- ������� DMA_CTRL
                reg41_wr                : in std_logic;                                                 -- 1 - ������ � ������� 41
 
                ---- CTRL_EXT_DESCRIPTOR ----
                dsc_adr                 : in std_logic_vector( 23 downto 0 );    -- �����, ����� 3..1
                dsc_adr_h               : in std_logic_vector(  7 downto 0 );    -- �����, ���� 4
                dsc_size                : in std_logic_vector( 23 downto 0 );    -- ������, ����� 3..1 
                                                                                                                                -- ������ 0 ���������� ����������� ������, 0-������, 1-������
 
                ---- ����� ----
                pci_adr                 : out std_logic_vector( 39 downto 0 );   -- ������� ����� 
                pci_size_z              : out std_logic;                                                -- 1 - ������ ����� 0
                pci_rw                  : out std_logic                                                 -- 0 - ������, 1 - ������       
 
        );
end component;
 
end package;
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library unisim;
use unisim.vcomponents.all;
 
 
entity ctrl_dma_adr is
        generic(
                is_dsp48                : in integer:=1         -- 1 - ������������ DSP48, 0 - �� ������������ DSP48
        );
        port(
                ---- Global ----
                clk                             : in std_logic; -- �������� �������
 
                ---- ������ � PICOBLAZE ----
                dma_chn                 : in std_logic;                                                 -- ����� ������ DMA       
                reg0                    : in std_logic_vector( 2 downto 0 );     -- ������� DMA_CTRL
                reg41_wr                : in std_logic;                                                 -- 1 - ������ � ������� 41
 
                ---- CTRL_EXT_DESCRIPTOR ----
                dsc_adr                 : in std_logic_vector( 23 downto 0 );    -- �����, ����� 3..1
                dsc_adr_h               : in std_logic_vector(  7 downto 0 );    -- �����, ���� 4
                dsc_size                : in std_logic_vector( 23 downto 0 );    -- ������, ����� 3..1
 
                ---- ����� ----
                pci_adr                 : out std_logic_vector( 39 downto 0 );   -- ������� ����� 
                pci_size_z              : out std_logic;                                                -- 1 - ������ ����� 0
                pci_rw                  : out std_logic                                                 -- 0 - ������, 1 - ������       
 
        );
end ctrl_dma_adr;
 
 
architecture ctrl_dma_adr of ctrl_dma_adr is
 
 
signal  port_a0         : std_logic_vector( 17 downto 0 );
signal  port_b0         : std_logic_vector( 17 downto 0 );
signal  port_c0         : std_logic_vector( 47 downto 0 );
signal  port_p0         : std_logic_vector( 47 downto 0 );
signal  opmode          : std_logic_vector( 6 downto 0 );
signal  carry0          : std_logic;
 
 
signal  port_a1         : std_logic_vector( 17 downto 0 );
signal  port_b1         : std_logic_vector( 17 downto 0 );
signal  port_c1         : std_logic_vector( 47 downto 0 );
signal  port_p1         : std_logic_vector( 47 downto 0 );
signal  carry1          : std_logic;
signal  subtract1       : std_logic;
 
signal  p2                      : std_logic;
signal  n2                      : std_logic;
 
signal  reg410_wr       : std_logic;
 
signal  adr_low         : std_logic_vector( 2 downto 0 );
 
begin
 
p2 <= reg0(2);
n2 <= not reg0(2);
 
-- reg0(2)=1 - ��������� ������: opmode=0x30 carry=1
-- reg0(2)=0 - ������ ������ �� �����������: opmode=0x03 carry=0
opmode  <= '0' & p2 & p2 & "00" & n2 & n2;
carry0  <= p2;
carry1  <= p2;
subtract1 <= p2;
 
port_b0 <= dsc_adr( 21 downto 4 );
port_a0 <= x"00" & dsc_adr_h & dsc_adr( 23 downto 22 );
 
--port_c0 <= port_p0;
--port_c1 <= port_p1;
 
port_b1 <= dsc_size( 21 downto 4 );
port_a1 <= "00" & x"0000";
 
pci_adr( 8 downto 0 ) <= (others=>'0');
pci_adr( 11 downto 9 )  <= adr_low( 2 downto 0 );
pci_adr( 31 downto 12 ) <= port_c0( 19 downto 0 );
pci_adr( 39 downto 32 ) <= port_c0( 27 downto 20 );
 
gen_dsp48: if( is_dsp48=1 ) generate
 
dsp0: DSP48
  generic map(
 
        AREG            => 1,
        B_INPUT         => "DIRECT",
        BREG            => 1,
        CARRYINREG      => 1,
        CARRYINSELREG   => 1,
        CREG            => 1,
        LEGACY_MODE     => "MULT18X18S",
        MREG            => 1,
        OPMODEREG       => 1,
        PREG            => 1,
        SUBTRACTREG     => 1
        )
 
  port map(
        --BCOUT                   : out std_logic_vector(17 downto 0);
        P                       => port_p0,
        --PCOUT                   : out std_logic_vector(47 downto 0);
 
        A                       => port_a0,
        B                       => port_b0,
        BCIN                    => (others=>'0'),
        C                       => port_c0,
        CARRYIN                 => carry0,
        CARRYINSEL              => "00",
        CEA                     => '1',
        CEB                     => '1',
        CEC                     => '1',
        CECARRYIN               => '1',
        CECINSUB                => '1',
        CECTRL                  => '1',
        CEM                     => '1',
        CEP                     => '1',
        CLK                     => clk,
        OPMODE                  => opmode,
        PCIN                    => (others=>'0'),
        RSTA                    => '0',
        RSTB                    => '0',
        RSTC                    => '0',
        RSTCARRYIN              => '0',
        RSTCTRL                 => '0',
        RSTM                    => '0',
        RSTP                    => '0',
        SUBTRACT                => '0'
      );
 
 
 
dsp1: DSP48
  generic map(
 
        AREG            => 1,
        B_INPUT         => "DIRECT",
        BREG            => 1,
        CARRYINREG      => 1,
        CARRYINSELREG   => 1,
        CREG            => 1,
        LEGACY_MODE     => "MULT18X18S",
        MREG            => 1,
        OPMODEREG       => 1,
        PREG            => 1,
        SUBTRACTREG     => 1
        )
 
  port map(
        --BCOUT                   : out std_logic_vector(17 downto 0);
        P                       => port_p1,
        --PCOUT                   : out std_logic_vector(47 downto 0);
 
        A                       => port_a1,
        B                       => port_b1,
        BCIN                    => (others=>'0'),
        C                       => port_c1,
        CARRYIN                 => carry1,
        CARRYINSEL              => "00",
        CEA                     => '1',
        CEB                     => '1',
        CEC                     => '1',
        CECARRYIN               => '1',
        CECINSUB                => '1',
        CECTRL                  => '1',
        CEM                     => '1',
        CEP                     => '1',
        CLK                     => clk,
        OPMODE                  => opmode,
        PCIN                    => (others=>'0'),
        RSTA                    => '0',
        RSTB                    => '0',
        RSTC                    => '0',
        RSTCARRYIN              => '0',
        RSTCTRL                 => '0',
        RSTM                    => '0',
        RSTP                    => '0',
        SUBTRACT                => subtract1
      );
 
 
pci_size_z <= port_p1( 47 );
 
end generate;
 
gen_no_dsp48: if( is_dsp48=0 ) generate
 
pr_adr: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( p2='1' ) then
                        port_p0( 19 downto 0 ) <= port_c0( 19 downto 0 ) + 1 after 1 ns;
                else
                        port_p0( 19 downto 0 ) <= dsc_adr( 23 downto 4 ) after 1 ns;
                end if;
        end if;
end process;
 
 
pr_size: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( p2='1' ) then
                        port_p1( 18 downto 0 ) <= port_c1( 18 downto 0 ) - 1 after 1 ns;
                else
                        port_p1( 18 downto 0 ) <= '0' & dsc_size( 21 downto 4 ) after 1 ns;
                end if;
        end if;
end process;
 
pci_size_z <= port_p1( 18 );
 
end generate;
 
gen_ram: for ii in 0 to 27 generate
 
ram0:   ram16x1d
                port map(
                        we      => reg41_wr,
                        d       => port_p0(ii),
                        wclk => clk,
                        a0      => dma_chn,
                        a1      => '0',
                        a2      => '0',
                        a3      => '0',
                        spo     => port_c0(ii),
                        dpra0 => '0',
                        dpra1 => '0',
                        dpra2 => '0',
                        dpra3 => '1'
                );
 
ram1:   ram16x1d
                port map(
                        we      => reg41_wr,
                        d       => port_p1(ii),
                        wclk => clk,
                        a0      => dma_chn,
                        a1      => '0',
                        a2      => '0',
                        a3      => '0',
                        spo     => port_c1(ii),
                        dpra0 => '0',
                        dpra1 => '0',
                        dpra2 => '0',
                        dpra3 => '1'
                );
 
end generate;
 
port_c0( 47 downto 28 ) <= (others=>'0');
port_c1( 47 downto 28 ) <= (others=>'0');
 
 
 
 
reg410_wr <= reg41_wr and n2;
 
ram2:   ram16x1d
                port map(
                        we      => reg410_wr,
                        d       => dsc_size(0),
                        wclk => clk,
                        a0      => dma_chn,
                        a1      => '0',
                        a2      => '0',
                        a3      => '0',
                        spo     => pci_rw,
                        dpra0 => '0',
                        dpra1 => '0',
                        dpra2 => '0',
                        dpra3 => '1'
                );
 
 
 
gen_ram_low: for ii in 0 to 2 generate
 
ram_low:        ram16x1d
                port map(
                        we      => reg41_wr,
                        d       => dsc_adr(ii+1),
                        wclk => clk,
                        a0      => dma_chn,
                        a1      => '0',
                        a2      => '0',
                        a3      => '0',
                        spo     => adr_low(ii),
                        dpra0 => '0',
                        dpra1 => '0',
                        dpra2 => '0',
                        dpra3 => '1'
                );
 
 
end generate;
 
end ctrl_dma_adr;

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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_fifo_ext/] [ctrl_dma_adr.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dsmv	`-------------------------------------------------------------------------------`
2			`--`
3			`-- Title : ctrl_dma_adr`
4			`-- Author : Dmitry Smekhov`
5			`-- Company : Instrumental Systems`
6			`-- E-mail : dsmv@insys.ru`
7			`--`
8			`-- Version : 1.2`
9			`--`
10			`-------------------------------------------------------------------------------`
11			`--`
12			`-- Description : �� `
13			`--`
14			`-------------------------------------------------------------------------------`
15			`--`
16			`-- Version 1.2 21.01.2011`
17			`-- �� 40 ��`
18			`--`
19			`-------------------------------------------------------------------------------`
20			`--`
21			`-- Version 1.1 05.04.2010`
22			`-- �� is_dsp48 - �� `
23			`-- �� DSP48`
24			`--`
25			`-------------------------------------------------------------------------------`
26
27			`library ieee;`
28			`use ieee.std_logic_1164.all;`
29
30			`library unisim;`
31			`use unisim.vcomponents.all;`
32
33
34			`package ctrl_dma_adr_pkg is`
35
36			`component ctrl_dma_adr is`
37			`generic(`
38			`is_dsp48 : in integer:=1 -- 1 - �� DSP48, 0 - �� DSP48`
39			`);`
40			`port(`
41			`---- Global ----`
42			`clk : in std_logic; -- �� `
43
44			`---- �� PICOBLAZE ----`
45			`dma_chn : in std_logic; -- �� DMA`
46			`reg0 : in std_logic_vector( 2 downto 0 ); -- �� DMA_CTRL`
47			`reg41_wr : in std_logic; -- 1 - �� 41`
48
49			`---- CTRL_EXT_DESCRIPTOR ----`
50			`dsc_adr : in std_logic_vector( 23 downto 0 ); -- ��, �� 3..1`
51			`dsc_adr_h : in std_logic_vector( 7 downto 0 ); -- ��, �� 4`
52			`dsc_size : in std_logic_vector( 23 downto 0 ); -- ��, �� 3..1`
53			`-- �� 0 �� , 0-��, 1-��`
54
55			`---- �� ----`
56			`pci_adr : out std_logic_vector( 39 downto 0 ); -- �� `
57			`pci_size_z : out std_logic; -- 1 - �� 0`
58			`pci_rw : out std_logic -- 0 - ��, 1 - ��`
59
60			`);`
61			`end component;`
62
63			`end package;`
64
65
66			`library ieee;`
67			`use ieee.std_logic_1164.all;`
68			`use ieee.std_logic_arith.all;`
69			`use ieee.std_logic_unsigned.all;`
70
71			`library unisim;`
72			`use unisim.vcomponents.all;`
73
74
75			`entity ctrl_dma_adr is`
76			`generic(`
77			`is_dsp48 : in integer:=1 -- 1 - �� DSP48, 0 - �� DSP48`
78			`);`
79			`port(`
80			`---- Global ----`
81			`clk : in std_logic; -- �� `
82
83			`---- �� PICOBLAZE ----`
84			`dma_chn : in std_logic; -- �� DMA`
85			`reg0 : in std_logic_vector( 2 downto 0 ); -- �� DMA_CTRL`
86			`reg41_wr : in std_logic; -- 1 - �� 41`
87
88			`---- CTRL_EXT_DESCRIPTOR ----`
89			`dsc_adr : in std_logic_vector( 23 downto 0 ); -- ��, �� 3..1`
90			`dsc_adr_h : in std_logic_vector( 7 downto 0 ); -- ��, �� 4`
91			`dsc_size : in std_logic_vector( 23 downto 0 ); -- ��, �� 3..1`
92
93			`---- �� ----`
94			`pci_adr : out std_logic_vector( 39 downto 0 ); -- �� `
95			`pci_size_z : out std_logic; -- 1 - �� 0`
96			`pci_rw : out std_logic -- 0 - ��, 1 - ��`
97
98			`);`
99			`end ctrl_dma_adr;`
100
101
102			`architecture ctrl_dma_adr of ctrl_dma_adr is`
103
104
105			`signal port_a0 : std_logic_vector( 17 downto 0 );`
106			`signal port_b0 : std_logic_vector( 17 downto 0 );`
107			`signal port_c0 : std_logic_vector( 47 downto 0 );`
108			`signal port_p0 : std_logic_vector( 47 downto 0 );`
109			`signal opmode : std_logic_vector( 6 downto 0 );`
110			`signal carry0 : std_logic;`
111
112
113			`signal port_a1 : std_logic_vector( 17 downto 0 );`
114			`signal port_b1 : std_logic_vector( 17 downto 0 );`
115			`signal port_c1 : std_logic_vector( 47 downto 0 );`
116			`signal port_p1 : std_logic_vector( 47 downto 0 );`
117			`signal carry1 : std_logic;`
118			`signal subtract1 : std_logic;`
119
120			`signal p2 : std_logic;`
121			`signal n2 : std_logic;`
122
123			`signal reg410_wr : std_logic;`
124
125			`signal adr_low : std_logic_vector( 2 downto 0 );`
126
127			`begin`
128
129			`p2 <= reg0(2);`
130			`n2 <= not reg0(2);`
131
132			`-- reg0(2)=1 - �� : opmode=0x30 carry=1`
133			`-- reg0(2)=0 - �� : opmode=0x03 carry=0`
134			`opmode <= '0' & p2 & p2 & "00" & n2 & n2;`
135			`carry0 <= p2;`
136			`carry1 <= p2;`
137			`subtract1 <= p2;`
138
139			`port_b0 <= dsc_adr( 21 downto 4 );`
140			`port_a0 <= x"00" & dsc_adr_h & dsc_adr( 23 downto 22 );`
141
142			`--port_c0 <= port_p0;`
143			`--port_c1 <= port_p1;`
144
145			`port_b1 <= dsc_size( 21 downto 4 );`
146			`port_a1 <= "00" & x"0000";`
147
148			`pci_adr( 8 downto 0 ) <= (others=>'0');`
149			`pci_adr( 11 downto 9 ) <= adr_low( 2 downto 0 );`
150			`pci_adr( 31 downto 12 ) <= port_c0( 19 downto 0 );`
151			`pci_adr( 39 downto 32 ) <= port_c0( 27 downto 20 );`
152
153			`gen_dsp48: if( is_dsp48=1 ) generate`
154
155			`dsp0: DSP48`
156			`generic map(`
157
158			`AREG => 1,`
159			`B_INPUT => "DIRECT",`
160			`BREG => 1,`
161			`CARRYINREG => 1,`
162			`CARRYINSELREG => 1,`
163			`CREG => 1,`
164			`LEGACY_MODE => "MULT18X18S",`
165			`MREG => 1,`
166			`OPMODEREG => 1,`
167			`PREG => 1,`
168			`SUBTRACTREG => 1`
169			`)`
170
171			`port map(`
172			`--BCOUT : out std_logic_vector(17 downto 0);`
173			`P => port_p0,`
174			`--PCOUT : out std_logic_vector(47 downto 0);`
175
176			`A => port_a0,`
177			`B => port_b0,`
178			`BCIN => (others=>'0'),`
179			`C => port_c0,`
180			`CARRYIN => carry0,`
181			`CARRYINSEL => "00",`
182			`CEA => '1',`
183			`CEB => '1',`
184			`CEC => '1',`
185			`CECARRYIN => '1',`
186			`CECINSUB => '1',`
187			`CECTRL => '1',`
188			`CEM => '1',`
189			`CEP => '1',`
190			`CLK => clk,`
191			`OPMODE => opmode,`
192			`PCIN => (others=>'0'),`
193			`RSTA => '0',`
194			`RSTB => '0',`
195			`RSTC => '0',`
196			`RSTCARRYIN => '0',`
197			`RSTCTRL => '0',`
198			`RSTM => '0',`
199			`RSTP => '0',`
200			`SUBTRACT => '0'`
201			`);`
202
203
204
205			`dsp1: DSP48`
206			`generic map(`
207
208			`AREG => 1,`
209			`B_INPUT => "DIRECT",`
210			`BREG => 1,`
211			`CARRYINREG => 1,`
212			`CARRYINSELREG => 1,`
213			`CREG => 1,`
214			`LEGACY_MODE => "MULT18X18S",`
215			`MREG => 1,`
216			`OPMODEREG => 1,`
217			`PREG => 1,`
218			`SUBTRACTREG => 1`
219			`)`
220
221			`port map(`
222			`--BCOUT : out std_logic_vector(17 downto 0);`
223			`P => port_p1,`
224			`--PCOUT : out std_logic_vector(47 downto 0);`
225
226			`A => port_a1,`
227			`B => port_b1,`
228			`BCIN => (others=>'0'),`
229			`C => port_c1,`
230			`CARRYIN => carry1,`
231			`CARRYINSEL => "00",`
232			`CEA => '1',`
233			`CEB => '1',`
234			`CEC => '1',`
235			`CECARRYIN => '1',`
236			`CECINSUB => '1',`
237			`CECTRL => '1',`
238			`CEM => '1',`
239			`CEP => '1',`
240			`CLK => clk,`
241			`OPMODE => opmode,`
242			`PCIN => (others=>'0'),`
243			`RSTA => '0',`
244			`RSTB => '0',`
245			`RSTC => '0',`
246			`RSTCARRYIN => '0',`
247			`RSTCTRL => '0',`
248			`RSTM => '0',`
249			`RSTP => '0',`
250			`SUBTRACT => subtract1`
251			`);`
252
253
254			`pci_size_z <= port_p1( 47 );`
255
256			`end generate;`
257
258			`gen_no_dsp48: if( is_dsp48=0 ) generate`
259
260			`pr_adr: process( clk ) begin`
261			`if( rising_edge( clk ) ) then`
262			`if( p2='1' ) then`
263			`port_p0( 19 downto 0 ) <= port_c0( 19 downto 0 ) + 1 after 1 ns;`
264			`else`
265			`port_p0( 19 downto 0 ) <= dsc_adr( 23 downto 4 ) after 1 ns;`
266			`end if;`
267			`end if;`
268			`end process;`
269
270
271			`pr_size: process( clk ) begin`
272			`if( rising_edge( clk ) ) then`
273			`if( p2='1' ) then`
274			`port_p1( 18 downto 0 ) <= port_c1( 18 downto 0 ) - 1 after 1 ns;`
275			`else`
276			`port_p1( 18 downto 0 ) <= '0' & dsc_size( 21 downto 4 ) after 1 ns;`
277			`end if;`
278			`end if;`
279			`end process;`
280
281			`pci_size_z <= port_p1( 18 );`
282
283			`end generate;`
284
285			`gen_ram: for ii in 0 to 27 generate`
286
287			`ram0: ram16x1d`
288			`port map(`
289			`we => reg41_wr,`
290			`d => port_p0(ii),`
291			`wclk => clk,`
292			`a0 => dma_chn,`
293			`a1 => '0',`
294			`a2 => '0',`
295			`a3 => '0',`
296			`spo => port_c0(ii),`
297			`dpra0 => '0',`
298			`dpra1 => '0',`
299			`dpra2 => '0',`
300			`dpra3 => '1'`
301			`);`
302
303			`ram1: ram16x1d`
304			`port map(`
305			`we => reg41_wr,`
306			`d => port_p1(ii),`
307			`wclk => clk,`
308			`a0 => dma_chn,`
309			`a1 => '0',`
310			`a2 => '0',`
311			`a3 => '0',`
312			`spo => port_c1(ii),`
313			`dpra0 => '0',`
314			`dpra1 => '0',`
315			`dpra2 => '0',`
316			`dpra3 => '1'`
317			`);`
318
319			`end generate;`
320
321			`port_c0( 47 downto 28 ) <= (others=>'0');`
322			`port_c1( 47 downto 28 ) <= (others=>'0');`
323
324
325
326
327			`reg410_wr <= reg41_wr and n2;`
328
329			`ram2: ram16x1d`
330			`port map(`
331			`we => reg410_wr,`
332			`d => dsc_size(0),`
333			`wclk => clk,`
334			`a0 => dma_chn,`
335			`a1 => '0',`
336			`a2 => '0',`
337			`a3 => '0',`
338			`spo => pci_rw,`
339			`dpra0 => '0',`
340			`dpra1 => '0',`
341			`dpra2 => '0',`
342			`dpra3 => '1'`
343			`);`
344
345
346
347			`gen_ram_low: for ii in 0 to 2 generate`
348
349			`ram_low: ram16x1d`
350			`port map(`
351			`we => reg41_wr,`
352			`d => dsc_adr(ii+1),`
353			`wclk => clk,`
354			`a0 => dma_chn,`
355			`a1 => '0',`
356			`a2 => '0',`
357			`a3 => '0',`
358			`spo => adr_low(ii),`
359			`dpra0 => '0',`
360			`dpra1 => '0',`
361			`dpra2 => '0',`
362			`dpra3 => '1'`
363			`);`
364
365
366			`end generate;`
367
368			`end ctrl_dma_adr;`