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-------------------------------------------------------------------------------
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--
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-- Title : ctrl_ext_descriptor
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.5
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Память дескрипторов
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--
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-- Регистры для записи
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-- 0 - регистр управления
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-- 0: 1 - разрешение записи дескриптора
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-- 1: 1 - сброс адреса
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-- 2:
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-- 4 - Запись в регистр приводит к смене адреса
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-- 8 - регистр записи данных в память дескриптора
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-- последовательно записывается три байта адреса,
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-- которые помещаются по текущему адресу памяти.
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-- Первым записывается страший байт адреса.
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--
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--
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--
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-- Регистры для чтения
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-- 0 - DESCRIPTOR_CMD
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-- командное слово дескриптора
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--
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-- Поле регистра состояния:
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-- 0: 1 - блок дескрипторов правильный
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-- 1: 0 - наличие следующего дескриптора
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--
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.5 04.02.2012
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-- Исправлен подсчёт контрольной суммы при is_dsp48=0
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.4 14.12.2011
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-- Добавлены сигналы dsc_check_start, dsc_check_ready -
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-- для управления подсчётом контрольной суммы после
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-- чтения дескриптора
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--
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-------------------------------------------------------------------------------
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--
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-- Version : 1.3 26.01.2011
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-- Добавлена запись 40-битного начального адреса дескриптора
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--
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-------------------------------------------------------------------------------
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--
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-- Version : 1.2 05.04.2010
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-- Добавлен параметр is_dsp48 - разрешение использования
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-- блоков DSP48
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--
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-------------------------------------------------------------------------------
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--
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-- Version : 1.1 26.01.2010
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-- Используется 40-битный адрес на шине PCI
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package ctrl_ext_descriptor_pkg is
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component ctrl_ext_descriptor is
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generic(
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is_dsp48 : in integer:=1 -- 1 - использовать DSP48, 0 - не использовать DSP48
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);
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port(
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---- Global ----
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reset : in std_logic; -- 0 - сброс
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clk : in std_logic; -- тактовая частота
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---- Запись адреса ----
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data_in : in std_logic_vector( 31 downto 0 ); -- шина данных памяти
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pci_adr_we : in std_logic; -- 1 - запись адреса
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pci_adr_h_we : in std_logic; -- 1 - запись старших разрядов адреса
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---- ctrl_main ----
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dma_chn : in std_logic; -- номер канала DMA
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dsc_correct : out std_logic; -- 1 - загружен правильный дескриптор
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dsc_cmd : out std_logic_vector( 7 downto 0 ); -- командное слово дескриптора
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dsc_change_adr : in std_logic; -- 1 - смена адреса дескриптора
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dsc_change_mode : in std_logic; -- Режим изменения адреса:
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-- 0: - увеличение
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-- 1: - переход к нулевомй дескриптору
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dsc_load_en : in std_logic; -- 1 - разрешение записи дескриптора
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dsc_check_start : in std_logic; -- 1 - проверка дескриптора
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dsc_check_ready : out std_logic; -- 1 - проверка завершена
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---- ctrl_dma_ext_cmd ---
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ram0_wr : in std_logic; -- 1 - запись в память дескрипторов
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dma_wraddr : in std_logic_vector( 11 downto 0 ); -- адрес памяти
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dma_wrdata : in std_logic_vector( 63 downto 0 ); -- данные DMA
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dsc_adr_h : out std_logic_vector( 7 downto 0 ); -- адрес, байт 4
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dsc_adr : out std_logic_vector( 23 downto 0 ); -- адрес, байты 3..1
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dsc_size : out std_logic_vector( 23 downto 0 ); -- размер, байты 3..1
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---- Контрольные точки ----
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test : out std_logic_vector( 3 downto 0 )
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);
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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entity ctrl_ext_descriptor is
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generic(
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is_dsp48 : in integer:=1 -- 1 - использовать DSP48, 0 - не использовать DSP48
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);
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port(
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---- Global ----
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reset : in std_logic; -- 0 - сброс
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clk : in std_logic; -- тактовая частота
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---- Запись адреса ----
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data_in : in std_logic_vector( 31 downto 0 ); -- шина данных памяти
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pci_adr_we : in std_logic; -- 1 - запись адреса
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pci_adr_h_we : in std_logic; -- 1 - запись старших разрядов адреса
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---- ctrl_main ----
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dma_chn : in std_logic; -- номер канала DMA
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dsc_correct : out std_logic; -- 1 - загружен правильный дескриптор
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dsc_cmd : out std_logic_vector( 7 downto 0 ); -- командное слово дескриптора
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dsc_change_adr : in std_logic; -- 1 - смена адреса дескриптора
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dsc_change_mode : in std_logic; -- Режим изменения адреса:
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-- 0: - увеличение
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-- 1: - переход к нулевомй дескриптору
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dsc_load_en : in std_logic; -- 1 - разрешение записи дескриптора
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dsc_check_start : in std_logic; -- 1 - проверка дескриптора
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dsc_check_ready : out std_logic; -- 1 - проверка завершена
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---- ctrl_dma_ext_cmd ---
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ram0_wr : in std_logic; -- 1 - запись в память дескрипторов
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dma_wraddr : in std_logic_vector( 11 downto 0 ); -- адрес памяти
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dma_wrdata : in std_logic_vector( 63 downto 0 ); -- данные DMA
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dsc_adr_h : out std_logic_vector( 7 downto 0 ); -- адрес, байт 4
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dsc_adr : out std_logic_vector( 23 downto 0 ); -- адрес, байты 3..1
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dsc_size : out std_logic_vector( 23 downto 0 ); -- размер, байты 3..1
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---- Контрольные точки ----
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test : out std_logic_vector( 3 downto 0 )
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);
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end ctrl_ext_descriptor;
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architecture ctrl_ext_descriptor of ctrl_ext_descriptor is
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signal ram_a_out : std_logic_vector( 63 downto 0 );
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signal ram_a_out_x : std_logic_vector( 63 downto 0 );
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signal ram_a_in : std_logic_vector( 63 downto 0 );
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signal ram_a_adr : std_logic_vector( 8 downto 0 );
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signal ram_a_wr : std_logic;
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signal ram_b_wr : std_logic;
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signal ram_b_adr : std_logic_vector( 8 downto 0 );
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--signal reg0 : std_logic_vector( 7 downto 0 );
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--signal reg1 : std_logic_vector( 7 downto 0 );
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--signal reg2 : std_logic_vector( 7 downto 0 );
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signal reg_write : std_logic;
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signal status : std_logic_vector( 7 downto 0 );
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--signal reg84_wr : std_logic;
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--signal reg88_wr : std_logic;
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signal port_a : std_logic_vector( 17 downto 0 );
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signal port_b : std_logic_vector( 17 downto 0 );
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signal port_c : std_logic_vector( 47 downto 0 );
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signal port_p : std_logic_vector( 47 downto 0 );
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signal opmode : std_logic_vector( 6 downto 0 );
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signal carry : std_logic;
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signal reg_0 : std_logic_vector( 7 downto 0 );
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signal reg_1 : std_logic_vector( 7 downto 0 );
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signal reg_2 : std_logic_vector( 7 downto 0 );
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--signal reg_3 : std_logic_vector( 7 downto 0 );
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--signal reg_4 : std_logic_vector( 7 downto 0 );
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--signal reg_5 : std_logic_vector( 7 downto 0 );
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--signal reg_6 : std_logic_vector( 7 downto 0 );
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--signal reg_7 : std_logic_vector( 7 downto 0 );
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signal reg0_z : std_logic;
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signal crc_reset : std_logic;
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signal crc : std_logic_vector( 15 downto 0 );
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signal crc_z : std_logic;
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signal sig_error : std_logic;
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signal dma_descriptor_error : std_logic;
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signal dsc_change_adr_i : std_logic;
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signal crc_we : std_logic;
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signal crc_we_0 : std_logic;
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signal dsc_check_ready_i : std_logic;
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--signal crc_2 : std_logic_vector( 15 downto 0 );
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begin
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--reg0 <= reg_di after 1 ns when rising_edge( clk ) and reg_write='1' and reg_adr( 2 downto 0 )="000"; -- адрес памяти 0 --
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----reg1 <= reg_di after 1 ns when rising_edge( clk ) and reg_write='1' and reg_adr( 2 downto 0 )="001"; -- адрес памяти 1 --
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----reg2 <= reg_di after 1 ns when rising_edge( clk ) and reg_write='1' and reg_adr( 2 downto 0 )="010"; -- регистр управления --
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--
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--reg_write <= reg_wr and reg_adr(7) and not reg_adr(6); -- декодирование адресов 0x80-0x8F
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--
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--reg88_wr <= reg_write and reg_adr(3) after 1 ns; -- запись в регистр 88
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--
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--pr_reg_write: process( clk ) begin
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-- if( rising_edge( clk ) ) then
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-- reg84_wr <= reg_write and reg_adr(2) after 1 ns; -- запись в регистр 84
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-- end if;
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--end process;
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--
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--
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--reg_0 <= reg_di after 1 ns when rising_edge( clk ) and reg88_wr='1';
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--reg_1 <= reg_0 after 1 ns when rising_edge( clk ) and reg88_wr='1';
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--reg_2 <= reg_1 after 1 ns when rising_edge( clk ) and reg88_wr='1';
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--reg_3 <= reg_2 after 1 ns when rising_edge( clk ) and reg88_wr='1';
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--reg_4 <= reg_3 after 1 ns when rising_edge( clk ) and reg88_wr='1';
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--reg_5 <= reg_4 after 1 ns when rising_edge( clk ) and reg88_wr='1';
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--reg_6 <= reg_5 after 1 ns when rising_edge( clk ) and reg88_wr='1';
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--reg_7 <= reg_6 after 1 ns when rising_edge( clk ) and reg88_wr='1';
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--ram_a_in <= x"0000000000" & data_in( 31 downto 8 );
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ram_a_in( 63 downto 32 ) <= (others=>'0');
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ram_a_in( 31 downto 24 ) <= data_in( 7 downto 0 ) after 1 ns when rising_edge( clk ) and pci_adr_h_we='1';
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ram_a_in( 23 downto 0 ) <= data_in( 31 downto 8 );
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ram_a_wr <= pci_adr_we;
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ram_b_adr( 7 downto 0 ) <= dma_wraddr( 10 downto 3 );
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ram_b_adr( 8 ) <= dma_chn;
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ram_b_wr <= ram0_wr and dsc_load_en;
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ram_a_adr( 7 downto 0 ) <= port_c( 7 downto 0 );
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ram_a_adr( 8 ) <= dma_chn;
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dsc_adr_h <= ram_a_out( 31 downto 24 );
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dsc_adr <= ram_a_out( 23 downto 0 );
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dsc_size <= ram_a_out( 63 downto 40 );
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dsc_cmd <= ram_a_out( 39 downto 32 );
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dsc_correct <= dma_descriptor_error;
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ram0: RAMB16_S36_S36
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generic map(
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SIM_COLLISION_CHECK => "NONE"
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)
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port map(
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DOA => ram_a_out( 31 downto 0 ), --: out std_logic_vector(3 downto 0);
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--DOB => ram_b_out( 31 downto 0 ), --: out std_logic_vector(31 downto 0);
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--DOPB : out std_logic_vector(3 downto 0);
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ADDRA => ram_a_adr( 8 downto 0 ), --: in std_logic_vector(11 downto 0);
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ADDRB => ram_b_adr( 8 downto 0 ), --: in std_logic_vector(8 downto 0);
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CLKA => clk,
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CLKB => clk,
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DIA => ram_a_in( 31 downto 0 ), --: in std_logic_vector(3 downto 0);
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DIB => dma_wrdata( 31 downto 0 ), --: in std_logic_vector(31 downto 0);
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DIPA => (others=>'0'),
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DIPB => (others=>'0'),
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ENA => '1',
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ENB => '1',
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SSRA => '0',
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SSRB => '0',
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WEA => ram_a_wr,
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WEB => ram_b_wr
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);
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ram1: RAMB16_S36_S36
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generic map(
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SIM_COLLISION_CHECK => "NONE"
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)
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port map(
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DOA => ram_a_out( 63 downto 32 ), --: out std_logic_vector(3 downto 0);
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--DOB => ram_b_out( 31 downto 0 ), --: out std_logic_vector(31 downto 0);
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--DOPB : out std_logic_vector(3 downto 0);
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ADDRA => ram_a_adr( 8 downto 0 ), --: in std_logic_vector(11 downto 0);
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ADDRB => ram_b_adr( 8 downto 0 ), --: in std_logic_vector(8 downto 0);
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CLKA => clk,
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|
CLKB => clk,
|
308 |
|
|
DIA => ram_a_in( 63 downto 32 ), --: in std_logic_vector(3 downto 0);
|
309 |
|
|
DIB => dma_wrdata( 63 downto 32 ), --: in std_logic_vector(31 downto 0);
|
310 |
|
|
DIPA => (others=>'0'),
|
311 |
|
|
DIPB => (others=>'0'),
|
312 |
|
|
ENA => '1',
|
313 |
|
|
ENB => '1',
|
314 |
|
|
SSRA => '0',
|
315 |
|
|
SSRB => '0',
|
316 |
|
|
WEA => ram_a_wr,
|
317 |
|
|
WEB => ram_b_wr
|
318 |
|
|
);
|
319 |
|
|
|
320 |
|
|
ram_a_out_x <= ram_a_out after 1 ns;
|
321 |
|
|
|
322 |
|
|
|
323 |
|
|
|
324 |
|
|
|
325 |
|
|
--p1 <= reg2(1);
|
326 |
|
|
--n1 <= not reg2(1);
|
327 |
|
|
|
328 |
|
|
-- reg0(2)=1 - изменение адреса: opmode=0x30 carry=1
|
329 |
|
|
-- reg0(2)=0 - запись адреса из дескриптора: opmode=0x03 carry=0
|
330 |
|
|
--opmode <= '0' & p1 & p1 & "00" & n1 & n1;
|
331 |
|
|
--carry <= p1;
|
332 |
|
|
--opmode <= "0110000";
|
333 |
|
|
opmode <= '0' & not dsc_check_start & not dsc_check_start & "00" & dsc_check_start & '0';
|
334 |
|
|
carry <= '1';
|
335 |
|
|
|
336 |
|
|
port_b <= x"0000" & "00";
|
337 |
|
|
port_a <= x"0000" & "00";
|
338 |
|
|
|
339 |
|
|
|
340 |
|
|
gen_dsp48: if( is_dsp48=1 ) generate
|
341 |
|
|
|
342 |
|
|
dsp: DSP48
|
343 |
|
|
generic map(
|
344 |
|
|
|
345 |
|
|
AREG => 1,
|
346 |
|
|
B_INPUT => "DIRECT",
|
347 |
|
|
BREG => 1,
|
348 |
|
|
CARRYINREG => 1,
|
349 |
|
|
CARRYINSELREG => 1,
|
350 |
|
|
CREG => 1,
|
351 |
|
|
LEGACY_MODE => "MULT18X18S",
|
352 |
|
|
MREG => 1,
|
353 |
|
|
OPMODEREG => 1,
|
354 |
|
|
PREG => 1,
|
355 |
|
|
SUBTRACTREG => 1
|
356 |
|
|
)
|
357 |
|
|
|
358 |
|
|
port map(
|
359 |
|
|
--BCOUT : out std_logic_vector(17 downto 0);
|
360 |
|
|
P => port_p,
|
361 |
|
|
--PCOUT : out std_logic_vector(47 downto 0);
|
362 |
|
|
|
363 |
|
|
A => port_a,
|
364 |
|
|
B => port_b,
|
365 |
|
|
BCIN => (others=>'0'),
|
366 |
|
|
C => port_c,
|
367 |
|
|
CARRYIN => carry,
|
368 |
|
|
CARRYINSEL => "00",
|
369 |
|
|
CEA => '1',
|
370 |
|
|
CEB => '1',
|
371 |
|
|
CEC => '1',
|
372 |
|
|
CECARRYIN => '1',
|
373 |
|
|
CECINSUB => '1',
|
374 |
|
|
CECTRL => '1',
|
375 |
|
|
CEM => '1',
|
376 |
|
|
CEP => '1',
|
377 |
|
|
CLK => clk,
|
378 |
|
|
OPMODE => opmode,
|
379 |
|
|
PCIN => (others=>'0'),
|
380 |
|
|
RSTA => '0',
|
381 |
|
|
RSTB => '0',
|
382 |
|
|
RSTC => '0',
|
383 |
|
|
RSTCARRYIN => '0',
|
384 |
|
|
RSTCTRL => '0',
|
385 |
|
|
RSTM => '0',
|
386 |
|
|
RSTP => dsc_change_mode,
|
387 |
|
|
SUBTRACT => '0'
|
388 |
|
|
);
|
389 |
|
|
|
390 |
|
|
|
391 |
|
|
end generate;
|
392 |
|
|
|
393 |
|
|
gen_ndsp48: if( is_dsp48=0 ) generate
|
394 |
|
|
|
395 |
|
|
pr_dsp: process( clk ) begin
|
396 |
|
|
if( rising_edge( clk ) ) then
|
397 |
|
|
if( dsc_change_mode='1' ) then
|
398 |
|
|
port_p( 11 downto 0 ) <= (others=>'0') after 1 ns;
|
399 |
|
|
elsif( dsc_check_start='1' ) then
|
400 |
|
|
port_p( 11 downto 0 ) <= port_p( 11 downto 0 ) + 1 after 1 ns;
|
401 |
|
|
else
|
402 |
|
|
port_p( 11 downto 0 ) <= port_c( 11 downto 0 ) + 1 after 1 ns;
|
403 |
|
|
end if;
|
404 |
|
|
end if;
|
405 |
|
|
end process;
|
406 |
|
|
|
407 |
|
|
end generate;
|
408 |
|
|
|
409 |
|
|
gen_ram: for ii in 0 to 11 generate
|
410 |
|
|
|
411 |
|
|
ram_adr: ram16x1d
|
412 |
|
|
port map(
|
413 |
|
|
we => dsc_change_adr_i,
|
414 |
|
|
d => port_p(ii),
|
415 |
|
|
wclk => clk,
|
416 |
|
|
a0 => dma_chn,
|
417 |
|
|
a1 => '0',
|
418 |
|
|
a2 => '0',
|
419 |
|
|
a3 => '0',
|
420 |
|
|
spo => port_c(ii),
|
421 |
|
|
dpra0 => '0',
|
422 |
|
|
dpra1 => '0',
|
423 |
|
|
dpra2 => '0',
|
424 |
|
|
dpra3 => '1'
|
425 |
|
|
);
|
426 |
|
|
|
427 |
|
|
end generate;
|
428 |
|
|
|
429 |
|
|
port_c( 47 downto 12 ) <= (others=>'0');
|
430 |
|
|
|
431 |
|
|
reg0_z <= dsc_load_en after 1 ns when rising_edge( clk );
|
432 |
|
|
crc_reset <= '1' when dsc_load_en='1' and reg0_z='0' else '0';
|
433 |
|
|
|
434 |
|
|
---- Проверка дескриптора ----
|
435 |
|
|
pr_crc: process( clk )
|
436 |
|
|
|
437 |
|
|
variable v : std_logic_vector( 15 downto 0 );
|
438 |
|
|
|
439 |
|
|
begin
|
440 |
|
|
if( rising_edge( clk ) ) then
|
441 |
|
|
if( crc_reset='1' ) then
|
442 |
|
|
crc <= (others=>'1') after 1 ns;
|
443 |
|
|
elsif( crc_we='1' ) then
|
444 |
|
|
v := crc xor
|
445 |
|
|
ram_a_out_x( 15 downto 0 ) xor
|
446 |
|
|
ram_a_out_x( 31 downto 16 ) xor
|
447 |
|
|
ram_a_out_x( 47 downto 32 ) xor
|
448 |
|
|
ram_a_out_x( 63 downto 48 );
|
449 |
|
|
|
450 |
|
|
crc( 15 downto 1 ) <= v( 14 downto 0 ) after 1 ns;
|
451 |
|
|
crc( 0 ) <= not v( 15 ) after 1 ns;
|
452 |
|
|
end if;
|
453 |
|
|
end if;
|
454 |
|
|
end process;
|
455 |
|
|
|
456 |
|
|
|
457 |
|
|
------ Проверка дескриптора ----
|
458 |
|
|
--pr_crc2: process( clk )
|
459 |
|
|
--
|
460 |
|
|
--variable v : std_logic_vector( 15 downto 0 );
|
461 |
|
|
--
|
462 |
|
|
--begin
|
463 |
|
|
-- if( rising_edge( clk ) ) then
|
464 |
|
|
-- if( crc_reset='1' ) then
|
465 |
|
|
-- crc_2 <= (others=>'1') after 1 ns;
|
466 |
|
|
-- elsif( ram_b_wr='1' ) then
|
467 |
|
|
-- v := crc_2 xor
|
468 |
|
|
-- dma_wrdata( 15 downto 0 ) xor
|
469 |
|
|
-- dma_wrdata( 31 downto 16 ) xor
|
470 |
|
|
-- dma_wrdata( 47 downto 32 ) xor
|
471 |
|
|
-- dma_wrdata( 63 downto 48 );
|
472 |
|
|
--
|
473 |
|
|
-- crc_2( 15 downto 1 ) <= v( 14 downto 0 ) after 1 ns;
|
474 |
|
|
-- crc_2( 0 ) <= not v( 15 ) after 1 ns;
|
475 |
|
|
-- end if;
|
476 |
|
|
-- end if;
|
477 |
|
|
--end process;
|
478 |
|
|
|
479 |
|
|
crc_z <= '1' when crc=x"0001" else '0';
|
480 |
|
|
dma_descriptor_error <= not ( (not crc_z) or sig_error ) after 1 ns when rising_edge( clk );
|
481 |
|
|
|
482 |
|
|
pr_sig: process( clk ) begin
|
483 |
|
|
if( rising_edge( clk ) ) then
|
484 |
|
|
if( crc_we='1' ) then
|
485 |
|
|
if( ram_a_out( 47 downto 32 )=x"4953" ) then
|
486 |
|
|
sig_error <= '0' after 1 ns;
|
487 |
|
|
else
|
488 |
|
|
sig_error <= '1' after 1 ns;
|
489 |
|
|
end if;
|
490 |
|
|
end if;
|
491 |
|
|
end if;
|
492 |
|
|
end process;
|
493 |
|
|
|
494 |
|
|
|
495 |
|
|
pr_dsc_check_ready: process( clk ) begin
|
496 |
|
|
if( rising_edge( clk ) ) then
|
497 |
|
|
if( dsc_check_start='0' ) then
|
498 |
|
|
dsc_check_ready_i <= '0' after 1 ns;
|
499 |
|
|
elsif( port_p(6)='1' ) then
|
500 |
|
|
dsc_check_ready_i <= '1' after 1 ns;
|
501 |
|
|
end if;
|
502 |
|
|
end if;
|
503 |
|
|
end process;
|
504 |
|
|
|
505 |
|
|
xready: srl16 port map( q=>dsc_check_ready, clk=>clk, d=>dsc_check_ready_i, a3=>'0', a2=>'1', a1=>'0', a0=>'0' );
|
506 |
|
|
|
507 |
|
|
dsc_change_adr_i <= dsc_change_adr or dsc_check_start;
|
508 |
|
|
|
509 |
|
|
crc_we_0 <= dsc_check_start and not port_p(6) after 1 ns when rising_edge( clk );
|
510 |
|
|
crc_we <= crc_we_0 after 1 ns when rising_edge( clk );
|
511 |
|
|
|
512 |
|
|
--pr_crc_we: process( clk ) begin
|
513 |
|
|
-- if( rising_edge( clk ) ) then
|
514 |
|
|
-- if( dsc_check_start='0' ) then
|
515 |
|
|
-- crc_we <= '0' after 1 ns;
|
516 |
|
|
-- elsif( crc_we_0='1' ) then
|
517 |
|
|
-- crc_we <= not crc_we after 1 ns;
|
518 |
|
|
-- end if;
|
519 |
|
|
-- end if;
|
520 |
|
|
--end process;
|
521 |
|
|
|
522 |
|
|
end ctrl_ext_descriptor;
|