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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_fifo_ext/] [ctrl_ext_descriptor.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
--
-- Title       : ctrl_ext_descriptor
-- Author      : Dmitry Smekhov
-- Company     : Instrumental Systems
-- E-mail      : dsmv@insys.ru
--
-- Version     : 1.5
--
-------------------------------------------------------------------------------
--
-- Description :  ������ ������������      
--
--                                �������� ��� ������
--                                      0 - ������� ����������
--                                                      0: 1 - ���������� ������ �����������
--                                                      1: 1 - ����� ������
--                                                      2: 
--                                      4 - ������ � ������� �������� � ����� ������    
--                                      8 - ������� ������ ������ � ������ �����������
--                                              ��������������� ������������ ��� ����� ������,
--                                              ������� ���������� �� �������� ������ ������.
--                                              ������ ������������ ������� ���� ������.
--                                              
--                                                      
--
--                                �������� ��� ������
--                                      0 - DESCRIPTOR_CMD
--                                                      ��������� ����� �����������
--
--                                ���� �������� ���������:
--                                      0: 1 - ���� ������������ ����������
--                                      1: 0 - ������� ���������� �����������
--
--
-------------------------------------------------------------------------------
--
--  Version 1.5   04.02.2012
--                                ��������� ������� ����������� ����� ��� is_dsp48=0
--
-------------------------------------------------------------------------------
--
--  Version 1.4   14.12.2011
--                               ��������� ������� dsc_check_start, dsc_check_ready -
--                               ��� ���������� ��������� ����������� ����� ����� 
--                               ������ ����������� 
--
-------------------------------------------------------------------------------
--
--  Version  : 1.3  26.01.2011
--                               ��������� ������ 40-������� ���������� ������ �����������
--
-------------------------------------------------------------------------------
--
--  Version  : 1.2  05.04.2010
--                               �������� �������� is_dsp48 - ���������� �������������
--                               ������ DSP48
--
-------------------------------------------------------------------------------
--
--  Version  :  1.1   26.01.2010 
--              ������������ 40-������ ����� �� ���� PCI
--
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
 
package  ctrl_ext_descriptor_pkg is
 
component ctrl_ext_descriptor is
        generic(
                is_dsp48                : in integer:=1         -- 1 - ������������ DSP48, 0 - �� ������������ DSP48
        );
        port(
                ---- Global ----
                reset                           : in std_logic; -- 0 - �����
                clk                                     : in std_logic; -- �������� �������
 
                ---- ������ ������ ----
                data_in                         : in std_logic_vector( 31 downto 0 ); -- ���� ������ ������
                pci_adr_we                      : in std_logic; -- 1 - ������ ������
                pci_adr_h_we            : in std_logic; -- 1 - ������ ������� �������� ������
 
                ---- ctrl_main ----
                dma_chn                         : in  std_logic;        -- ����� ������ DMA
                dsc_correct                     : out std_logic;                -- 1 - �������� ���������� ����������
                dsc_cmd                         : out std_logic_vector( 7 downto 0 );    -- ��������� ����� �����������
                dsc_change_adr          : in  std_logic;        -- 1 - ����� ������ �����������
                dsc_change_mode         : in  std_logic;        -- ����� ��������� ������:
                                                                                                -- 0: - ����������
                                                        -- 1: - ������� � �������� �����������
                dsc_load_en                     : in  std_logic;        -- 1 - ���������� ������ �����������
                dsc_check_start         : in  std_logic;        -- 1 - �������� �����������
                dsc_check_ready         : out std_logic;        -- 1 - �������� ���������
 
                ---- ctrl_dma_ext_cmd ---
                ram0_wr                         : in std_logic; -- 1 - ������ � ������ ������������
                dma_wraddr                      : in std_logic_vector( 11 downto 0 );    -- ����� ������
                dma_wrdata                      : in std_logic_vector( 63 downto 0 );    -- ������ DMA
                dsc_adr_h                       : out std_logic_vector( 7 downto 0 );    -- �����, ���� 4
                dsc_adr                         : out std_logic_vector( 23 downto 0 );   -- �����, ����� 3..1
                dsc_size                        : out std_logic_vector( 23 downto 0 );   -- ������, ����� 3..1
 
                ---- ����������� ����� ----
                test                            : out std_logic_vector( 3 downto 0 )
 
 
        );
end component;
 
end package;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library unisim;
use unisim.vcomponents.all;
 
 
entity ctrl_ext_descriptor is
        generic(
                is_dsp48                : in integer:=1         -- 1 - ������������ DSP48, 0 - �� ������������ DSP48
        );
        port(
                ---- Global ----
                reset                           : in std_logic; -- 0 - �����
                clk                                     : in std_logic; -- �������� �������
 
                ---- ������ ������ ----
                data_in                         : in std_logic_vector( 31 downto 0 ); -- ���� ������ ������
                pci_adr_we                      : in std_logic; -- 1 - ������ ������
                pci_adr_h_we            : in std_logic; -- 1 - ������ ������� �������� ������
 
                ---- ctrl_main ----
                dma_chn                         : in  std_logic;        -- ����� ������ DMA
                dsc_correct                     : out std_logic;                -- 1 - �������� ���������� ����������
                dsc_cmd                         : out std_logic_vector( 7 downto 0 );    -- ��������� ����� �����������
                dsc_change_adr          : in  std_logic;        -- 1 - ����� ������ �����������
                dsc_change_mode         : in  std_logic;        -- ����� ��������� ������:
                                                                                                -- 0: - ����������
                                                        -- 1: - ������� � �������� �����������
                dsc_load_en                     : in  std_logic;        -- 1 - ���������� ������ �����������
                dsc_check_start         : in  std_logic;        -- 1 - �������� �����������
                dsc_check_ready         : out std_logic;        -- 1 - �������� ���������
 
                ---- ctrl_dma_ext_cmd ---
                ram0_wr                         : in std_logic; -- 1 - ������ � ������ ������������
                dma_wraddr                      : in std_logic_vector( 11 downto 0 );    -- ����� ������
                dma_wrdata                      : in std_logic_vector( 63 downto 0 );    -- ������ DMA
                dsc_adr_h                       : out std_logic_vector( 7 downto 0 );    -- �����, ���� 4
                dsc_adr                         : out std_logic_vector( 23 downto 0 );   -- �����, ����� 3..1
                dsc_size                        : out std_logic_vector( 23 downto 0 );   -- ������, ����� 3..1
 
                ---- ����������� ����� ----
                test                            : out std_logic_vector( 3 downto 0 )
 
 
        );
end ctrl_ext_descriptor;
 
 
architecture ctrl_ext_descriptor of ctrl_ext_descriptor is
 
signal          ram_a_out       : std_logic_vector( 63 downto 0 );
signal          ram_a_out_x     : std_logic_vector( 63 downto 0 );
signal          ram_a_in        : std_logic_vector( 63 downto 0 );
signal          ram_a_adr       : std_logic_vector( 8 downto 0 );
signal          ram_a_wr        : std_logic;
signal          ram_b_wr        : std_logic;
signal          ram_b_adr       : std_logic_vector( 8 downto 0 );
 
--signal        reg0                    : std_logic_vector( 7 downto 0 );
--signal        reg1                    : std_logic_vector( 7 downto 0 );
--signal        reg2                    : std_logic_vector( 7 downto 0 );
 
signal  reg_write               : std_logic;
 
signal  status                  : std_logic_vector( 7 downto 0 );
 
--signal        reg84_wr                : std_logic;
--signal        reg88_wr                : std_logic;
 
signal  port_a          : std_logic_vector( 17 downto 0 );
signal  port_b          : std_logic_vector( 17 downto 0 );
signal  port_c          : std_logic_vector( 47 downto 0 );
signal  port_p          : std_logic_vector( 47 downto 0 );
signal  opmode          : std_logic_vector( 6 downto 0 );
signal  carry           : std_logic;
 
signal  reg_0           : std_logic_vector( 7 downto 0 );
signal  reg_1           : std_logic_vector( 7 downto 0 );
signal  reg_2           : std_logic_vector( 7 downto 0 );
--signal        reg_3           : std_logic_vector( 7 downto 0 );
--signal        reg_4           : std_logic_vector( 7 downto 0 );
--signal        reg_5           : std_logic_vector( 7 downto 0 );
--signal        reg_6           : std_logic_vector( 7 downto 0 );
--signal        reg_7           : std_logic_vector( 7 downto 0 );
 
signal  reg0_z                                  : std_logic;
signal  crc_reset                               : std_logic;
signal  crc                                             : std_logic_vector( 15 downto 0 );
signal  crc_z                                   : std_logic;
signal  sig_error                               : std_logic;
signal  dma_descriptor_error    : std_logic;
 
signal  dsc_change_adr_i                : std_logic;
signal  crc_we                                  : std_logic;
signal  crc_we_0                                : std_logic;
 
signal  dsc_check_ready_i               : std_logic;
--signal        crc_2                                   : std_logic_vector( 15 downto 0 );
 
begin
 
 
--reg0 <= reg_di after 1 ns when rising_edge( clk ) and reg_write='1' and reg_adr( 2 downto 0 )="000"; -- ����� ������ 0 --
----reg1 <= reg_di after 1 ns when rising_edge( clk ) and reg_write='1' and reg_adr( 2 downto 0 )="001"; -- ����� ������ 1 --
----reg2 <= reg_di after 1 ns when rising_edge( clk ) and reg_write='1' and reg_adr( 2 downto 0 )="010"; -- ������� ���������� --
--
--reg_write <= reg_wr and  reg_adr(7) and not reg_adr(6); -- ������������� ������� 0x80-0x8F    
--
--reg88_wr <= reg_write and reg_adr(3) after 1 ns; -- ������ � ������� 88
--
--pr_reg_write: process( clk ) begin
--      if( rising_edge( clk ) ) then
--              reg84_wr <= reg_write and reg_adr(2) after 1 ns; -- ������ � ������� 84
--      end if;
--end process;
--
--
--reg_0 <= reg_di after 1 ns when rising_edge( clk ) and reg88_wr='1';
--reg_1 <= reg_0 after 1 ns when rising_edge( clk ) and reg88_wr='1';
--reg_2 <= reg_1 after 1 ns when rising_edge( clk ) and reg88_wr='1';
--reg_3 <= reg_2 after 1 ns when rising_edge( clk ) and reg88_wr='1';
--reg_4 <= reg_3 after 1 ns when rising_edge( clk ) and reg88_wr='1';
--reg_5 <= reg_4 after 1 ns when rising_edge( clk ) and reg88_wr='1';
--reg_6 <= reg_5 after 1 ns when rising_edge( clk ) and reg88_wr='1';
--reg_7 <= reg_6 after 1 ns when rising_edge( clk ) and reg88_wr='1';
 
--ram_a_in <= x"0000000000" & data_in( 31 downto 8 );
ram_a_in( 63 downto 32 ) <= (others=>'0');
ram_a_in( 31 downto 24 ) <= data_in( 7 downto 0 ) after 1 ns when rising_edge( clk ) and pci_adr_h_we='1';
ram_a_in( 23 downto 0 )  <= data_in( 31 downto 8 );
 
ram_a_wr <= pci_adr_we;
 
ram_b_adr( 7 downto 0 ) <= dma_wraddr( 10 downto 3 );
ram_b_adr( 8 ) <= dma_chn;
 
ram_b_wr <= ram0_wr and dsc_load_en;
 
ram_a_adr( 7 downto 0 ) <= port_c( 7 downto 0 );
ram_a_adr( 8 ) <= dma_chn;
 
dsc_adr_h  <= ram_a_out( 31 downto 24 );
dsc_adr  <= ram_a_out( 23 downto 0 );
dsc_size <= ram_a_out( 63 downto 40 );
 
dsc_cmd <= ram_a_out( 39 downto 32 );
 
dsc_correct <= dma_descriptor_error;
 
 
ram0: RAMB16_S36_S36
  generic map(
      SIM_COLLISION_CHECK => "NONE"
    )
 
  port map(
    DOA         => ram_a_out( 31 downto 0 ),  --: out std_logic_vector(3 downto 0);
    --DOB       => ram_b_out( 31 downto 0 ), --: out std_logic_vector(31 downto 0);
    --DOPB      : out std_logic_vector(3 downto 0);
 
    ADDRA       => ram_a_adr( 8 downto 0 ), --: in std_logic_vector(11 downto 0);
    ADDRB       => ram_b_adr( 8 downto 0 ),  --: in std_logic_vector(8 downto 0);
    CLKA        => clk,
    CLKB        => clk,
    DIA         => ram_a_in( 31 downto 0 ), --: in std_logic_vector(3 downto 0);
    DIB         => dma_wrdata( 31 downto 0 ), --: in std_logic_vector(31 downto 0);
    DIPA        => (others=>'0'),
    DIPB        => (others=>'0'),
    ENA         => '1',
    ENB         => '1',
    SSRA        => '0',
    SSRB        => '0',
    WEA         => ram_a_wr,
    WEB         => ram_b_wr
    );
 
ram1: RAMB16_S36_S36
  generic map(
      SIM_COLLISION_CHECK => "NONE"
    )
 
  port map(
    DOA         => ram_a_out( 63 downto 32 ),  --: out std_logic_vector(3 downto 0);
    --DOB       => ram_b_out( 31 downto 0 ), --: out std_logic_vector(31 downto 0);
    --DOPB      : out std_logic_vector(3 downto 0);
 
    ADDRA       => ram_a_adr( 8 downto 0 ), --: in std_logic_vector(11 downto 0);
    ADDRB       => ram_b_adr( 8 downto 0 ),  --: in std_logic_vector(8 downto 0);
    CLKA        => clk,
    CLKB        => clk,
    DIA         => ram_a_in( 63 downto 32 ), --: in std_logic_vector(3 downto 0);
    DIB         => dma_wrdata( 63 downto 32 ), --: in std_logic_vector(31 downto 0);
    DIPA        => (others=>'0'),
    DIPB        => (others=>'0'),
    ENA         => '1',
    ENB         => '1',
    SSRA        => '0',
    SSRB        => '0',
    WEA         => ram_a_wr,
    WEB         => ram_b_wr
    );
 
ram_a_out_x <= ram_a_out after 1 ns;
 
 
 
 
--p1 <= reg2(1);
--n1 <= not reg2(1);
 
-- reg0(2)=1 - ��������� ������: opmode=0x30 carry=1
-- reg0(2)=0 - ������ ������ �� �����������: opmode=0x03 carry=0
--opmode        <= '0' & p1 & p1 & "00" & n1 & n1;
--carry  <= p1;          
--opmode <= "0110000";
opmode <= '0' & not dsc_check_start & not dsc_check_start & "00" & dsc_check_start & '0';
carry <= '1';
 
port_b <= x"0000" & "00";
port_a <= x"0000" & "00";
 
 
gen_dsp48: if( is_dsp48=1 ) generate
 
dsp: DSP48
  generic map(
 
        AREG            => 1,
        B_INPUT         => "DIRECT",
        BREG            => 1,
        CARRYINREG      => 1,
        CARRYINSELREG   => 1,
        CREG            => 1,
        LEGACY_MODE     => "MULT18X18S",
        MREG            => 1,
        OPMODEREG       => 1,
        PREG            => 1,
        SUBTRACTREG     => 1
        )
 
  port map(
        --BCOUT                   : out std_logic_vector(17 downto 0);
        P                       => port_p,
        --PCOUT                   : out std_logic_vector(47 downto 0);
 
        A                       => port_a,
        B                       => port_b,
        BCIN                    => (others=>'0'),
        C                       => port_c,
        CARRYIN                 => carry,
        CARRYINSEL              => "00",
        CEA                     => '1',
        CEB                     => '1',
        CEC                     => '1',
        CECARRYIN               => '1',
        CECINSUB                => '1',
        CECTRL                  => '1',
        CEM                     => '1',
        CEP                     => '1',
        CLK                     => clk,
        OPMODE                  => opmode,
        PCIN                    => (others=>'0'),
        RSTA                    => '0',
        RSTB                    => '0',
        RSTC                    => '0',
        RSTCARRYIN              => '0',
        RSTCTRL                 => '0',
        RSTM                    => '0',
        RSTP                    => dsc_change_mode,
        SUBTRACT                => '0'
      );
 
 
end generate;
 
gen_ndsp48: if( is_dsp48=0 ) generate
 
pr_dsp: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( dsc_change_mode='1' ) then
                        port_p( 11 downto 0 ) <= (others=>'0') after 1 ns;
                elsif( dsc_check_start='1' ) then
                        port_p( 11 downto 0 ) <= port_p( 11 downto 0 ) + 1 after 1 ns;
                else
                        port_p( 11 downto 0 ) <= port_c( 11 downto 0 ) + 1 after 1 ns;
                end if;
        end if;
end process;
 
end generate;
 
gen_ram: for ii in 0 to 11 generate
 
ram_adr:        ram16x1d
                port map(
                        we      => dsc_change_adr_i,
                        d       => port_p(ii),
                        wclk => clk,
                        a0      => dma_chn,
                        a1      => '0',
                        a2      => '0',
                        a3      => '0',
                        spo     => port_c(ii),
                        dpra0 => '0',
                        dpra1 => '0',
                        dpra2 => '0',
                        dpra3 => '1'
                );
 
end generate;
 
port_c( 47 downto 12 ) <= (others=>'0');
 
reg0_z <= dsc_load_en after 1 ns when rising_edge( clk );
crc_reset <= '1' when dsc_load_en='1' and reg0_z='0' else '0';
 
---- �������� ����������� ----
pr_crc: process( clk )
 
variable        v       : std_logic_vector( 15 downto 0 );
 
begin
        if( rising_edge( clk ) ) then
                if( crc_reset='1' ) then
                        crc <= (others=>'1') after 1 ns;
                elsif( crc_we='1' ) then
                         v  :=  crc xor
                                        ram_a_out_x( 15 downto 0 )  xor
                                        ram_a_out_x( 31 downto 16 ) xor
                                        ram_a_out_x( 47 downto 32 ) xor
                                        ram_a_out_x( 63 downto 48 );
 
                        crc( 15 downto 1 ) <= v( 14 downto 0 ) after 1 ns;
                        crc( 0 ) <= not v( 15 ) after 1 ns;
                end if;
        end if;
end process;
 
 
------ �������� ����������� ----
--pr_crc2: process( clk ) 
--
--variable      v       : std_logic_vector( 15 downto 0 );
--
--begin
--      if( rising_edge( clk ) ) then
--              if( crc_reset='1' ) then
--                      crc_2 <= (others=>'1') after 1 ns;
--              elsif( ram_b_wr='1' ) then
--                       v  :=  crc_2 xor 
--                                      dma_wrdata( 15 downto 0 )  xor 
--                                      dma_wrdata( 31 downto 16 ) xor
--                                      dma_wrdata( 47 downto 32 ) xor
--                                      dma_wrdata( 63 downto 48 );
--                                      
--                      crc_2( 15 downto 1 ) <= v( 14 downto 0 ) after 1 ns;
--                      crc_2( 0 ) <= not v( 15 ) after 1 ns;
--              end if;
--      end if;
--end process;
 
crc_z <= '1' when crc=x"0001" else '0';
dma_descriptor_error <= not ( (not crc_z) or sig_error ) after 1 ns  when rising_edge( clk );
 
pr_sig: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( crc_we='1' ) then
                        if( ram_a_out( 47 downto 32 )=x"4953" ) then
                                sig_error <= '0' after 1 ns;
                        else
                                sig_error <= '1' after 1 ns;
                        end if;
                end if;
        end if;
end process;
 
 
pr_dsc_check_ready: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( dsc_check_start='0' ) then
                        dsc_check_ready_i <= '0' after 1 ns;
                elsif( port_p(6)='1' ) then
                        dsc_check_ready_i <= '1' after 1 ns;
                end if;
        end if;
end process;
 
xready: srl16 port map( q=>dsc_check_ready, clk=>clk, d=>dsc_check_ready_i, a3=>'0', a2=>'1', a1=>'0', a0=>'0' );
 
dsc_change_adr_i <= dsc_change_adr or dsc_check_start;
 
crc_we_0 <= dsc_check_start and not port_p(6) after 1 ns when rising_edge( clk );
crc_we <= crc_we_0 after 1 ns when rising_edge( clk );
 
--pr_crc_we: process( clk ) begin
--      if( rising_edge( clk ) ) then
--              if( dsc_check_start='0' ) then
--                      crc_we <= '0' after 1 ns;
--              elsif( crc_we_0='1' ) then
--                      crc_we <= not crc_we after 1 ns;
--              end if;
--      end if;
--end process;
 
end ctrl_ext_descriptor;

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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_fifo_ext/] [ctrl_ext_descriptor.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dsmv	`-------------------------------------------------------------------------------`
2			`--`
3			`-- Title : ctrl_ext_descriptor`
4			`-- Author : Dmitry Smekhov`
5			`-- Company : Instrumental Systems`
6			`-- E-mail : dsmv@insys.ru`
7			`--`
8			`-- Version : 1.5`
9			`--`
10			`-------------------------------------------------------------------------------`
11			`--`
12			`-- Description : �� `
13			`--`
14			`-- �� `
15			`-- 0 - �� `
16			`-- 0: 1 - �� `
17			`-- 1: 1 - �� `
18			`-- 2:`
19			`-- 4 - �� `
20			`-- 8 - �� `
21			`-- �� ,`
22			`-- �� .`
23			`-- �� .`
24			`--`
25			`--`
26			`--`
27			`-- �� `
28			`-- 0 - DESCRIPTOR_CMD`
29			`-- �� `
30			`--`
31			`-- �� :`
32			`-- 0: 1 - �� `
33			`-- 1: 0 - �� `
34			`--`
35			`--`
36			`-------------------------------------------------------------------------------`
37			`--`
38			`-- Version 1.5 04.02.2012`
39			`-- �� is_dsp48=0`
40			`--`
41			`-------------------------------------------------------------------------------`
42			`--`
43			`-- Version 1.4 14.12.2011`
44			`-- �� dsc_check_start, dsc_check_ready -`
45			`-- �� `
46			`-- �� `
47			`--`
48			`-------------------------------------------------------------------------------`
49			`--`
50			`-- Version : 1.3 26.01.2011`
51			`-- �� 40-�� `
52			`--`
53			`-------------------------------------------------------------------------------`
54			`--`
55			`-- Version : 1.2 05.04.2010`
56			`-- �� is_dsp48 - �� `
57			`-- �� DSP48`
58			`--`
59			`-------------------------------------------------------------------------------`
60			`--`
61			`-- Version : 1.1 26.01.2010`
62			`-- �� 40-�� PCI`
63			`--`
64			`-------------------------------------------------------------------------------`
65
66
67			`library ieee;`
68			`use ieee.std_logic_1164.all;`
69
70			`package ctrl_ext_descriptor_pkg is`
71
72			`component ctrl_ext_descriptor is`
73			`generic(`
74			`is_dsp48 : in integer:=1 -- 1 - �� DSP48, 0 - �� DSP48`
75			`);`
76			`port(`
77			`---- Global ----`
78			`reset : in std_logic; -- 0 - ��`
79			`clk : in std_logic; -- �� `
80
81			`---- �� ----`
82			`data_in : in std_logic_vector( 31 downto 0 ); -- �� `
83			`pci_adr_we : in std_logic; -- 1 - �� `
84			`pci_adr_h_we : in std_logic; -- 1 - �� `
85
86			`---- ctrl_main ----`
87			`dma_chn : in std_logic; -- �� DMA`
88			`dsc_correct : out std_logic; -- 1 - �� `
89			`dsc_cmd : out std_logic_vector( 7 downto 0 ); -- �� `
90			`dsc_change_adr : in std_logic; -- 1 - �� `
91			`dsc_change_mode : in std_logic; -- �� :`
92			`-- 0: - ��`
93			`-- 1: - �� `
94			`dsc_load_en : in std_logic; -- 1 - �� `
95			`dsc_check_start : in std_logic; -- 1 - �� `
96			`dsc_check_ready : out std_logic; -- 1 - �� `
97
98			`---- ctrl_dma_ext_cmd ---`
99			`ram0_wr : in std_logic; -- 1 - �� `
100			`dma_wraddr : in std_logic_vector( 11 downto 0 ); -- �� `
101			`dma_wrdata : in std_logic_vector( 63 downto 0 ); -- �� DMA`
102			`dsc_adr_h : out std_logic_vector( 7 downto 0 ); -- ��, �� 4`
103			`dsc_adr : out std_logic_vector( 23 downto 0 ); -- ��, �� 3..1`
104			`dsc_size : out std_logic_vector( 23 downto 0 ); -- ��, �� 3..1`
105
106			`---- �� ----`
107			`test : out std_logic_vector( 3 downto 0 )`
108
109
110			`);`
111			`end component;`
112
113			`end package;`
114
115			`library ieee;`
116			`use ieee.std_logic_1164.all;`
117			`use ieee.std_logic_arith.all;`
118			`use ieee.std_logic_unsigned.all;`
119
120			`library unisim;`
121			`use unisim.vcomponents.all;`
122
123
124			`entity ctrl_ext_descriptor is`
125			`generic(`
126			`is_dsp48 : in integer:=1 -- 1 - �� DSP48, 0 - �� DSP48`
127			`);`
128			`port(`
129			`---- Global ----`
130			`reset : in std_logic; -- 0 - ��`
131			`clk : in std_logic; -- �� `
132
133			`---- �� ----`
134			`data_in : in std_logic_vector( 31 downto 0 ); -- �� `
135			`pci_adr_we : in std_logic; -- 1 - �� `
136			`pci_adr_h_we : in std_logic; -- 1 - �� `
137
138			`---- ctrl_main ----`
139			`dma_chn : in std_logic; -- �� DMA`
140			`dsc_correct : out std_logic; -- 1 - �� `
141			`dsc_cmd : out std_logic_vector( 7 downto 0 ); -- �� `
142			`dsc_change_adr : in std_logic; -- 1 - �� `
143			`dsc_change_mode : in std_logic; -- �� :`
144			`-- 0: - ��`
145			`-- 1: - �� `
146			`dsc_load_en : in std_logic; -- 1 - �� `
147			`dsc_check_start : in std_logic; -- 1 - �� `
148			`dsc_check_ready : out std_logic; -- 1 - �� `
149
150			`---- ctrl_dma_ext_cmd ---`
151			`ram0_wr : in std_logic; -- 1 - �� `
152			`dma_wraddr : in std_logic_vector( 11 downto 0 ); -- �� `
153			`dma_wrdata : in std_logic_vector( 63 downto 0 ); -- �� DMA`
154			`dsc_adr_h : out std_logic_vector( 7 downto 0 ); -- ��, �� 4`
155			`dsc_adr : out std_logic_vector( 23 downto 0 ); -- ��, �� 3..1`
156			`dsc_size : out std_logic_vector( 23 downto 0 ); -- ��, �� 3..1`
157
158			`---- �� ----`
159			`test : out std_logic_vector( 3 downto 0 )`
160
161
162			`);`
163			`end ctrl_ext_descriptor;`
164
165
166			`architecture ctrl_ext_descriptor of ctrl_ext_descriptor is`
167
168			`signal ram_a_out : std_logic_vector( 63 downto 0 );`
169			`signal ram_a_out_x : std_logic_vector( 63 downto 0 );`
170			`signal ram_a_in : std_logic_vector( 63 downto 0 );`
171			`signal ram_a_adr : std_logic_vector( 8 downto 0 );`
172			`signal ram_a_wr : std_logic;`
173			`signal ram_b_wr : std_logic;`
174			`signal ram_b_adr : std_logic_vector( 8 downto 0 );`
175
176			`--signal reg0 : std_logic_vector( 7 downto 0 );`
177			`--signal reg1 : std_logic_vector( 7 downto 0 );`
178			`--signal reg2 : std_logic_vector( 7 downto 0 );`
179
180			`signal reg_write : std_logic;`
181
182			`signal status : std_logic_vector( 7 downto 0 );`
183
184			`--signal reg84_wr : std_logic;`
185			`--signal reg88_wr : std_logic;`
186
187			`signal port_a : std_logic_vector( 17 downto 0 );`
188			`signal port_b : std_logic_vector( 17 downto 0 );`
189			`signal port_c : std_logic_vector( 47 downto 0 );`
190			`signal port_p : std_logic_vector( 47 downto 0 );`
191			`signal opmode : std_logic_vector( 6 downto 0 );`
192			`signal carry : std_logic;`
193
194			`signal reg_0 : std_logic_vector( 7 downto 0 );`
195			`signal reg_1 : std_logic_vector( 7 downto 0 );`
196			`signal reg_2 : std_logic_vector( 7 downto 0 );`
197			`--signal reg_3 : std_logic_vector( 7 downto 0 );`
198			`--signal reg_4 : std_logic_vector( 7 downto 0 );`
199			`--signal reg_5 : std_logic_vector( 7 downto 0 );`
200			`--signal reg_6 : std_logic_vector( 7 downto 0 );`
201			`--signal reg_7 : std_logic_vector( 7 downto 0 );`
202
203			`signal reg0_z : std_logic;`
204			`signal crc_reset : std_logic;`
205			`signal crc : std_logic_vector( 15 downto 0 );`
206			`signal crc_z : std_logic;`
207			`signal sig_error : std_logic;`
208			`signal dma_descriptor_error : std_logic;`
209
210			`signal dsc_change_adr_i : std_logic;`
211			`signal crc_we : std_logic;`
212			`signal crc_we_0 : std_logic;`
213
214			`signal dsc_check_ready_i : std_logic;`
215			`--signal crc_2 : std_logic_vector( 15 downto 0 );`
216
217			`begin`
218
219
220			`--reg0 <= reg_di after 1 ns when rising_edge( clk ) and reg_write='1' and reg_adr( 2 downto 0 )="000"; -- �� 0 --`
221			`----reg1 <= reg_di after 1 ns when rising_edge( clk ) and reg_write='1' and reg_adr( 2 downto 0 )="001"; -- �� 1 --`
222			`----reg2 <= reg_di after 1 ns when rising_edge( clk ) and reg_write='1' and reg_adr( 2 downto 0 )="010"; -- �� --`
223			`--`
224			`--reg_write <= reg_wr and reg_adr(7) and not reg_adr(6); -- �� 0x80-0x8F`
225			`--`
226			`--reg88_wr <= reg_write and reg_adr(3) after 1 ns; -- �� 88`
227			`--`
228			`--pr_reg_write: process( clk ) begin`
229			`-- if( rising_edge( clk ) ) then`
230			`-- reg84_wr <= reg_write and reg_adr(2) after 1 ns; -- �� 84`
231			`-- end if;`
232			`--end process;`
233			`--`
234			`--`
235			`--reg_0 <= reg_di after 1 ns when rising_edge( clk ) and reg88_wr='1';`
236			`--reg_1 <= reg_0 after 1 ns when rising_edge( clk ) and reg88_wr='1';`
237			`--reg_2 <= reg_1 after 1 ns when rising_edge( clk ) and reg88_wr='1';`
238			`--reg_3 <= reg_2 after 1 ns when rising_edge( clk ) and reg88_wr='1';`
239			`--reg_4 <= reg_3 after 1 ns when rising_edge( clk ) and reg88_wr='1';`
240			`--reg_5 <= reg_4 after 1 ns when rising_edge( clk ) and reg88_wr='1';`
241			`--reg_6 <= reg_5 after 1 ns when rising_edge( clk ) and reg88_wr='1';`
242			`--reg_7 <= reg_6 after 1 ns when rising_edge( clk ) and reg88_wr='1';`
243
244			`--ram_a_in <= x"0000000000" & data_in( 31 downto 8 );`
245			`ram_a_in( 63 downto 32 ) <= (others=>'0');`
246			`ram_a_in( 31 downto 24 ) <= data_in( 7 downto 0 ) after 1 ns when rising_edge( clk ) and pci_adr_h_we='1';`
247			`ram_a_in( 23 downto 0 ) <= data_in( 31 downto 8 );`
248
249			`ram_a_wr <= pci_adr_we;`
250
251			`ram_b_adr( 7 downto 0 ) <= dma_wraddr( 10 downto 3 );`
252			`ram_b_adr( 8 ) <= dma_chn;`
253
254			`ram_b_wr <= ram0_wr and dsc_load_en;`
255
256			`ram_a_adr( 7 downto 0 ) <= port_c( 7 downto 0 );`
257			`ram_a_adr( 8 ) <= dma_chn;`
258
259			`dsc_adr_h <= ram_a_out( 31 downto 24 );`
260			`dsc_adr <= ram_a_out( 23 downto 0 );`
261			`dsc_size <= ram_a_out( 63 downto 40 );`
262
263			`dsc_cmd <= ram_a_out( 39 downto 32 );`
264
265			`dsc_correct <= dma_descriptor_error;`
266
267
268			`ram0: RAMB16_S36_S36`
269			`generic map(`
270			`SIM_COLLISION_CHECK => "NONE"`
271			`)`
272
273			`port map(`
274			`DOA => ram_a_out( 31 downto 0 ), --: out std_logic_vector(3 downto 0);`
275			`--DOB => ram_b_out( 31 downto 0 ), --: out std_logic_vector(31 downto 0);`
276			`--DOPB : out std_logic_vector(3 downto 0);`
277
278			`ADDRA => ram_a_adr( 8 downto 0 ), --: in std_logic_vector(11 downto 0);`
279			`ADDRB => ram_b_adr( 8 downto 0 ), --: in std_logic_vector(8 downto 0);`
280			`CLKA => clk,`
281			`CLKB => clk,`
282			`DIA => ram_a_in( 31 downto 0 ), --: in std_logic_vector(3 downto 0);`
283			`DIB => dma_wrdata( 31 downto 0 ), --: in std_logic_vector(31 downto 0);`
284			`DIPA => (others=>'0'),`
285			`DIPB => (others=>'0'),`
286			`ENA => '1',`
287			`ENB => '1',`
288			`SSRA => '0',`
289			`SSRB => '0',`
290			`WEA => ram_a_wr,`
291			`WEB => ram_b_wr`
292			`);`
293
294			`ram1: RAMB16_S36_S36`
295			`generic map(`
296			`SIM_COLLISION_CHECK => "NONE"`
297			`)`
298
299			`port map(`
300			`DOA => ram_a_out( 63 downto 32 ), --: out std_logic_vector(3 downto 0);`
301			`--DOB => ram_b_out( 31 downto 0 ), --: out std_logic_vector(31 downto 0);`
302			`--DOPB : out std_logic_vector(3 downto 0);`
303
304			`ADDRA => ram_a_adr( 8 downto 0 ), --: in std_logic_vector(11 downto 0);`
305			`ADDRB => ram_b_adr( 8 downto 0 ), --: in std_logic_vector(8 downto 0);`
306			`CLKA => clk,`
307			`CLKB => clk,`
308			`DIA => ram_a_in( 63 downto 32 ), --: in std_logic_vector(3 downto 0);`
309			`DIB => dma_wrdata( 63 downto 32 ), --: in std_logic_vector(31 downto 0);`
310			`DIPA => (others=>'0'),`
311			`DIPB => (others=>'0'),`
312			`ENA => '1',`
313			`ENB => '1',`
314			`SSRA => '0',`
315			`SSRB => '0',`
316			`WEA => ram_a_wr,`
317			`WEB => ram_b_wr`
318			`);`
319
320			`ram_a_out_x <= ram_a_out after 1 ns;`
321
322
323
324
325			`--p1 <= reg2(1);`
326			`--n1 <= not reg2(1);`
327
328			`-- reg0(2)=1 - �� : opmode=0x30 carry=1`
329			`-- reg0(2)=0 - �� : opmode=0x03 carry=0`
330			`--opmode <= '0' & p1 & p1 & "00" & n1 & n1;`
331			`--carry <= p1;`
332			`--opmode <= "0110000";`
333			`opmode <= '0' & not dsc_check_start & not dsc_check_start & "00" & dsc_check_start & '0';`
334			`carry <= '1';`
335
336			`port_b <= x"0000" & "00";`
337			`port_a <= x"0000" & "00";`
338
339
340			`gen_dsp48: if( is_dsp48=1 ) generate`
341
342			`dsp: DSP48`
343			`generic map(`
344
345			`AREG => 1,`
346			`B_INPUT => "DIRECT",`
347			`BREG => 1,`
348			`CARRYINREG => 1,`
349			`CARRYINSELREG => 1,`
350			`CREG => 1,`
351			`LEGACY_MODE => "MULT18X18S",`
352			`MREG => 1,`
353			`OPMODEREG => 1,`
354			`PREG => 1,`
355			`SUBTRACTREG => 1`
356			`)`
357
358			`port map(`
359			`--BCOUT : out std_logic_vector(17 downto 0);`
360			`P => port_p,`
361			`--PCOUT : out std_logic_vector(47 downto 0);`
362
363			`A => port_a,`
364			`B => port_b,`
365			`BCIN => (others=>'0'),`
366			`C => port_c,`
367			`CARRYIN => carry,`
368			`CARRYINSEL => "00",`
369			`CEA => '1',`
370			`CEB => '1',`
371			`CEC => '1',`
372			`CECARRYIN => '1',`
373			`CECINSUB => '1',`
374			`CECTRL => '1',`
375			`CEM => '1',`
376			`CEP => '1',`
377			`CLK => clk,`
378			`OPMODE => opmode,`
379			`PCIN => (others=>'0'),`
380			`RSTA => '0',`
381			`RSTB => '0',`
382			`RSTC => '0',`
383			`RSTCARRYIN => '0',`
384			`RSTCTRL => '0',`
385			`RSTM => '0',`
386			`RSTP => dsc_change_mode,`
387			`SUBTRACT => '0'`
388			`);`
389
390
391			`end generate;`
392
393			`gen_ndsp48: if( is_dsp48=0 ) generate`
394
395			`pr_dsp: process( clk ) begin`
396			`if( rising_edge( clk ) ) then`
397			`if( dsc_change_mode='1' ) then`
398			`port_p( 11 downto 0 ) <= (others=>'0') after 1 ns;`
399			`elsif( dsc_check_start='1' ) then`
400			`port_p( 11 downto 0 ) <= port_p( 11 downto 0 ) + 1 after 1 ns;`
401			`else`
402			`port_p( 11 downto 0 ) <= port_c( 11 downto 0 ) + 1 after 1 ns;`
403			`end if;`
404			`end if;`
405			`end process;`
406
407			`end generate;`
408
409			`gen_ram: for ii in 0 to 11 generate`
410
411			`ram_adr: ram16x1d`
412			`port map(`
413			`we => dsc_change_adr_i,`
414			`d => port_p(ii),`
415			`wclk => clk,`
416			`a0 => dma_chn,`
417			`a1 => '0',`
418			`a2 => '0',`
419			`a3 => '0',`
420			`spo => port_c(ii),`
421			`dpra0 => '0',`
422			`dpra1 => '0',`
423			`dpra2 => '0',`
424			`dpra3 => '1'`
425			`);`
426
427			`end generate;`
428
429			`port_c( 47 downto 12 ) <= (others=>'0');`
430
431			`reg0_z <= dsc_load_en after 1 ns when rising_edge( clk );`
432			`crc_reset <= '1' when dsc_load_en='1' and reg0_z='0' else '0';`
433
434			`---- �� ----`
435			`pr_crc: process( clk )`
436
437			`variable v : std_logic_vector( 15 downto 0 );`
438
439			`begin`
440			`if( rising_edge( clk ) ) then`
441			`if( crc_reset='1' ) then`
442			`crc <= (others=>'1') after 1 ns;`
443			`elsif( crc_we='1' ) then`
444			`v := crc xor`
445			`ram_a_out_x( 15 downto 0 ) xor`
446			`ram_a_out_x( 31 downto 16 ) xor`
447			`ram_a_out_x( 47 downto 32 ) xor`
448			`ram_a_out_x( 63 downto 48 );`
449
450			`crc( 15 downto 1 ) <= v( 14 downto 0 ) after 1 ns;`
451			`crc( 0 ) <= not v( 15 ) after 1 ns;`
452			`end if;`
453			`end if;`
454			`end process;`
455
456
457			`------ �� ----`
458			`--pr_crc2: process( clk )`
459			`--`
460			`--variable v : std_logic_vector( 15 downto 0 );`
461			`--`
462			`--begin`
463			`-- if( rising_edge( clk ) ) then`
464			`-- if( crc_reset='1' ) then`
465			`-- crc_2 <= (others=>'1') after 1 ns;`
466			`-- elsif( ram_b_wr='1' ) then`
467			`-- v := crc_2 xor`
468			`-- dma_wrdata( 15 downto 0 ) xor`
469			`-- dma_wrdata( 31 downto 16 ) xor`
470			`-- dma_wrdata( 47 downto 32 ) xor`
471			`-- dma_wrdata( 63 downto 48 );`
472			`--`
473			`-- crc_2( 15 downto 1 ) <= v( 14 downto 0 ) after 1 ns;`
474			`-- crc_2( 0 ) <= not v( 15 ) after 1 ns;`
475			`-- end if;`
476			`-- end if;`
477			`--end process;`
478
479			`crc_z <= '1' when crc=x"0001" else '0';`
480			`dma_descriptor_error <= not ( (not crc_z) or sig_error ) after 1 ns when rising_edge( clk );`
481
482			`pr_sig: process( clk ) begin`
483			`if( rising_edge( clk ) ) then`
484			`if( crc_we='1' ) then`
485			`if( ram_a_out( 47 downto 32 )=x"4953" ) then`
486			`sig_error <= '0' after 1 ns;`
487			`else`
488			`sig_error <= '1' after 1 ns;`
489			`end if;`
490			`end if;`
491			`end if;`
492			`end process;`
493
494
495			`pr_dsc_check_ready: process( clk ) begin`
496			`if( rising_edge( clk ) ) then`
497			`if( dsc_check_start='0' ) then`
498			`dsc_check_ready_i <= '0' after 1 ns;`
499			`elsif( port_p(6)='1' ) then`
500			`dsc_check_ready_i <= '1' after 1 ns;`
501			`end if;`
502			`end if;`
503			`end process;`
504
505			`xready: srl16 port map( q=>dsc_check_ready, clk=>clk, d=>dsc_check_ready_i, a3=>'0', a2=>'1', a1=>'0', a0=>'0' );`
506
507			`dsc_change_adr_i <= dsc_change_adr or dsc_check_start;`
508
509			`crc_we_0 <= dsc_check_start and not port_p(6) after 1 ns when rising_edge( clk );`
510			`crc_we <= crc_we_0 after 1 ns when rising_edge( clk );`
511
512			`--pr_crc_we: process( clk ) begin`
513			`-- if( rising_edge( clk ) ) then`
514			`-- if( dsc_check_start='0' ) then`
515			`-- crc_we <= '0' after 1 ns;`
516			`-- elsif( crc_we_0='1' ) then`
517			`-- crc_we <= not crc_we after 1 ns;`
518			`-- end if;`
519			`-- end if;`
520			`--end process;`
521
522			`end ctrl_ext_descriptor;`