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-------------------------------------------------------------------------------
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--
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-- Title : ctrl_ram_cmd
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.4
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Узел управления памятью
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.4 09.04.2012
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-- Исправлено формирование
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-- ch0_next_block, ch1_next_block
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.3 06.12.2011
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-- Добавлен local_adr_we
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.2 05.04.2010
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-- Добавлен параметр is_dsp48 - разрешение использования
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-- блоков DSP48
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.1 02.09.2009
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-- Исправлен сброс ch1_adr_hi
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package ctrl_ram_cmd_pkg is
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component ctrl_ram_cmd is
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generic(
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is_dsp48 : in integer:=1 -- 1 - использовать DSP48, 0 - не использовать DSP48
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);
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port(
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---- Global ----
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reset : in std_logic; -- 0 - сброс
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clk : in std_logic; --! Тактовая частота ядра - 250 МГц
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aclk : in std_logic; --! Тактовая частота локальной шины - 266 МГц
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---- Picoblaze ----
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dma_chn : in std_logic; -- номер канала DMA
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reg_ch0_ctrl : in std_logic_vector( 7 downto 0 ); -- регистр управления
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reg_ch1_ctrl : in std_logic_vector( 7 downto 0 ); -- регистр управления
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reg_write_E0 : in std_logic; -- 1 - смена блока памяти
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dma0_transfer_rdy : out std_logic; -- 1 - блок памяти готов к обмену
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dma1_transfer_rdy : out std_logic; -- 1 - блок памяти готов к обмену
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loc_adr_we : in std_logic; -- 1 - запись локального адреса
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---- PLB_BUS ----
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dmar0 : in std_logic; -- 1 - запрос DMA 0
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dmar1 : in std_logic; -- 1 - запрос DMA 1
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request_wr : out std_logic; --! 1 - запрос на запись в регистр
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request_rd : out std_logic; --! 1 - запрос на чтение из регистра
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allow_wr : in std_logic; --! 1 - разрешение записи
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pb_complete : in std_logic; --! 1 - завершение обмена по шине PLD_BUS
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pf_repack_we : in std_logic; -- 1 - запись в память
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pf_ram_rd_out : out std_logic; -- 1 - чтение из памяти
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---- Память ----
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ram_adra_a9 : out std_logic; -- разряд 9 адреса памяти
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ram_adrb : out std_logic_vector( 10 downto 0 )
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);
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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use work.ctrl_ram_cmd_pb_pkg.all;
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entity ctrl_ram_cmd is
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generic(
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is_dsp48 : in integer:=1 -- 1 - использовать DSP48, 0 - не использовать DSP48
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);
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port(
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---- Global ----
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reset : in std_logic; -- 0 - сброс
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clk : in std_logic; --! Тактовая частота ядра - 250 МГц
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aclk : in std_logic; --! Тактовая частота локальной шины - 266 МГц
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---- Picoblaze ----
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dma_chn : in std_logic; -- номер канала DMA
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reg_ch0_ctrl : in std_logic_vector( 7 downto 0 ); -- регистр управления
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reg_ch1_ctrl : in std_logic_vector( 7 downto 0 ); -- регистр управления
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reg_write_E0 : in std_logic; -- 1 - смена блока памяти
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dma0_transfer_rdy : out std_logic; -- 1 - блок памяти готов к обмену
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dma1_transfer_rdy : out std_logic; -- 1 - блок памяти готов к обмену
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loc_adr_we : in std_logic; -- 1 - запись локального адреса
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---- PLB_BUS ----
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dmar0 : in std_logic; -- 1 - запрос DMA 0
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dmar1 : in std_logic; -- 1 - запрос DMA 1
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request_wr : out std_logic; --! 1 - запрос на запись в регистр
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request_rd : out std_logic; --! 1 - запрос на чтение из регистра
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allow_wr : in std_logic; --! 1 - разрешение записи
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pb_complete : in std_logic; --! 1 - завершение обмена по шине PLD_BUS
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pf_repack_we : in std_logic; -- 1 - запись в память
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pf_ram_rd_out : out std_logic; -- 1 - чтение из памяти
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---- Память ----
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ram_adra_a9 : out std_logic; -- разряд 9 адреса памяти
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ram_adrb : out std_logic_vector( 10 downto 0 )
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);
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end ctrl_ram_cmd;
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architecture ctrl_ram_cmd of ctrl_ram_cmd is
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signal pb_current_block: std_logic_vector( 1 downto 0 );
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signal flag_data : std_logic_vector( 3 downto 0 );
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signal cb : std_logic;
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signal pb_flag_set : std_logic_vector( 3 downto 0 );
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signal pb_flag_clr : std_logic_vector( 3 downto 0 );
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signal pf_flag_set : std_logic_vector( 3 downto 0 );
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signal pf_flag_clr : std_logic_vector( 3 downto 0 );
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signal pb_fclr : std_logic;
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signal pb_fset : std_logic;
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signal reg_write_E0_z : std_logic;
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signal reg_write_E0_z1 : std_logic;
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signal pf_chn : std_logic;
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signal pf0_act : std_logic;
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signal pf0_rdy : std_logic;
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signal pf1_act : std_logic;
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signal pf1_rdy : std_logic;
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type stp_type is ( s0, s1, s2, s3 );
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signal stp : stp_type;
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signal rst_p : std_logic;
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signal rst_p0 : std_logic;
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signal pf0_cb : std_logic;
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signal pf0_dma_wr_rdy : std_logic;
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signal pf0_dma_rd_rdy : std_logic;
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signal pf1_cb : std_logic;
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signal pf1_dma_wr_rdy : std_logic;
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signal pf1_dma_rd_rdy : std_logic;
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signal ram0_transfer_rdy : std_logic;
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signal ram1_transfer_rdy : std_logic;
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signal port_a : std_logic_vector( 17 downto 0 );
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signal port_b : std_logic_vector( 17 downto 0 );
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signal port_c : std_logic_vector( 47 downto 0 );
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signal port_p : std_logic_vector( 47 downto 0 );
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signal opmode : std_logic_vector( 6 downto 0 );
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signal carry : std_logic;
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signal cnt_rstp : std_logic;
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signal ch0_adr_hi : std_logic_vector( 1 downto 0 );
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signal ch1_adr_hi : std_logic_vector( 1 downto 0 );
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signal ch0_next_block : std_logic;
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signal ch1_next_block : std_logic;
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signal ch0_adr_hi_wr : std_logic;
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signal ch1_adr_hi_wr : std_logic;
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signal pf_ram_rd : std_logic;
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signal pf_dma_wr_rdy : std_logic;
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signal pf_dma_rd_rdy : std_logic;
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signal pf_stop_rd : std_logic;
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signal loc_adr_ch0_we : std_logic;
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signal loc_adr_ch1_we : std_logic;
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begin
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cb <= pb_current_block( conv_integer( dma_chn ) );
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ram_adra_a9 <= cb;
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reg_write_E0_z <= reg_write_E0 after 1 ns when rising_edge( clk );
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reg_write_E0_z1 <= reg_write_E0_z after 1 ns when rising_edge( clk );
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pb_flag_clr(0) <= reg_ch0_ctrl(4) or ( reg_write_E0_z and reg_ch0_ctrl(2) and not dma_chn and not pb_current_block(0) ) after 1 ns when rising_edge( clk );
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pb_flag_clr(1) <= reg_ch0_ctrl(4) or ( reg_write_E0_z and reg_ch0_ctrl(2) and not dma_chn and pb_current_block(0) ) after 1 ns when rising_edge( clk );
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pb_flag_clr(2) <= reg_ch1_ctrl(4) or ( reg_write_E0_z and reg_ch1_ctrl(2) and dma_chn and not pb_current_block(1) ) after 1 ns when rising_edge( clk );
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pb_flag_clr(3) <= reg_ch1_ctrl(4) or ( reg_write_E0_z and reg_ch1_ctrl(2) and dma_chn and pb_current_block(1) ) after 1 ns when rising_edge( clk );
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pb_flag_set(0) <= reg_write_E0_z and not reg_ch0_ctrl(2) and not dma_chn and not pb_current_block(0) after 1 ns when rising_edge( clk );
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pb_flag_set(1) <= reg_write_E0_z and not reg_ch0_ctrl(2) and not dma_chn and pb_current_block(0) after 1 ns when rising_edge( clk );
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pb_flag_set(2) <= reg_write_E0_z and not reg_ch1_ctrl(2) and dma_chn and not pb_current_block(1) after 1 ns when rising_edge( clk );
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pb_flag_set(3) <= reg_write_E0_z and not reg_ch1_ctrl(2) and dma_chn and pb_current_block(1) after 1 ns when rising_edge( clk );
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pr_current_block0: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( reg_ch0_ctrl(4)='1' ) then
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pb_current_block(0) <= '0' after 1 ns;
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elsif( reg_write_E0_z1='1' and dma_chn='0' ) then
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pb_current_block(0) <= not pb_current_block(0) after 1 ns;
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end if;
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end if;
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end process;
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pr_current_block1: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( reg_ch1_ctrl(4)='1' ) then
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pb_current_block(1) <= '0' after 1 ns;
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elsif( reg_write_E0_z1='1' and dma_chn='1' ) then
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pb_current_block(1) <= not pb_current_block(1) after 1 ns;
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end if;
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end if;
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end process;
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gen_flag: for ii in 0 to 3 generate
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process( clk ) begin
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if( rising_edge( clk ) ) then
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if( pb_flag_clr(ii)='1' or pf_flag_clr(ii)='1' or rst_p='1' ) then
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flag_data(ii) <= '0' after 1 ns;
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elsif( pb_flag_set(ii)='1' or pf_flag_set(ii)='1' ) then
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flag_data(ii) <= '1' after 1 ns;
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end if;
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end if;
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end process;
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end generate;
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---- Формирование готовности блока к обмену ----
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pr0_transfer_rdy: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( reg_ch0_ctrl(2)='1' and flag_data( conv_integer(pb_current_block(0)) )='1' ) then
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ram0_transfer_rdy <= reg_ch0_ctrl(0) and not reg_ch0_ctrl(3) after 1 ns;
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elsif( reg_ch0_ctrl(2)='0' and flag_data( conv_integer(pb_current_block(0)) )='0' ) then
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ram0_transfer_rdy <= reg_ch0_ctrl(0) and not reg_ch0_ctrl(3) after 1 ns;
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else
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ram0_transfer_rdy <= '0' after 1 ns;
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end if;
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end if;
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end process;
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pr1_transfer_rdy: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( reg_ch1_ctrl(2)='1' and flag_data( 2+conv_integer(pb_current_block(1)) )='1' ) then
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ram1_transfer_rdy <= reg_ch1_ctrl(0) and not reg_ch1_ctrl(3) after 1 ns;
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elsif( reg_ch1_ctrl(2)='0' and flag_data( 2+conv_integer(pb_current_block(1)) )='0' ) then
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ram1_transfer_rdy <= reg_ch1_ctrl(0) and not reg_ch1_ctrl(3) after 1 ns;
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else
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ram1_transfer_rdy <= '0' after 1 ns;
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end if;
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end if;
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end process;
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dma0_transfer_rdy <= ram0_transfer_rdy;
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dma1_transfer_rdy <= ram1_transfer_rdy;
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--ram_transfer_rdy <= (ram0_transfer_rdy and not dma_chn) or (ram1_transfer_rdy and dma_chn) after 1 ns
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-- when rising_edge( clk );
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---- Перебор каналов DMA ----
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rst_p0 <= not reset after 1 ns when rising_edge( aclk );
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rst_p <= rst_p0 after 1 ns when rising_edge( aclk );
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pr_state: process( aclk ) begin
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if( rising_edge( aclk ) ) then
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case( stp ) is
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when s0 =>
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cnt_rstp <= '0' after 1 ns;
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pf_chn <= '0' after 1 ns;
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pf0_act <= '1' after 1 ns;
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pf1_act <= '0' after 1 ns;
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if( pf0_rdy='1' ) then
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stp <= s1 after 1 ns;
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end if;
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when s1 =>
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cnt_rstp <= '1' after 1 ns;
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|
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pf0_act <= '0' after 1 ns;
|
313 |
|
|
if( pf0_rdy='0' ) then
|
314 |
|
|
stp <= s2 after 1 ns;
|
315 |
|
|
end if;
|
316 |
|
|
|
317 |
|
|
when s2 =>
|
318 |
|
|
cnt_rstp <= '0' after 1 ns;
|
319 |
|
|
pf_chn <= '1' after 1 ns;
|
320 |
|
|
pf1_act <= '1' after 1 ns;
|
321 |
|
|
if( pf1_rdy='1' ) then
|
322 |
|
|
stp <= s3 after 1 ns;
|
323 |
|
|
end if;
|
324 |
|
|
|
325 |
|
|
when s3 =>
|
326 |
|
|
cnt_rstp <= '1' after 1 ns;
|
327 |
|
|
pf1_act <= '0' after 1 ns;
|
328 |
|
|
if( pf1_rdy='0' ) then
|
329 |
|
|
stp <= s0 after 1 ns;
|
330 |
|
|
end if;
|
331 |
|
|
|
332 |
|
|
end case;
|
333 |
|
|
|
334 |
|
|
if( rst_p='1' ) then
|
335 |
|
|
stp <= s0 after 1 ns;
|
336 |
|
|
pf0_act <= '0' after 1 ns;
|
337 |
|
|
cnt_rstp <= '1' after 1 ns;
|
338 |
|
|
|
339 |
|
|
end if;
|
340 |
|
|
|
341 |
|
|
end if;
|
342 |
|
|
end process;
|
343 |
|
|
|
344 |
|
|
|
345 |
|
|
|
346 |
|
|
cmd0: ctrl_ram_cmd_pb
|
347 |
|
|
port map(
|
348 |
|
|
---- Global ----
|
349 |
|
|
reset => reset, -- 0 - сброс
|
350 |
|
|
clk => clk, -- тактовая частота 250 МГц
|
351 |
|
|
aclk => aclk, -- тактовая частота 266 МГц
|
352 |
|
|
|
353 |
|
|
act => pf0_act, -- 1 - разрешение цикла обработки
|
354 |
|
|
rdy => pf0_rdy, -- 1 - завершение цикла обработки
|
355 |
|
|
|
356 |
|
|
loc_adr_we => loc_adr_ch0_we, -- 1 - запись локального адреса
|
357 |
|
|
flag_data => flag_data( 1 downto 0 ), -- 1 - наличие данных в блоке
|
358 |
|
|
|
359 |
|
|
flag_set => pf_flag_set( 1 downto 0 ), -- 1 - установка флага наличия данных
|
360 |
|
|
flag_clr => pf_flag_clr( 1 downto 0 ), -- 1 - сброс флага наличия данных
|
361 |
|
|
next_block => ch0_next_block, -- 1 - признак достижения блока 4 килобайта
|
362 |
|
|
adr_hi_wr => ch0_adr_hi_wr, -- 1 - увеличение старших разрядов адреса для блока
|
363 |
|
|
|
364 |
|
|
reg_ctrl => reg_ch0_ctrl( 7 downto 0 ), -- регистр управления
|
365 |
|
|
|
366 |
|
|
dmar => dmar0, -- 1 - запрос DMA
|
367 |
|
|
|
368 |
|
|
pf_cb => pf0_cb, -- номер текущего блока для обмена с шиной
|
369 |
|
|
pf_dma_wr_rdy => pf0_dma_wr_rdy, -- 1 - готовность передать 128 слов
|
370 |
|
|
pf_dma_rd_rdy => pf0_dma_rd_rdy, -- 1 - готовность принять 128 слов
|
371 |
|
|
|
372 |
|
|
pf_ram_rd => pf_ram_rd, -- 1 - чтение данных из памяти
|
373 |
|
|
pf_repack_we => pf_repack_we -- 1 - запись в память
|
374 |
|
|
);
|
375 |
|
|
|
376 |
|
|
cmd1: ctrl_ram_cmd_pb
|
377 |
|
|
port map(
|
378 |
|
|
---- Global ----
|
379 |
|
|
reset => reset, -- 0 - сброс
|
380 |
|
|
clk => clk, -- тактовая частота 250 МГц
|
381 |
|
|
aclk => aclk, -- тактовая частота 266 МГц
|
382 |
|
|
|
383 |
|
|
act => pf1_act, -- 1 - разрешение цикла обработки
|
384 |
|
|
rdy => pf1_rdy, -- 1 - завершение цикла обработки
|
385 |
|
|
|
386 |
|
|
loc_adr_we => loc_adr_ch1_we, -- 1 - запись локального адреса
|
387 |
|
|
flag_data => flag_data( 3 downto 2 ), -- 1 - наличие данных в блоке
|
388 |
|
|
|
389 |
|
|
flag_set => pf_flag_set( 3 downto 2 ), -- 1 - установка флага наличия данных
|
390 |
|
|
flag_clr => pf_flag_clr( 3 downto 2 ), -- 1 - сброс флага наличия данных
|
391 |
|
|
next_block => ch1_next_block, -- 1 - признак достижения блока 4 килобайта
|
392 |
|
|
adr_hi_wr => ch1_adr_hi_wr, -- 1 - увеличение старших разрядов адреса для блока
|
393 |
|
|
|
394 |
|
|
reg_ctrl => reg_ch1_ctrl( 7 downto 0 ), -- регистр управления
|
395 |
|
|
|
396 |
|
|
dmar => dmar1, -- 1 - запрос DMA
|
397 |
|
|
|
398 |
|
|
pf_cb => pf1_cb, -- номер текущего блока для обмена с шиной
|
399 |
|
|
pf_dma_wr_rdy => pf1_dma_wr_rdy, -- 1 - готовность передать 128 слов
|
400 |
|
|
pf_dma_rd_rdy => pf1_dma_rd_rdy, -- 1 - готовность принять 128 слов
|
401 |
|
|
|
402 |
|
|
pf_ram_rd => pf_ram_rd, -- 1 - чтение данных из памяти
|
403 |
|
|
pf_repack_we => pf_repack_we -- 1 - запись в память
|
404 |
|
|
);
|
405 |
|
|
|
406 |
|
|
pf_dma_wr_rdy <= pf0_dma_wr_rdy or pf1_dma_wr_rdy;
|
407 |
|
|
pf_dma_rd_rdy <= pf0_dma_rd_rdy or pf1_dma_rd_rdy;
|
408 |
|
|
|
409 |
|
|
request_wr <= pf_dma_wr_rdy;
|
410 |
|
|
request_rd <= pf_dma_rd_rdy;
|
411 |
|
|
|
412 |
|
|
ram_adrb(10) <= pf_chn;
|
413 |
|
|
ram_adrb(9) <= pf0_cb when pf_chn='0' else pf1_cb;
|
414 |
|
|
|
415 |
|
|
--ram_adrb( 8 downto 7 ) <= ch0_adr_hi when pf_chn='0' else ch1_adr_hi;
|
416 |
|
|
--
|
417 |
|
|
--ram_adrb( 6 downto 0 ) <= port_p( 6 downto 0 ) after 1 ns;
|
418 |
|
|
|
419 |
|
|
ram_adrb( 8 downto 0 ) <= port_p( 8 downto 0 ) after 1 ns;
|
420 |
|
|
|
421 |
|
|
opmode <= "0100000";
|
422 |
|
|
carry <= pf_repack_we or pf_ram_rd;
|
423 |
|
|
|
424 |
|
|
pr_pf_ram_rd: process( aclk ) begin
|
425 |
|
|
if( rising_edge( aclk ) ) then
|
426 |
|
|
if( cnt_rstp='1' or port_p( 8 downto 0 )="111111111" ) or pf_stop_rd='1' or allow_wr='0' then
|
427 |
|
|
pf_ram_rd <= '0' after 1 ns;
|
428 |
|
|
elsif( pf_dma_wr_rdy='1' and allow_wr='1' ) then
|
429 |
|
|
pf_ram_rd <= '1' after 1 ns;
|
430 |
|
|
end if;
|
431 |
|
|
end if;
|
432 |
|
|
end process;
|
433 |
|
|
|
434 |
|
|
pr_stop_rd: process( aclk ) begin
|
435 |
|
|
if( rising_edge( aclk ) ) then
|
436 |
|
|
if( cnt_rstp='1' ) then
|
437 |
|
|
pf_stop_rd <= '0' after 1 ns;
|
438 |
|
|
elsif( port_p( 8 downto 0 )="111111111" ) then
|
439 |
|
|
pf_stop_rd <= '1' after 1 ns;
|
440 |
|
|
end if;
|
441 |
|
|
end if;
|
442 |
|
|
end process;
|
443 |
|
|
|
444 |
|
|
--pf_ram_rd_out <= pf_ram_rd;
|
445 |
|
|
pf_ram_rd_out <= pf_ram_rd and allow_wr;
|
446 |
|
|
|
447 |
|
|
|
448 |
|
|
port_b <= x"0000" & "00";
|
449 |
|
|
port_a <= x"0000" & "00";
|
450 |
|
|
|
451 |
|
|
port_c <= port_p;
|
452 |
|
|
|
453 |
|
|
|
454 |
|
|
gen_dsp48: if( is_dsp48=1 ) generate
|
455 |
|
|
|
456 |
|
|
dsp: DSP48
|
457 |
|
|
generic map(
|
458 |
|
|
|
459 |
|
|
AREG => 1,
|
460 |
|
|
B_INPUT => "DIRECT",
|
461 |
|
|
BREG => 1,
|
462 |
|
|
CARRYINREG => 0,
|
463 |
|
|
CARRYINSELREG => 1,
|
464 |
|
|
CREG => 1,
|
465 |
|
|
LEGACY_MODE => "NONE",
|
466 |
|
|
MREG => 1,
|
467 |
|
|
OPMODEREG => 1,
|
468 |
|
|
PREG => 1,
|
469 |
|
|
SUBTRACTREG => 0
|
470 |
|
|
)
|
471 |
|
|
|
472 |
|
|
port map(
|
473 |
|
|
--BCOUT : out std_logic_vector(17 downto 0);
|
474 |
|
|
P => port_p,
|
475 |
|
|
--PCOUT : out std_logic_vector(47 downto 0);
|
476 |
|
|
|
477 |
|
|
A => port_a,
|
478 |
|
|
B => port_b,
|
479 |
|
|
BCIN => (others=>'0'),
|
480 |
|
|
C => port_c,
|
481 |
|
|
CARRYIN => carry,
|
482 |
|
|
CARRYINSEL => "00",
|
483 |
|
|
CEA => '1',
|
484 |
|
|
CEB => '1',
|
485 |
|
|
CEC => '1',
|
486 |
|
|
CECARRYIN => '1',
|
487 |
|
|
CECINSUB => '1',
|
488 |
|
|
CECTRL => '1',
|
489 |
|
|
CEM => '1',
|
490 |
|
|
CEP => '1',
|
491 |
|
|
CLK => aclk,
|
492 |
|
|
OPMODE => opmode,
|
493 |
|
|
PCIN => (others=>'0'),
|
494 |
|
|
RSTA => '0',
|
495 |
|
|
RSTB => '0',
|
496 |
|
|
RSTC => '0',
|
497 |
|
|
RSTCARRYIN => '0',
|
498 |
|
|
RSTCTRL => '0',
|
499 |
|
|
RSTM => '0',
|
500 |
|
|
RSTP => cnt_rstp,
|
501 |
|
|
SUBTRACT => '0'
|
502 |
|
|
);
|
503 |
|
|
|
504 |
|
|
end generate;
|
505 |
|
|
|
506 |
|
|
gen_ndsp48: if( is_dsp48=0 ) generate
|
507 |
|
|
|
508 |
|
|
port_p( 47 downto 9 ) <= (others=>'0');
|
509 |
|
|
|
510 |
|
|
pr_dsp: process( clk ) begin
|
511 |
|
|
if( rising_edge( clk ) ) then
|
512 |
|
|
if( cnt_rstp='1' ) then
|
513 |
|
|
port_p( 8 downto 0 ) <= (others=>'0' ) after 1 ns;
|
514 |
|
|
elsif( carry='1' ) then
|
515 |
|
|
port_p( 8 downto 0 ) <= port_p( 8 downto 0 ) + 1 after 1 ns;
|
516 |
|
|
end if;
|
517 |
|
|
end if;
|
518 |
|
|
end process;
|
519 |
|
|
|
520 |
|
|
end generate;
|
521 |
|
|
|
522 |
|
|
|
523 |
|
|
pr_ch0_adr_hi: process( clk ) begin
|
524 |
|
|
if( rising_edge( clk ) ) then
|
525 |
|
|
if( reset='0' or reg_ch0_ctrl(4)='1' ) then
|
526 |
|
|
ch0_adr_hi <= "00" after 1 ns;
|
527 |
|
|
elsif( ch0_adr_hi_wr='1' ) then
|
528 |
|
|
ch0_adr_hi <= ch0_adr_hi + 1 after 1 ns;
|
529 |
|
|
end if;
|
530 |
|
|
end if;
|
531 |
|
|
end process;
|
532 |
|
|
|
533 |
|
|
pr_ch1_adr_hi: process( clk ) begin
|
534 |
|
|
if( rising_edge( clk ) ) then
|
535 |
|
|
if( reset='0' or reg_ch1_ctrl(4)='1' ) then
|
536 |
|
|
ch1_adr_hi <= "00" after 1 ns;
|
537 |
|
|
elsif( ch1_adr_hi_wr='1' ) then
|
538 |
|
|
ch1_adr_hi <= ch1_adr_hi + 1 after 1 ns;
|
539 |
|
|
end if;
|
540 |
|
|
end if;
|
541 |
|
|
end process;
|
542 |
|
|
|
543 |
|
|
--ch0_next_block <= ch0_adr_hi(0) and ch0_adr_hi(1);
|
544 |
|
|
--ch1_next_block <= ch1_adr_hi(0) and ch1_adr_hi(1);
|
545 |
|
|
|
546 |
|
|
--ch0_next_block <= '1';
|
547 |
|
|
--ch1_next_block <= '1';
|
548 |
|
|
|
549 |
|
|
ch0_next_block <= pb_complete and pf0_act;
|
550 |
|
|
ch1_next_block <= pb_complete and pf1_act;
|
551 |
|
|
|
552 |
|
|
loc_adr_ch0_we <= loc_adr_we and not dma_chn;
|
553 |
|
|
loc_adr_ch1_we <= loc_adr_we and dma_chn;
|
554 |
|
|
|
555 |
|
|
|
556 |
|
|
end ctrl_ram_cmd;
|