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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_fifo_ext/] [ctrl_ram_cmd_pb.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
--
-- Title       : ctrl_ram_cmd_pb
-- Author      : Dmitry Smekhov
-- Company     : Instrumental Systems
-- E-mail      : dsmv@insys.ru
--
-- Version     : 1.3
--
-------------------------------------------------------------------------------
--
-- Description : ���� ���������� ��������� � ���� PLD_BUS
--
-------------------------------------------------------------------------------
--                                       
--  Version 1.3   24.04.2012 Dmitry Smekhov
--
--  ���������� ������������ block_rd_eot
--
-------------------------------------------------------------------------------
--                                       
--  Version 1.3   09.04.2012 Dmitry Smekhov
--
--  ���������� ������������ rdy �� ����� ������
--
-------------------------------------------------------------------------------
--                                       
--  Version 1.1   06.12.2011 Dmitry Smekhov
--
--  �������� local_adr_we - ����� DMA ������ �������� ������ ������ �����
--                                                  ��������� ���������� ������
--
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
 
package ctrl_ram_cmd_pb_pkg is
 
component ctrl_ram_cmd_pb is
        port(
                ---- Global ----
                reset                           : in std_logic;         -- 0 - �����
                clk                                     : in std_logic;         --! �������� ������� ���� - 250 ���
                aclk                            : in std_logic;         --! �������� ������� ��������� ���� - 266 ���
 
                act                                     : in std_logic;         -- 1 - ���������� ����� ���������
                rdy                                     : out std_logic;        -- 1 - ���������� ����� ���������
 
                loc_adr_we                      : in std_logic; -- 1 - ������ ���������� ������
                flag_data                       : in  std_logic_vector( 1 downto 0 );    -- 1 - ������� ������ � �����
 
                flag_set                        : out std_logic_vector( 1 downto 0 );    -- 1 - ��������� ����� ������� ������
                flag_clr                        : out std_logic_vector( 1 downto 0 );    -- 1 - ����� ����� ������� ������
                next_block                      : in  std_logic;        -- 1 - ������� ���������� ����� 4 ���������
                adr_hi_wr                       : out std_logic;        -- 1 - ���������� ������� �������� ������ ��� �����
 
                reg_ctrl                        : in std_logic_vector( 7 downto 0 ); -- ������� ����������
 
                dmar                            : in  std_logic;        -- 1 - ������ DMA                                         
 
                pf_cb                           : out std_logic;        -- ����� �������� ����� ��� ������ � �����
                pf_dma_wr_rdy           : out std_logic;        -- 1 - ���������� �������� 512 ����
                pf_dma_rd_rdy           : out std_logic;        -- 1 - ���������� ������� 512 ����
 
                pf_ram_rd                       : in  std_logic;        -- 1 - ������ ������ �� ������
                pf_repack_we            : in  std_logic         -- 1 - ������ � ������
 
 
        );
end component;
 
end package;
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity ctrl_ram_cmd_pb is
        port(
                ---- Global ----
                reset                           : in std_logic;         -- 0 - �����
                clk                                     : in std_logic;         --! �������� ������� ���� - 250 ���
                aclk                            : in std_logic;         --! �������� ������� ��������� ���� - 266 ���
 
                act                                     : in std_logic;         -- 1 - ���������� ����� ���������
                rdy                                     : out std_logic;        -- 1 - ���������� ����� ���������
 
                loc_adr_we                      : in std_logic; -- 1 - ������ ���������� ������
                flag_data                       : in  std_logic_vector( 1 downto 0 );    -- 1 - ������� ������ � �����
 
                flag_set                        : out std_logic_vector( 1 downto 0 );    -- 1 - ��������� ����� ������� ������
                flag_clr                        : out std_logic_vector( 1 downto 0 );    -- 1 - ����� ����� ������� ������
                next_block                      : in  std_logic;        -- 1 - ������� ���������� ����� 4 ���������
                adr_hi_wr                       : out std_logic;        -- 1 - ���������� ������� �������� ������ ��� �����
 
                reg_ctrl                        : in std_logic_vector( 7 downto 0 ); -- ������� ����������
 
                dmar                            : in  std_logic;        -- 1 - ������ DMA                                         
 
                pf_cb                           : out std_logic;        -- ����� �������� ����� ��� ������ � �����
                pf_dma_wr_rdy           : out std_logic;        -- 1 - ���������� �������� 128 ����
                pf_dma_rd_rdy           : out std_logic;        -- 1 - ���������� ������� 128 ����
 
                pf_ram_rd                       : in  std_logic;        -- 1 - ������ ������ �� ������
                pf_repack_we            : in  std_logic         -- 1 - ������ � ������
 
 
        );
end ctrl_ram_cmd_pb;
 
 
architecture ctrl_ram_cmd_pb of ctrl_ram_cmd_pb is
 
type  stp_type is ( s0, s2,  sr2, sr5, sr6, sw2, sw3 ); -- s1, sr0, sr1,
signal  stp             : stp_type;
 
signal  rst_p   : std_logic;
signal  rst_p0  : std_logic;
 
signal  cb              : std_logic;
 
signal  block_rd_eot    : std_logic;
--signal        block_wr_eot    : std_logic;
signal  pf_repack_we_z  : std_logic;
signal  pf_ram_rd_z             : std_logic;
 
signal  start_rd                : std_logic;
signal  start_wr                : std_logic;
signal  dmari                   : std_logic;
 
signal  start_rd0               : std_logic;
signal  start_wr0               : std_logic;
 
signal  start_rd1               : std_logic;
signal  start_wr1               : std_logic;
 
signal  flag0_set               : std_logic_vector( 1 downto 0 );
signal  flag1_set               : std_logic_vector( 1 downto 0 );
signal  flag2_set               : std_logic_vector( 1 downto 0 );
 
signal  flag0_clr               : std_logic_vector( 1 downto 0 );
signal  flag1_clr               : std_logic_vector( 1 downto 0 );
signal  flag2_clr               : std_logic_vector( 1 downto 0 );
signal  local_adr_rdy   : std_logic;    -- 1 - ��������� ����� ������� 
 
 
 
attribute       tig                     : string;
attribute       tig                     of flag2_set    : signal is "";
attribute       tig                     of flag2_clr    : signal is "";
attribute       tig                     of start_rd0    : signal is "";
attribute       tig                     of start_wr0    : signal is "";
 
begin
 
rst_p0 <= (not reset) or reg_ctrl(4) after 1 ns when rising_edge( aclk );
rst_p <= rst_p0 after 1 ns when rising_edge( aclk );
 
pf_cb <= cb;
 
pf_repack_we_z <= pf_repack_we after 1 ns when rising_edge( aclk );
--block_rd_eot <= '1' when pf_repack_we='0' and pf_repack_we_z='1' else '0';
block_rd_eot <= next_block after 1 ns when rising_edge( aclk );
 
pf_ram_rd_z <= pf_ram_rd after 1 ns when rising_edge( aclk );
--block_wr_eot <= '1' when pf_ram_rd='0' and pf_ram_rd_z='1' else '0';
 
dmari <= dmar or not reg_ctrl(1);
 
pr_local_adr_rdy: process( clk ) begin
        if( rising_edge( clk ) ) then
                if( reg_ctrl(0)='0' ) then
                        local_adr_rdy <= '0' after 1 ns;
                elsif( loc_adr_we='1' ) then
                        local_adr_rdy <= '1' after 1 ns;
                end if;
        end if;
end process;
 
 
start_rd0 <= reg_ctrl(0) and reg_ctrl(2) and dmari and not flag_data( conv_integer(cb) ) and local_adr_rdy after 1 ns when rising_edge( aclk );
start_wr0 <= reg_ctrl(0) and (not reg_ctrl(2)) and dmari and flag_data( conv_integer(cb) ) and local_adr_rdy after 1 ns when rising_edge( aclk ) ;
 
 
start_rd1 <= start_rd0 after 1 ns when rising_edge( aclk );
start_wr1 <= start_wr0 after 1 ns when rising_edge( aclk );
 
start_rd <= act and start_rd1;
start_wr <= act and start_wr1;
 
pr_state: process( aclk ) begin
        if( rising_edge( aclk ) ) then
 
                case( stp ) is
 
                        when s0 =>
                                flag0_set(0) <= '0' after 1 ns;
                                flag0_set(1) <= '0' after 1 ns;
                                flag0_clr(0) <= '0' after 1 ns;
                                flag0_clr(1) <= '0' after 1 ns;
                                adr_hi_wr <= '0' after 1 ns;
 
                                pf_dma_wr_rdy <= '0' after 1 ns;
                                pf_dma_rd_rdy <= '0' after 1 ns;
 
                                rdy <= '0' after 1 ns;
                                if( start_rd='1' ) then
                                        pf_dma_rd_rdy <= '1' after  1 ns;
                                        stp <= sr2 after  1ns;
                                elsif( start_wr='1' ) then
                                    pf_dma_wr_rdy <= '1' after 1 ns;
                                        stp <= sw2 after 1 ns;
                                elsif( act='1' ) then
                                        stp <= s2 after 1 ns;
                                end if;
 
 
 
                        when s2 => --- ����� DMA �������� ----
                                rdy <= '1' after 1 ns;
                                --cb <= '0';
                                if( act='0' ) then
                                        stp <= s0 after 1 ns;
                                end if;
 
 
 
                        when sr2 =>
--                              if( pf_repack_we_z='1' ) then
--                                      pf_dma_rd_rdy <= '0' after 1 ns;
--                              end if;
                                if( block_rd_eot='1' ) then
                                        stp <= sr5 after 1 ns;
                                end if;
 
 
                        when sr5 =>
                                pf_dma_rd_rdy <= '0' after 1 ns;
                        --flag_set(conv_integer(cb)) <= '1' after 1 ns;
                                flag0_set(0) <= not cb after 1 ns;
                                flag0_set(1) <= cb after 1 ns;
 
--                      
--                              flag0_set(0) <= next_block and not cb after 1 ns;
--                              flag0_set(1) <= next_block and cb after 1 ns;
--                              if( next_block='1' ) then
--                                      cb <= not cb after 1 ns;
--                              end if;                                         
                                cb <= not cb after 1 ns;
                                stp <= sr6 after 1 ns;
                                adr_hi_wr <= '1' after 1 ns;
 
                        when sr6 =>
                                adr_hi_wr <= '0' after 1 ns;
                                flag0_set(0) <= '0' after 1 ns;
                                flag0_set(1) <= '0' after 1 ns;
                                flag0_clr(0) <= '0' after 1 ns;
                                flag0_clr(1) <= '0' after 1 ns;
                                rdy <= '1' after 1 ns;
                                if( act='0' ) then
                                        stp <= s0 after 1 ns;
                                end if;
 
                        when sw2 =>
--                              if( pf_ram_rd='1' ) then
--                                      pf_dma_wr_rdy <= '0' after  1 ns;
--                              end if;
                                if( block_rd_eot='1' ) then
                                        stp <= sw3 after 1 ns;
                                end if;
 
                        when sw3 =>
                                pf_dma_wr_rdy <= '0' after  1 ns;
                                flag0_clr(0) <= not cb after 1 ns;
                                flag0_clr(1) <= cb after 1 ns;
--                              if( next_block='1' ) then
--                                      cb <= not cb after 1 ns;
--                              end if;                 
                                cb <= not cb after 1 ns;
                                stp <= sr6 after  1 ns;
                                adr_hi_wr <= '1' after 1 ns;
 
 
 
                end case;
 
 
                if( rst_p='1' ) then
                        stp <= s0 after 1 ns;
                        cb <= '0' after 1 ns;
                        rdy <= act after 1 ns;
                end if;
 
 
        end if;
end process;
 
gen_flag: for ii in 0 to 1 generate
 
pr_flag1_set: process( flag0_set(ii), clk ) begin
 
        if( flag0_set(ii)='1' ) then
                flag1_set(ii) <= '1' after 1 ns;
        elsif( rising_edge( clk ) ) then
                if( flag2_set(ii)='1' or rst_p='1' ) then
                        flag1_set(ii) <= '0' after 1 ns;
                end if;
        end if;
 
end process;
 
pr_flag1_clr: process( flag0_clr(ii), clk ) begin
 
        if( flag0_clr(ii)='1' or rst_p='1' ) then
                flag1_clr(ii) <= '1' after 1 ns;
        elsif( rising_edge( clk ) ) then
                if( flag2_clr(ii)='1' ) then
                        flag1_clr(ii) <= '0' after 1 ns;
                end if;
        end if;
 
end process;
 
end generate;
 
flag2_set <= flag1_set after 1 ns when rising_edge( clk );
flag2_clr <= flag1_clr after 1 ns when rising_edge( clk );
 
flag_set <= flag1_set;
flag_clr <= flag1_clr;
 
 
end ctrl_ram_cmd_pb;

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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_fifo_ext/] [ctrl_ram_cmd_pb.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dsmv	`-------------------------------------------------------------------------------`
2			`--`
3			`-- Title : ctrl_ram_cmd_pb`
4			`-- Author : Dmitry Smekhov`
5			`-- Company : Instrumental Systems`
6			`-- E-mail : dsmv@insys.ru`
7			`--`
8			`-- Version : 1.3`
9			`--`
10			`-------------------------------------------------------------------------------`
11			`--`
12			`-- Description : �� PLD_BUS`
13			`--`
14			`-------------------------------------------------------------------------------`
15			`--`
16			`-- Version 1.3 24.04.2012 Dmitry Smekhov`
17			`--`
18			`-- �� block_rd_eot`
19			`--`
20			`-------------------------------------------------------------------------------`
21			`--`
22			`-- Version 1.3 09.04.2012 Dmitry Smekhov`
23			`--`
24			`-- �� rdy �� `
25			`--`
26			`-------------------------------------------------------------------------------`
27			`--`
28			`-- Version 1.1 06.12.2011 Dmitry Smekhov`
29			`--`
30			`-- �� local_adr_we - �� DMA �� `
31			`-- �� `
32			`--`
33			`-------------------------------------------------------------------------------`
34
35
36			`library ieee;`
37			`use ieee.std_logic_1164.all;`
38
39			`package ctrl_ram_cmd_pb_pkg is`
40
41			`component ctrl_ram_cmd_pb is`
42			`port(`
43			`---- Global ----`
44			`reset : in std_logic; -- 0 - ��`
45			`clk : in std_logic; --! �� - 250 ��`
46			`aclk : in std_logic; --! �� - 266 ��`
47
48			`act : in std_logic; -- 1 - �� `
49			`rdy : out std_logic; -- 1 - �� `
50
51			`loc_adr_we : in std_logic; -- 1 - �� `
52			`flag_data : in std_logic_vector( 1 downto 0 ); -- 1 - �� `
53
54			`flag_set : out std_logic_vector( 1 downto 0 ); -- 1 - �� `
55			`flag_clr : out std_logic_vector( 1 downto 0 ); -- 1 - �� `
56			`next_block : in std_logic; -- 1 - �� 4 ��`
57			`adr_hi_wr : out std_logic; -- 1 - �� `
58
59			`reg_ctrl : in std_logic_vector( 7 downto 0 ); -- �� `
60
61			`dmar : in std_logic; -- 1 - �� DMA`
62
63			`pf_cb : out std_logic; -- �� `
64			`pf_dma_wr_rdy : out std_logic; -- 1 - �� 512 ��`
65			`pf_dma_rd_rdy : out std_logic; -- 1 - �� 512 ��`
66
67			`pf_ram_rd : in std_logic; -- 1 - �� `
68			`pf_repack_we : in std_logic -- 1 - �� `
69
70
71			`);`
72			`end component;`
73
74			`end package;`
75
76
77
78			`library ieee;`
79			`use ieee.std_logic_1164.all;`
80			`use ieee.std_logic_arith.all;`
81			`use ieee.std_logic_unsigned.all;`
82
83			`entity ctrl_ram_cmd_pb is`
84			`port(`
85			`---- Global ----`
86			`reset : in std_logic; -- 0 - ��`
87			`clk : in std_logic; --! �� - 250 ��`
88			`aclk : in std_logic; --! �� - 266 ��`
89
90			`act : in std_logic; -- 1 - �� `
91			`rdy : out std_logic; -- 1 - �� `
92
93			`loc_adr_we : in std_logic; -- 1 - �� `
94			`flag_data : in std_logic_vector( 1 downto 0 ); -- 1 - �� `
95
96			`flag_set : out std_logic_vector( 1 downto 0 ); -- 1 - �� `
97			`flag_clr : out std_logic_vector( 1 downto 0 ); -- 1 - �� `
98			`next_block : in std_logic; -- 1 - �� 4 ��`
99			`adr_hi_wr : out std_logic; -- 1 - �� `
100
101			`reg_ctrl : in std_logic_vector( 7 downto 0 ); -- �� `
102
103			`dmar : in std_logic; -- 1 - �� DMA`
104
105			`pf_cb : out std_logic; -- �� `
106			`pf_dma_wr_rdy : out std_logic; -- 1 - �� 128 ��`
107			`pf_dma_rd_rdy : out std_logic; -- 1 - �� 128 ��`
108
109			`pf_ram_rd : in std_logic; -- 1 - �� `
110			`pf_repack_we : in std_logic -- 1 - �� `
111
112
113			`);`
114			`end ctrl_ram_cmd_pb;`
115
116
117			`architecture ctrl_ram_cmd_pb of ctrl_ram_cmd_pb is`
118
119			`type stp_type is ( s0, s2, sr2, sr5, sr6, sw2, sw3 ); -- s1, sr0, sr1,`
120			`signal stp : stp_type;`
121
122			`signal rst_p : std_logic;`
123			`signal rst_p0 : std_logic;`
124
125			`signal cb : std_logic;`
126
127			`signal block_rd_eot : std_logic;`
128			`--signal block_wr_eot : std_logic;`
129			`signal pf_repack_we_z : std_logic;`
130			`signal pf_ram_rd_z : std_logic;`
131
132			`signal start_rd : std_logic;`
133			`signal start_wr : std_logic;`
134			`signal dmari : std_logic;`
135
136			`signal start_rd0 : std_logic;`
137			`signal start_wr0 : std_logic;`
138
139			`signal start_rd1 : std_logic;`
140			`signal start_wr1 : std_logic;`
141
142			`signal flag0_set : std_logic_vector( 1 downto 0 );`
143			`signal flag1_set : std_logic_vector( 1 downto 0 );`
144			`signal flag2_set : std_logic_vector( 1 downto 0 );`
145
146			`signal flag0_clr : std_logic_vector( 1 downto 0 );`
147			`signal flag1_clr : std_logic_vector( 1 downto 0 );`
148			`signal flag2_clr : std_logic_vector( 1 downto 0 );`
149			`signal local_adr_rdy : std_logic; -- 1 - �� `
150
151
152
153			`attribute tig : string;`
154			`attribute tig of flag2_set : signal is "";`
155			`attribute tig of flag2_clr : signal is "";`
156			`attribute tig of start_rd0 : signal is "";`
157			`attribute tig of start_wr0 : signal is "";`
158
159			`begin`
160
161			`rst_p0 <= (not reset) or reg_ctrl(4) after 1 ns when rising_edge( aclk );`
162			`rst_p <= rst_p0 after 1 ns when rising_edge( aclk );`
163
164			`pf_cb <= cb;`
165
166			`pf_repack_we_z <= pf_repack_we after 1 ns when rising_edge( aclk );`
167			`--block_rd_eot <= '1' when pf_repack_we='0' and pf_repack_we_z='1' else '0';`
168			`block_rd_eot <= next_block after 1 ns when rising_edge( aclk );`
169
170			`pf_ram_rd_z <= pf_ram_rd after 1 ns when rising_edge( aclk );`
171			`--block_wr_eot <= '1' when pf_ram_rd='0' and pf_ram_rd_z='1' else '0';`
172
173			`dmari <= dmar or not reg_ctrl(1);`
174
175			`pr_local_adr_rdy: process( clk ) begin`
176			`if( rising_edge( clk ) ) then`
177			`if( reg_ctrl(0)='0' ) then`
178			`local_adr_rdy <= '0' after 1 ns;`
179			`elsif( loc_adr_we='1' ) then`
180			`local_adr_rdy <= '1' after 1 ns;`
181			`end if;`
182			`end if;`
183			`end process;`
184
185
186			`start_rd0 <= reg_ctrl(0) and reg_ctrl(2) and dmari and not flag_data( conv_integer(cb) ) and local_adr_rdy after 1 ns when rising_edge( aclk );`
187			`start_wr0 <= reg_ctrl(0) and (not reg_ctrl(2)) and dmari and flag_data( conv_integer(cb) ) and local_adr_rdy after 1 ns when rising_edge( aclk ) ;`
188
189
190			`start_rd1 <= start_rd0 after 1 ns when rising_edge( aclk );`
191			`start_wr1 <= start_wr0 after 1 ns when rising_edge( aclk );`
192
193			`start_rd <= act and start_rd1;`
194			`start_wr <= act and start_wr1;`
195
196			`pr_state: process( aclk ) begin`
197			`if( rising_edge( aclk ) ) then`
198
199			`case( stp ) is`
200
201			`when s0 =>`
202			`flag0_set(0) <= '0' after 1 ns;`
203			`flag0_set(1) <= '0' after 1 ns;`
204			`flag0_clr(0) <= '0' after 1 ns;`
205			`flag0_clr(1) <= '0' after 1 ns;`
206			`adr_hi_wr <= '0' after 1 ns;`
207
208			`pf_dma_wr_rdy <= '0' after 1 ns;`
209			`pf_dma_rd_rdy <= '0' after 1 ns;`
210
211			`rdy <= '0' after 1 ns;`
212			`if( start_rd='1' ) then`
213			`pf_dma_rd_rdy <= '1' after 1 ns;`
214			`stp <= sr2 after 1ns;`
215			`elsif( start_wr='1' ) then`
216			`pf_dma_wr_rdy <= '1' after 1 ns;`
217			`stp <= sw2 after 1 ns;`
218			`elsif( act='1' ) then`
219			`stp <= s2 after 1 ns;`
220			`end if;`
221
222
223
224			`when s2 => --- �� DMA �� ----`
225			`rdy <= '1' after 1 ns;`
226			`--cb <= '0';`
227			`if( act='0' ) then`
228			`stp <= s0 after 1 ns;`
229			`end if;`
230
231
232
233			`when sr2 =>`
234			`-- if( pf_repack_we_z='1' ) then`
235			`-- pf_dma_rd_rdy <= '0' after 1 ns;`
236			`-- end if;`
237			`if( block_rd_eot='1' ) then`
238			`stp <= sr5 after 1 ns;`
239			`end if;`
240
241
242			`when sr5 =>`
243			`pf_dma_rd_rdy <= '0' after 1 ns;`
244			`--flag_set(conv_integer(cb)) <= '1' after 1 ns;`
245			`flag0_set(0) <= not cb after 1 ns;`
246			`flag0_set(1) <= cb after 1 ns;`
247
248			`--`
249			`-- flag0_set(0) <= next_block and not cb after 1 ns;`
250			`-- flag0_set(1) <= next_block and cb after 1 ns;`
251			`-- if( next_block='1' ) then`
252			`-- cb <= not cb after 1 ns;`
253			`-- end if;`
254			`cb <= not cb after 1 ns;`
255			`stp <= sr6 after 1 ns;`
256			`adr_hi_wr <= '1' after 1 ns;`
257
258			`when sr6 =>`
259			`adr_hi_wr <= '0' after 1 ns;`
260			`flag0_set(0) <= '0' after 1 ns;`
261			`flag0_set(1) <= '0' after 1 ns;`
262			`flag0_clr(0) <= '0' after 1 ns;`
263			`flag0_clr(1) <= '0' after 1 ns;`
264			`rdy <= '1' after 1 ns;`
265			`if( act='0' ) then`
266			`stp <= s0 after 1 ns;`
267			`end if;`
268
269			`when sw2 =>`
270			`-- if( pf_ram_rd='1' ) then`
271			`-- pf_dma_wr_rdy <= '0' after 1 ns;`
272			`-- end if;`
273			`if( block_rd_eot='1' ) then`
274			`stp <= sw3 after 1 ns;`
275			`end if;`
276
277			`when sw3 =>`
278			`pf_dma_wr_rdy <= '0' after 1 ns;`
279			`flag0_clr(0) <= not cb after 1 ns;`
280			`flag0_clr(1) <= cb after 1 ns;`
281			`-- if( next_block='1' ) then`
282			`-- cb <= not cb after 1 ns;`
283			`-- end if;`
284			`cb <= not cb after 1 ns;`
285			`stp <= sr6 after 1 ns;`
286			`adr_hi_wr <= '1' after 1 ns;`
287
288
289
290			`end case;`
291
292
293			`if( rst_p='1' ) then`
294			`stp <= s0 after 1 ns;`
295			`cb <= '0' after 1 ns;`
296			`rdy <= act after 1 ns;`
297			`end if;`
298
299
300			`end if;`
301			`end process;`
302
303			`gen_flag: for ii in 0 to 1 generate`
304
305			`pr_flag1_set: process( flag0_set(ii), clk ) begin`
306
307			`if( flag0_set(ii)='1' ) then`
308			`flag1_set(ii) <= '1' after 1 ns;`
309			`elsif( rising_edge( clk ) ) then`
310			`if( flag2_set(ii)='1' or rst_p='1' ) then`
311			`flag1_set(ii) <= '0' after 1 ns;`
312			`end if;`
313			`end if;`
314
315			`end process;`
316
317			`pr_flag1_clr: process( flag0_clr(ii), clk ) begin`
318
319			`if( flag0_clr(ii)='1' or rst_p='1' ) then`
320			`flag1_clr(ii) <= '1' after 1 ns;`
321			`elsif( rising_edge( clk ) ) then`
322			`if( flag2_clr(ii)='1' ) then`
323			`flag1_clr(ii) <= '0' after 1 ns;`
324			`end if;`
325			`end if;`
326
327			`end process;`
328
329			`end generate;`
330
331			`flag2_set <= flag1_set after 1 ns when rising_edge( clk );`
332			`flag2_clr <= flag1_clr after 1 ns when rising_edge( clk );`
333
334			`flag_set <= flag1_set;`
335			`flag_clr <= flag1_clr;`
336
337
338			`end ctrl_ram_cmd_pb;`