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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [bram_common.v] - Blame information for rev 2

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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project    : V5-Block Plus for PCI Express
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// File       : bram_common.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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module bram_common #
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(
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   parameter NUM_BRAMS = 16,
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   parameter ADDR_WIDTH = 13,
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   parameter READ_LATENCY = 3,
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   parameter WRITE_LATENCY = 1,
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   parameter WRITE_PIPE = 0,
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   parameter READ_ADDR_PIPE = 0,
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   parameter READ_DATA_PIPE = 0,
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   parameter BRAM_OREG = 1 //parameter to enable use of output register on BRAM
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)
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(
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   input                         clka, // Port A Clk,  
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   input                         ena,  // Port A enable
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   input                         wena, // read/write enable
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   input    [63:0]               dina, // Port A Write data 
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   output   [63:0]               douta,// Port A Write data 
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   input    [ADDR_WIDTH - 1:0]   addra,// Write Address for TL RX Buffers,
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   input                         clkb, // Port B Clk,  
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   input                         enb,  // Port B enable
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   input                         wenb, // read/write enable
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   input    [63:0]               dinb, // Port B Write data 
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   output   [63:0]               doutb,// Port B Write data 
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   input    [ADDR_WIDTH - 1:0]   addrb // Write Address for TL RX Buffers,
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);
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   // width of the BRAM: used bits
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   localparam BRAM_WIDTH = 64/NUM_BRAMS;
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   // unused bits of the databus
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   localparam UNUSED_DATA = 32 - BRAM_WIDTH;
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   parameter UNUSED_ADDR = (BRAM_WIDTH == 64) ? 6: (BRAM_WIDTH == 32)
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                                              ? 5: (BRAM_WIDTH == 16)
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                                              ? 4: (BRAM_WIDTH == 8)
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                                              ? 3: (BRAM_WIDTH == 4)
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                                              ? 2: (BRAM_WIDTH == 2)
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                                              ? 1:0;
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    parameter BRAM_WIDTH_PARITY = (BRAM_WIDTH == 32) ? 36: (BRAM_WIDTH == 16)? 18: (BRAM_WIDTH == 8)? 9: BRAM_WIDTH;
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   //used address bits. This will be used to determine the slice of the 
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   //address bits from the upper level
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   localparam USED_ADDR = 15 - UNUSED_ADDR;
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   wire [31:0]ex_dat_a = 32'b0;
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   wire [31:0]ex_dat_b = 32'b0;
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    generate
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    genvar i;
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    if (NUM_BRAMS == 1)
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        begin: generate_sdp
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        // single BRAM implies Simple Dual Port and width of 64
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        RAMB36SDP
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        #(
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            .DO_REG (BRAM_OREG)
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        )
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        ram_sdp_inst
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        (
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            .DI (dina),
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            .WRADDR (addra[8:0]),
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            .WE ({8{wena}}),
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            .WREN (ena),
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            .WRCLK (clka),
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            .DO (doutb),
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            .RDADDR (addrb[8:0]),
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            .RDEN (enb),
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            .REGCE (1'b1),
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            .SSR (1'b0),
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            .RDCLK (clkb),
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            .DIP (8'h00),
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            .DBITERR(),
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            .SBITERR(),
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            .DOP(),
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            .ECCPARITY()
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        );
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        end
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    else  if (NUM_BRAMS ==2)
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    for (i=0; i < NUM_BRAMS; i = i+1)
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            begin:generate_tdp2
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            RAMB36
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            #(
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                .READ_WIDTH_A (BRAM_WIDTH_PARITY),
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                .WRITE_WIDTH_A (BRAM_WIDTH_PARITY),
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                .READ_WIDTH_B (BRAM_WIDTH_PARITY),
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                .WRITE_WIDTH_B (BRAM_WIDTH_PARITY),
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                .WRITE_MODE_A("READ_FIRST"),
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                .WRITE_MODE_B("READ_FIRST"),
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                .DOB_REG (BRAM_OREG)
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            )
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            ram_tdp2_inst
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            (
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                .DOA       (douta[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
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                .DIA       (dina[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
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                .ADDRA     ({ 1'b0, addra[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
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                .WEA       ({4{wena}}),
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                .ENA       (ena),
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                .CLKA      (clka),
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                .DOB       (doutb[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
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                .DIB       (dinb [(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
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                .ADDRB     ({ 1'b0, addrb[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
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                .WEB       (4'b0),
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                .ENB       (enb),
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                .REGCEB    (1'b1),
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                .REGCEA    (1'b1),
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        //        .REGCLKB   (clkb),
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                .SSRA      (1'b0),
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                .SSRB      (1'b0),
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                .CLKB      (clkb)
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            );
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            end
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    else
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    for (i=0; i < NUM_BRAMS; i = i+1)
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        begin:generate_tdp
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        RAMB36
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        #(
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            .READ_WIDTH_A (BRAM_WIDTH_PARITY),
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            .WRITE_WIDTH_A (BRAM_WIDTH_PARITY),
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            .READ_WIDTH_B (BRAM_WIDTH_PARITY),
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            .WRITE_WIDTH_B (BRAM_WIDTH_PARITY),
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            .WRITE_MODE_A("READ_FIRST"),
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            .WRITE_MODE_B("READ_FIRST"),
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            .DOB_REG (BRAM_OREG)
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        )
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        ram_tdp_inst
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        (
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            .DOA       ({ ex_dat_a[UNUSED_DATA-1:0], douta[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
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            .DIA       ({ {UNUSED_DATA{1'b0}} ,dina[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
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            .ADDRA     ({ 1'b0, addra[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
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            .WEA       ({4{wena}}),
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            .ENA       (ena),
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            .CLKA      (clka),
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            .DOB       ({ ex_dat_b[UNUSED_DATA-1:0], doutb[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
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            .DIB       ({ {UNUSED_DATA{1'b0}}, dinb [(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
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            .ADDRB     ({ 1'b0, addrb[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
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            .WEB       (4'b0),
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            .ENB       (enb),
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            .REGCEB    (1'b1),
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            .REGCEA    (1'b1),
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           // .REGCLKB   (clkb),
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            .SSRA      (1'b0),
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            .SSRB      (1'b0),
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            .CLKB      (clkb)
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        );
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        end
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   endgenerate
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endmodule

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