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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : cmm_decoder.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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module cmm_decoder (
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raddr,
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rmem32,
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rmem64,
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rio,
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rcheck_bus_id,
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rcheck_dev_id,
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63 |
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rcheck_fun_id,
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64 |
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65 |
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rhit,
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bar_hit,
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cmmt_rbar_hit_lat2_n,
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68 |
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69 |
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command,
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bar0_reg,
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bar1_reg,
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bar2_reg,
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bar3_reg,
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bar4_reg,
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bar5_reg,
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xrom_reg,
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pme_pmcsr,
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bus_num,
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device_num,
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function_num,
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phantom_functions_supported,
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phantom_functions_enabled,
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cfg,
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rst,
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clk
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);
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parameter Tcq = 1;
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input [63:0] raddr;
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input rmem32;
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input rmem64;
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input rio;
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input rcheck_bus_id;
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input rcheck_dev_id;
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input rcheck_fun_id;
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output rhit;
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output [6:0] bar_hit;
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output cmmt_rbar_hit_lat2_n;
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input [15:0] command;
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input [31:0] bar0_reg;
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input [31:0] bar1_reg;
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input [31:0] bar2_reg;
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input [31:0] bar3_reg;
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input [31:0] bar4_reg;
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input [31:0] bar5_reg;
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input [31:0] xrom_reg;
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input [15:0] pme_pmcsr;
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input [7:0] bus_num;
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input [4:0] device_num;
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input [2:0] function_num;
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input [671:0] cfg;
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input rst;
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input clk;
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input [1:0] phantom_functions_supported;
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input phantom_functions_enabled;
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reg rhit;
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reg [6:0] bar_hit;
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reg cmmt_rbar_hit_lat2_n;
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wire allow_mem;
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wire allow_io;
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wire bar01_64;
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wire bar12_64;
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129 |
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wire bar23_64;
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wire bar34_64;
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wire bar45_64;
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assign allow_mem = command[1] & !pme_pmcsr[1] & !pme_pmcsr[0];
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assign allow_io = command[0] & !pme_pmcsr[1] & !pme_pmcsr[0];
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// 64 bit programmability built into bar registers
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assign bar01_64 = (bar0_reg[2:0] == 3'b100);
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assign bar12_64 = (bar1_reg[2:0] == 3'b100);
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assign bar23_64 = (bar2_reg[2:0] == 3'b100);
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assign bar34_64 = (bar3_reg[2:0] == 3'b100);
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assign bar45_64 = (bar4_reg[2:0] == 3'b100);
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// 32 bits bar hits
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wire bar0_32_hit;
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wire bar1_32_hit;
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wire bar2_32_hit;
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wire bar3_32_hit;
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wire bar4_32_hit;
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wire bar5_32_hit;
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wire bar6_32_hit;
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reg bar0_32_hit_nc;
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reg bar1_32_hit_nc;
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reg bar2_32_hit_nc;
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reg bar3_32_hit_nc;
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reg bar4_32_hit_nc;
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reg bar5_32_hit_nc;
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reg bar6_32_hit_nc;
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reg bar0_eq_raddr;
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reg bar1_eq_raddr;
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reg bar2_eq_raddr;
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reg bar3_eq_raddr;
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reg bar4_eq_raddr;
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reg bar5_eq_raddr;
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reg bar6_eq_raddr;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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bar0_eq_raddr <= #Tcq 0;
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bar1_eq_raddr <= #Tcq 0;
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bar2_eq_raddr <= #Tcq 0;
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bar3_eq_raddr <= #Tcq 0;
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bar4_eq_raddr <= #Tcq 0;
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bar5_eq_raddr <= #Tcq 0;
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bar6_eq_raddr <= #Tcq 0;
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bar0_32_hit_nc <= #Tcq 0;
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bar1_32_hit_nc <= #Tcq 0;
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bar2_32_hit_nc <= #Tcq 0;
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bar3_32_hit_nc <= #Tcq 0;
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bar4_32_hit_nc <= #Tcq 0;
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bar5_32_hit_nc <= #Tcq 0;
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bar6_32_hit_nc <= #Tcq 0;
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end
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else begin
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bar0_eq_raddr <= #Tcq ((raddr[63:36] & cfg[95:68]) == bar0_reg[31:4]);
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bar1_eq_raddr <= #Tcq ((raddr[63:36] & cfg[127:100]) == bar1_reg[31:4]);
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bar2_eq_raddr <= #Tcq ((raddr[63:36] & cfg[159:132]) == bar2_reg[31:4]);
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bar3_eq_raddr <= #Tcq ((raddr[63:36] & cfg[191:164]) == bar3_reg[31:4]);
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bar4_eq_raddr <= #Tcq ((raddr[63:36] & cfg[223:196]) == bar4_reg[31:4]);
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bar5_eq_raddr <= #Tcq ((raddr[63:36] & cfg[255:228]) == bar5_reg[31:4]);
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bar6_eq_raddr <= #Tcq ((raddr[63:43] & cfg[351:331]) == xrom_reg[31:11]);
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bar0_32_hit_nc <= #Tcq ((rmem32 & allow_mem & !cfg[64]) | (rio & allow_io & cfg[64])) & (|cfg[95:64]) &
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(!bar01_64 | (bar01_64 && (bar1_reg == 0)));
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bar1_32_hit_nc <= #Tcq ((rmem32 & allow_mem & !cfg[96]) | (rio & allow_io & cfg[96])) & (|cfg[127:96]) &
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(!bar12_64 | (bar12_64 && (bar2_reg == 0))) & (!bar01_64);
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bar2_32_hit_nc <= #Tcq ((rmem32 & allow_mem & !cfg[128]) | (rio & allow_io & cfg[128])) & (|cfg[159:128]) &
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(!bar23_64 | (bar23_64 && (bar3_reg == 0))) & (!bar12_64);
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bar3_32_hit_nc <= #Tcq ((rmem32 & allow_mem & !cfg[160]) | (rio & allow_io & cfg[160])) & (|cfg[191:160]) &
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(!bar34_64 | (bar34_64 && (bar4_reg == 0))) & (!bar23_64);
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bar4_32_hit_nc <= #Tcq ((rmem32 & allow_mem & !cfg[192]) | (rio & allow_io & cfg[192])) & (|cfg[224:192]) &
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(!bar45_64 | (bar45_64 && (bar5_reg == 0))) & (!bar34_64);
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bar5_32_hit_nc <= #Tcq (((rmem32 & allow_mem & !cfg[224]) | (rio & allow_io & cfg[224])) & (|cfg[255:224]) &
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!bar45_64);
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bar6_32_hit_nc <= #Tcq (rmem32 & xrom_reg[0] & allow_mem) & |cfg[351:327];
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end
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end
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assign bar0_32_hit = bar0_32_hit_nc & bar0_eq_raddr;
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assign bar1_32_hit = bar1_32_hit_nc & bar1_eq_raddr;
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assign bar2_32_hit = bar2_32_hit_nc & bar2_eq_raddr;
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assign bar3_32_hit = bar3_32_hit_nc & bar3_eq_raddr;
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assign bar4_32_hit = bar4_32_hit_nc & bar4_eq_raddr;
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assign bar5_32_hit = bar5_32_hit_nc & bar5_eq_raddr;
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assign bar6_32_hit = bar6_32_hit_nc & bar6_eq_raddr;
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// 64 bit bar hits
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reg bar01_64_hit_low;
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reg bar12_64_hit_low;
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reg bar23_64_hit_low;
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reg bar34_64_hit_low;
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reg bar45_64_hit_low;
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reg bar01_64_hit_high;
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reg bar12_64_hit_high;
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reg bar23_64_hit_high;
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reg bar34_64_hit_high;
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reg bar45_64_hit_high;
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wire bar01_64_hit;
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wire bar12_64_hit;
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wire bar23_64_hit;
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wire bar34_64_hit;
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wire bar45_64_hit;
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assign bar01_64_hit = bar01_64_hit_low && bar01_64_hit_high;
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assign bar12_64_hit = bar12_64_hit_low && bar12_64_hit_high;
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assign bar23_64_hit = bar23_64_hit_low && bar23_64_hit_high;
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assign bar34_64_hit = bar34_64_hit_low && bar34_64_hit_high;
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assign bar45_64_hit = bar45_64_hit_low && bar45_64_hit_high;
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always @(posedge clk or posedge rst) begin
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252 |
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if (rst) begin
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bar01_64_hit_low <= #Tcq 0;
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bar01_64_hit_high <= #Tcq 0;
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255 |
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bar12_64_hit_low <= #Tcq 0;
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256 |
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bar12_64_hit_high <= #Tcq 0;
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257 |
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bar23_64_hit_low <= #Tcq 0;
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258 |
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bar23_64_hit_high <= #Tcq 0;
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259 |
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bar34_64_hit_low <= #Tcq 0;
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260 |
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bar34_64_hit_high <= #Tcq 0;
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bar45_64_hit_low <= #Tcq 0;
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262 |
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bar45_64_hit_high <= #Tcq 0;
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end
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else begin
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265 |
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bar01_64_hit_low <= #Tcq (rmem64 & allow_mem) & ((raddr[63:32] & cfg[127:96]) == bar1_reg[31:0]) & |cfg[127:96];
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bar01_64_hit_high <= #Tcq ((raddr[31:4] & cfg[95:68]) == bar0_reg[31:4]) & bar01_64 & |cfg[95:64];
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267 |
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268 |
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bar12_64_hit_low <= #Tcq (rmem64 & allow_mem) & ((raddr[63:32] & cfg[159:128]) == bar2_reg[31:0]) & |cfg[159:128];
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bar12_64_hit_high <= #Tcq ((raddr[31:4] & cfg[127:100]) == bar1_reg[31:4]) & bar12_64 & |cfg[127:96];
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270 |
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271 |
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bar23_64_hit_low <= #Tcq (rmem64 & allow_mem) & ((raddr[63:32] & cfg[191:160]) == bar3_reg[31:0]) & |cfg[191:160];
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272 |
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bar23_64_hit_high <= #Tcq ((raddr[31:4] & cfg[159:132]) == bar2_reg[31:4]) & bar23_64 & |cfg[159:128];
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273 |
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274 |
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bar34_64_hit_low <= #Tcq (rmem64 & allow_mem) & ((raddr[63:32] & cfg[223:192]) == bar4_reg[31:0]) & |cfg[223:192];
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275 |
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bar34_64_hit_high <= #Tcq ((raddr[31:4] & cfg[191:164]) == bar3_reg[31:4]) & bar34_64 & |cfg[191:160];
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276 |
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277 |
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bar45_64_hit_low <= #Tcq (rmem64 & allow_mem) & ((raddr[63:32] & cfg[255:224]) == bar5_reg[31:0]) & |cfg[255:224];
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278 |
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bar45_64_hit_high <= #Tcq ((raddr[31:4] & cfg[223:196]) == bar4_reg[31:4]) & bar45_64 & |cfg[223:192];
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279 |
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end
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280 |
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end
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281 |
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|
282 |
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// bdf hit
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283 |
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|
284 |
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reg bdf_hit;
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285 |
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reg bdf_check;
|
286 |
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reg phantom_function_check;
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287 |
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288 |
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always @* begin
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289 |
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casex ({phantom_functions_enabled, phantom_functions_supported})
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290 |
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3'b0xx : phantom_function_check = (function_num[2:0] == raddr[50:48]);
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291 |
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3'b100 : phantom_function_check = (function_num[2:0] == raddr[50:48]);
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292 |
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3'b101 : phantom_function_check = (function_num[1:0] == raddr[49:48]);
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293 |
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3'b110 : phantom_function_check = (function_num[0] == raddr[48]);
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294 |
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3'b111 : phantom_function_check = 1;
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295 |
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default: phantom_function_check = (function_num[2:0] == raddr[50:48]);
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296 |
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endcase
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297 |
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end
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298 |
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299 |
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always @(posedge clk or posedge rst)
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300 |
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begin
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301 |
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if (rst) begin
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302 |
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bdf_hit <= #Tcq 0;
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303 |
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bdf_check <= #Tcq 0;
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304 |
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end else begin
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305 |
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bdf_hit <= #Tcq ({bus_num,device_num} == raddr[63:51]) && phantom_function_check;
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306 |
|
|
bdf_check <= #Tcq rcheck_bus_id | rcheck_dev_id | rcheck_fun_id;
|
307 |
|
|
end
|
308 |
|
|
end
|
309 |
|
|
|
310 |
|
|
|
311 |
|
|
always@(posedge clk or posedge rst)
|
312 |
|
|
begin
|
313 |
|
|
if (rst) begin
|
314 |
|
|
rhit <= #Tcq 0;
|
315 |
|
|
end
|
316 |
|
|
else begin
|
317 |
|
|
rhit <= #Tcq (bdf_hit && bdf_check) | bar01_64_hit | bar12_64_hit |
|
318 |
|
|
bar23_64_hit | bar34_64_hit | bar45_64_hit |
|
319 |
|
|
bar0_32_hit | bar1_32_hit | bar2_32_hit | bar3_32_hit |
|
320 |
|
|
bar4_32_hit | bar5_32_hit | bar6_32_hit;
|
321 |
|
|
end
|
322 |
|
|
end
|
323 |
|
|
|
324 |
|
|
always@(posedge clk or posedge rst)
|
325 |
|
|
begin
|
326 |
|
|
if (rst) begin
|
327 |
|
|
bar_hit[6:0] <= #Tcq 6'b000000;
|
328 |
|
|
cmmt_rbar_hit_lat2_n <= #Tcq 0;
|
329 |
|
|
end
|
330 |
|
|
else begin
|
331 |
|
|
bar_hit[0] <= #Tcq bar0_32_hit | bar01_64_hit;
|
332 |
|
|
bar_hit[1] <= #Tcq bar1_32_hit | bar12_64_hit | bar01_64_hit;
|
333 |
|
|
bar_hit[2] <= #Tcq bar2_32_hit | bar23_64_hit | bar12_64_hit;
|
334 |
|
|
bar_hit[3] <= #Tcq bar3_32_hit | bar34_64_hit | bar23_64_hit;
|
335 |
|
|
bar_hit[4] <= #Tcq bar4_32_hit | bar45_64_hit | bar34_64_hit;
|
336 |
|
|
bar_hit[5] <= #Tcq bar5_32_hit | bar45_64_hit;
|
337 |
|
|
bar_hit[6] <= #Tcq bar6_32_hit ;
|
338 |
|
|
cmmt_rbar_hit_lat2_n <= #Tcq 0;
|
339 |
|
|
end
|
340 |
|
|
end
|
341 |
|
|
|
342 |
|
|
endmodule
|