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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [cmm_decoder.v] - Blame information for rev 2

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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
12
// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
16
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
19
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project    : V5-Block Plus for PCI Express
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// File       : cmm_decoder.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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56
module cmm_decoder (
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                raddr,
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                rmem32,
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                rmem64,
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                rio,
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                rcheck_bus_id,
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                rcheck_dev_id,
63
                rcheck_fun_id,
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65
                rhit,
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                bar_hit,
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                cmmt_rbar_hit_lat2_n,
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69
                command,
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                bar0_reg,
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                bar1_reg,
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                bar2_reg,
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                bar3_reg,
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                bar4_reg,
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                bar5_reg,
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                xrom_reg,
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                pme_pmcsr,
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79
                bus_num,
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                device_num,
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                function_num,
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                phantom_functions_supported,
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                phantom_functions_enabled,
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                cfg,
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                rst,
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                clk
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                );
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91
  parameter Tcq = 1;
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93
  input  [63:0] raddr;
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  input         rmem32;
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  input         rmem64;
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  input         rio;
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  input         rcheck_bus_id;
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  input         rcheck_dev_id;
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  input         rcheck_fun_id;
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  output        rhit;
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  output [6:0]  bar_hit;
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  output        cmmt_rbar_hit_lat2_n;
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  input  [15:0] command;
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  input  [31:0] bar0_reg;
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  input  [31:0] bar1_reg;
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  input  [31:0] bar2_reg;
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  input  [31:0] bar3_reg;
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  input  [31:0] bar4_reg;
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  input  [31:0] bar5_reg;
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  input  [31:0] xrom_reg;
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  input  [15:0] pme_pmcsr;
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  input   [7:0] bus_num;
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  input   [4:0] device_num;
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  input   [2:0] function_num;
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  input [671:0] cfg;
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  input         rst;
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  input         clk;
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  input   [1:0] phantom_functions_supported;
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  input         phantom_functions_enabled;
120
 
121
  reg        rhit;
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  reg [6:0]  bar_hit;
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  reg        cmmt_rbar_hit_lat2_n;
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125
wire allow_mem;
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wire allow_io;
127
wire bar01_64;
128
wire bar12_64;
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wire bar23_64;
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wire bar34_64;
131
wire bar45_64;
132
 
133
assign allow_mem = command[1] & !pme_pmcsr[1] & !pme_pmcsr[0];
134
assign allow_io = command[0] & !pme_pmcsr[1] & !pme_pmcsr[0];
135
 
136
// 64 bit programmability built into bar registers
137
 
138
assign bar01_64 = (bar0_reg[2:0] == 3'b100);
139
assign bar12_64 = (bar1_reg[2:0] == 3'b100);
140
assign bar23_64 = (bar2_reg[2:0] == 3'b100);
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assign bar34_64 = (bar3_reg[2:0] == 3'b100);
142
assign bar45_64 = (bar4_reg[2:0] == 3'b100);
143
 
144
// 32 bits bar hits
145
 
146
wire bar0_32_hit;
147
wire bar1_32_hit;
148
wire bar2_32_hit;
149
wire bar3_32_hit;
150
wire bar4_32_hit;
151
wire bar5_32_hit;
152
wire bar6_32_hit;
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reg  bar0_32_hit_nc;
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reg  bar1_32_hit_nc;
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reg  bar2_32_hit_nc;
156
reg  bar3_32_hit_nc;
157
reg  bar4_32_hit_nc;
158
reg  bar5_32_hit_nc;
159
reg  bar6_32_hit_nc;
160
reg  bar0_eq_raddr;
161
reg  bar1_eq_raddr;
162
reg  bar2_eq_raddr;
163
reg  bar3_eq_raddr;
164
reg  bar4_eq_raddr;
165
reg  bar5_eq_raddr;
166
reg  bar6_eq_raddr;
167
 
168
always @(posedge clk or posedge rst) begin
169
   if (rst) begin
170
      bar0_eq_raddr  <= #Tcq 0;
171
      bar1_eq_raddr  <= #Tcq 0;
172
      bar2_eq_raddr  <= #Tcq 0;
173
      bar3_eq_raddr  <= #Tcq 0;
174
      bar4_eq_raddr  <= #Tcq 0;
175
      bar5_eq_raddr  <= #Tcq 0;
176
      bar6_eq_raddr  <= #Tcq 0;
177
      bar0_32_hit_nc <= #Tcq  0;
178
      bar1_32_hit_nc <= #Tcq  0;
179
      bar2_32_hit_nc <= #Tcq  0;
180
      bar3_32_hit_nc <= #Tcq  0;
181
      bar4_32_hit_nc <= #Tcq  0;
182
      bar5_32_hit_nc <= #Tcq  0;
183
      bar6_32_hit_nc <= #Tcq  0;
184
   end
185
   else begin
186
      bar0_eq_raddr <= #Tcq ((raddr[63:36] & cfg[95:68])   == bar0_reg[31:4]);
187
      bar1_eq_raddr <= #Tcq ((raddr[63:36] & cfg[127:100]) == bar1_reg[31:4]);
188
      bar2_eq_raddr <= #Tcq ((raddr[63:36] & cfg[159:132]) == bar2_reg[31:4]);
189
      bar3_eq_raddr <= #Tcq ((raddr[63:36] & cfg[191:164]) == bar3_reg[31:4]);
190
      bar4_eq_raddr <= #Tcq ((raddr[63:36] & cfg[223:196]) == bar4_reg[31:4]);
191
      bar5_eq_raddr <= #Tcq ((raddr[63:36] & cfg[255:228]) == bar5_reg[31:4]);
192
      bar6_eq_raddr <= #Tcq ((raddr[63:43] & cfg[351:331]) == xrom_reg[31:11]);
193
      bar0_32_hit_nc <= #Tcq  ((rmem32 & allow_mem & !cfg[64]) | (rio & allow_io & cfg[64])) & (|cfg[95:64]) &
194
                            (!bar01_64 | (bar01_64 && (bar1_reg == 0)));
195
 
196
      bar1_32_hit_nc <= #Tcq  ((rmem32 & allow_mem & !cfg[96]) | (rio & allow_io & cfg[96])) & (|cfg[127:96]) &
197
                            (!bar12_64 | (bar12_64 && (bar2_reg == 0))) & (!bar01_64);
198
 
199
      bar2_32_hit_nc <= #Tcq  ((rmem32 & allow_mem & !cfg[128]) | (rio & allow_io & cfg[128])) & (|cfg[159:128]) &
200
                            (!bar23_64 | (bar23_64 && (bar3_reg == 0))) & (!bar12_64);
201
 
202
      bar3_32_hit_nc <= #Tcq  ((rmem32 & allow_mem & !cfg[160]) | (rio & allow_io & cfg[160])) & (|cfg[191:160]) &
203
                            (!bar34_64 | (bar34_64 && (bar4_reg == 0))) & (!bar23_64);
204
 
205
      bar4_32_hit_nc <= #Tcq  ((rmem32 & allow_mem & !cfg[192]) | (rio & allow_io & cfg[192])) & (|cfg[224:192]) &
206
                            (!bar45_64 | (bar45_64 && (bar5_reg == 0))) & (!bar34_64);
207
 
208
      bar5_32_hit_nc <= #Tcq  (((rmem32 & allow_mem & !cfg[224]) | (rio & allow_io & cfg[224])) & (|cfg[255:224]) &
209
                            !bar45_64);
210
 
211
      bar6_32_hit_nc <= #Tcq   (rmem32 & xrom_reg[0] & allow_mem) & |cfg[351:327];
212
   end
213
end
214
 
215
assign  bar0_32_hit = bar0_32_hit_nc & bar0_eq_raddr;
216
assign  bar1_32_hit = bar1_32_hit_nc & bar1_eq_raddr;
217
assign  bar2_32_hit = bar2_32_hit_nc & bar2_eq_raddr;
218
assign  bar3_32_hit = bar3_32_hit_nc & bar3_eq_raddr;
219
assign  bar4_32_hit = bar4_32_hit_nc & bar4_eq_raddr;
220
assign  bar5_32_hit = bar5_32_hit_nc & bar5_eq_raddr;
221
assign  bar6_32_hit = bar6_32_hit_nc & bar6_eq_raddr;
222
 
223
 
224
// 64 bit bar hits
225
 
226
reg   bar01_64_hit_low;
227
reg   bar12_64_hit_low;
228
reg   bar23_64_hit_low;
229
reg   bar34_64_hit_low;
230
reg   bar45_64_hit_low;
231
 
232
reg   bar01_64_hit_high;
233
reg   bar12_64_hit_high;
234
reg   bar23_64_hit_high;
235
reg   bar34_64_hit_high;
236
reg   bar45_64_hit_high;
237
 
238
 
239
wire  bar01_64_hit;
240
wire  bar12_64_hit;
241
wire  bar23_64_hit;
242
wire  bar34_64_hit;
243
wire  bar45_64_hit;
244
 
245
assign  bar01_64_hit = bar01_64_hit_low &&  bar01_64_hit_high;
246
assign  bar12_64_hit = bar12_64_hit_low &&  bar12_64_hit_high;
247
assign  bar23_64_hit = bar23_64_hit_low &&  bar23_64_hit_high;
248
assign  bar34_64_hit = bar34_64_hit_low &&  bar34_64_hit_high;
249
assign  bar45_64_hit = bar45_64_hit_low &&  bar45_64_hit_high;
250
 
251
always @(posedge clk or posedge rst) begin
252
   if (rst) begin
253
      bar01_64_hit_low  <= #Tcq  0;
254
      bar01_64_hit_high <= #Tcq  0;
255
      bar12_64_hit_low  <= #Tcq  0;
256
      bar12_64_hit_high <= #Tcq  0;
257
      bar23_64_hit_low  <= #Tcq  0;
258
      bar23_64_hit_high <= #Tcq  0;
259
      bar34_64_hit_low  <= #Tcq  0;
260
      bar34_64_hit_high <= #Tcq  0;
261
      bar45_64_hit_low  <= #Tcq  0;
262
      bar45_64_hit_high <= #Tcq  0;
263
   end
264
   else begin
265
      bar01_64_hit_low  <= #Tcq  (rmem64 & allow_mem) & ((raddr[63:32] & cfg[127:96]) == bar1_reg[31:0]) & |cfg[127:96];
266
      bar01_64_hit_high <= #Tcq  ((raddr[31:4] & cfg[95:68]) == bar0_reg[31:4]) &  bar01_64 & |cfg[95:64];
267
 
268
      bar12_64_hit_low  <= #Tcq  (rmem64 & allow_mem) & ((raddr[63:32] & cfg[159:128]) == bar2_reg[31:0]) & |cfg[159:128];
269
      bar12_64_hit_high <= #Tcq  ((raddr[31:4] & cfg[127:100]) == bar1_reg[31:4]) &  bar12_64 & |cfg[127:96];
270
 
271
      bar23_64_hit_low  <= #Tcq  (rmem64 & allow_mem) & ((raddr[63:32] & cfg[191:160]) == bar3_reg[31:0]) & |cfg[191:160];
272
      bar23_64_hit_high <= #Tcq  ((raddr[31:4] & cfg[159:132]) == bar2_reg[31:4]) &  bar23_64 & |cfg[159:128];
273
 
274
      bar34_64_hit_low  <= #Tcq  (rmem64 & allow_mem) & ((raddr[63:32] & cfg[223:192]) == bar4_reg[31:0]) & |cfg[223:192];
275
      bar34_64_hit_high <= #Tcq  ((raddr[31:4] & cfg[191:164]) == bar3_reg[31:4]) &  bar34_64 & |cfg[191:160];
276
 
277
      bar45_64_hit_low  <= #Tcq  (rmem64 & allow_mem) & ((raddr[63:32] & cfg[255:224]) == bar5_reg[31:0]) & |cfg[255:224];
278
      bar45_64_hit_high <= #Tcq  ((raddr[31:4] & cfg[223:196]) == bar4_reg[31:4]) &  bar45_64 & |cfg[223:192];
279
   end
280
end
281
 
282
// bdf hit
283
 
284
reg bdf_hit;
285
reg bdf_check;
286
reg phantom_function_check;
287
 
288
always @* begin
289
   casex ({phantom_functions_enabled, phantom_functions_supported})
290
   3'b0xx : phantom_function_check = (function_num[2:0] == raddr[50:48]);
291
   3'b100 : phantom_function_check = (function_num[2:0] == raddr[50:48]);
292
   3'b101 : phantom_function_check = (function_num[1:0] == raddr[49:48]);
293
   3'b110 : phantom_function_check = (function_num[0]   == raddr[48]);
294
   3'b111 : phantom_function_check = 1;
295
   default: phantom_function_check = (function_num[2:0] == raddr[50:48]);
296
   endcase
297
end
298
 
299
always @(posedge clk or posedge rst)
300
begin
301
   if (rst) begin
302
       bdf_hit   <= #Tcq  0;
303
       bdf_check <= #Tcq  0;
304
   end else begin
305
       bdf_hit <= #Tcq  ({bus_num,device_num} == raddr[63:51]) && phantom_function_check;
306
       bdf_check <= #Tcq  rcheck_bus_id | rcheck_dev_id | rcheck_fun_id;
307
   end
308
end
309
 
310
 
311
always@(posedge clk or posedge rst)
312
begin
313
   if (rst) begin
314
      rhit <= #Tcq  0;
315
   end
316
   else begin
317
      rhit <= #Tcq  (bdf_hit && bdf_check) | bar01_64_hit | bar12_64_hit |
318
                 bar23_64_hit | bar34_64_hit | bar45_64_hit |
319
                 bar0_32_hit | bar1_32_hit | bar2_32_hit | bar3_32_hit |
320
                 bar4_32_hit | bar5_32_hit | bar6_32_hit;
321
   end
322
end
323
 
324
always@(posedge clk or posedge rst)
325
begin
326
   if (rst) begin
327
      bar_hit[6:0] <= #Tcq 6'b000000;
328
      cmmt_rbar_hit_lat2_n <= #Tcq 0;
329
   end
330
   else begin
331
      bar_hit[0] <= #Tcq bar0_32_hit | bar01_64_hit;
332
      bar_hit[1] <= #Tcq bar1_32_hit | bar12_64_hit | bar01_64_hit;
333
      bar_hit[2] <= #Tcq bar2_32_hit | bar23_64_hit | bar12_64_hit;
334
      bar_hit[3] <= #Tcq bar3_32_hit | bar34_64_hit | bar23_64_hit;
335
      bar_hit[4] <= #Tcq bar4_32_hit | bar45_64_hit | bar34_64_hit;
336
      bar_hit[5] <= #Tcq bar5_32_hit | bar45_64_hit;
337
      bar_hit[6] <= #Tcq bar6_32_hit ;
338
      cmmt_rbar_hit_lat2_n <= #Tcq 0;
339
   end
340
end
341
 
342
endmodule

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