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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : cmm_errman_cnt_nfl_en.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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/***********************************************************************
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Description:
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This is the error counter module for tracking the outstanding
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completion. When overflow or underflow occurs, it remains at either
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full scale (overflow) or zero (underflow) instead of rolling over.
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***********************************************************************/
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module cmm_errman_cnt_nfl_en (
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count, // Outputs
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index, // Inputs
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inc_dec_b,
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enable,
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rst,
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clk
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);
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output count;
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input index; // ftl_num, nfl_num or cor_num
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input inc_dec_b; // 1 = increment, 0 = decrement
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input enable; // err_*_en
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input rst;
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input clk;
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//******************************************************************//
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// Reality check. //
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//******************************************************************//
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parameter FFD = 1; // clock to out delay model
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//******************************************************************//
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// There are 2 pipeline stages to help timing. //
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// Stage 1: a simple add/subtract accumulator with no overflow or //
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// underflow check. //
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// Stage 2: underflow, overflow and counter enable are handled. //
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//******************************************************************//
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// Stage 1: count up or count down
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reg reg_cnt;
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reg reg_extra;
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reg reg_inc_dec_b;
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reg reg_uflow;
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wire cnt;
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wire oflow;
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wire uflow;
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always @(posedge clk or posedge rst)
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begin
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if (rst) {reg_extra, reg_cnt} <= #FFD 2'b00;
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else if (~enable) {reg_extra, reg_cnt} <= #FFD 2'b00;
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else if (inc_dec_b) {reg_extra, reg_cnt} <= #FFD cnt + index;
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else {reg_extra, reg_cnt} <= #FFD cnt - index;
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end
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assign cnt = oflow ? 1'b1 : (uflow ? 1'b0 : reg_cnt);
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always @(posedge clk or posedge rst)
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begin
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if (rst) reg_inc_dec_b <= #FFD 1'b0;
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else reg_inc_dec_b <= #FFD inc_dec_b;
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end
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assign oflow = reg_extra & reg_inc_dec_b;
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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reg_uflow <= 1'b0;
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else
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reg_uflow <= #FFD ~count & index & ~inc_dec_b;
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end
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assign uflow = reg_uflow;
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// Stage 2: if overflow occurs, the counter is set to full scale;
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// if underflow occurs, it is set to zero.
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// if counter is not enable, it is set to zero.
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reg reg_count;
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always @(posedge clk or posedge rst)
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begin
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if (rst) reg_count <= #FFD 1'b0;
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else if (~enable) reg_count <= #FFD 1'b0;
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else if (oflow) reg_count <= #FFD 1'b1;
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else if (uflow) reg_count <= #FFD 1'b0;
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else reg_count <= #FFD cnt;
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end
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assign count = reg_count;
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//******************************************************************//
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// //
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//******************************************************************//
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endmodule
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