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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [cmm_errman_cor.v] - Blame information for rev 2

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//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project    : V5-Block Plus for PCI Express
// File       : cmm_errman_cor.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
/***********************************************************************
 
  Description:
 
  This module figures out what to do for correctable errors:
    1) count up or count down,
    2) how much to add or to subtract
  It returns the number and a add/subtract_b signals to the error
  tracking counter. The outputs are based on how many errors are
  asserted by the error reporting modules.
 
***********************************************************************/
 
 
module cmm_errman_cor (
                cor_num,                // Output
                inc_dec_b,
                reg_decr_cor,
 
                add_input_one,      // Inputs
                add_input_two_n,
                add_input_three_n,
                add_input_four_n,
                add_input_five_n,
                add_input_six_n,
                decr_cor,
                rst,
                clk
                );
 
 
  output  [2:0] cor_num;
  output        inc_dec_b;              // 1 = increment, 0 = decrement 
  output        reg_decr_cor;
 
  input         add_input_one;
  input         add_input_two_n;
  input         add_input_three_n;
  input         add_input_four_n;
  input         add_input_five_n;
  input         add_input_six_n;
  input         decr_cor;
  input         rst;
  input         clk;
 
 
  //******************************************************************//
  // Reality check.                                                   //
  //******************************************************************//
 
  parameter FFD       = 1;        // clock to out delay model
 
 
  //******************************************************************//
  // Figure out how many errors to increment.                         //
  //******************************************************************//
 
 
  reg     [2:0] to_incr         /* synthesis syn_romstyle = "logic" */;
  reg           add_sub_b       /* synthesis syn_romstyle = "logic" */;
  reg           add_input_one_d;
  reg           add_input_two_n_d;
  reg           add_input_three_n_d;
  reg           add_input_four_n_d;
  reg           add_input_five_n_d;
  reg           add_input_six_n_d;
 
  always @(posedge clk)
  begin
    if (rst) begin
      add_input_one_d     <= #FFD 0;
      add_input_two_n_d   <= #FFD 1;
      add_input_three_n_d <= #FFD 1;
      add_input_four_n_d  <= #FFD 1;
      add_input_five_n_d  <= #FFD 1;
      add_input_six_n_d   <= #FFD 1;
    end else begin
      add_input_one_d     <= #FFD add_input_one;
      add_input_two_n_d   <= #FFD add_input_two_n;
      add_input_three_n_d <= #FFD add_input_three_n;
      add_input_four_n_d  <= #FFD add_input_four_n;
      add_input_five_n_d  <= #FFD add_input_five_n;
      add_input_six_n_d   <= #FFD add_input_six_n;
    end
  end
 
  always @*
  begin
    case ({add_input_six_n_d, add_input_one_d,
           add_input_two_n_d, add_input_three_n_d,
           add_input_four_n_d,  add_input_five_n_d})   // synthesis full_case parallel_case
    6'b00_0000: begin   to_incr  = 3'b101;
                        add_sub_b = 1'b1;
                end
    6'b00_0001: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b00_0010: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b00_0011: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b00_0100: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b00_0101: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b00_0110: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b00_0111: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b00_1000: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b00_1001: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b00_1010: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b00_1011: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b00_1100: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b00_1101: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b00_1110: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b00_1111: begin   to_incr  = 3'b001;
                        add_sub_b = 1'b1;
                end
    6'b01_0000: begin   to_incr  = 3'b110;
                        add_sub_b = 1'b1;
                end
    6'b01_0001: begin   to_incr  = 3'b101;
                        add_sub_b = 1'b1;
                end
    6'b01_0010: begin   to_incr  = 3'b101;
                        add_sub_b = 1'b1;
                end
    6'b01_0011: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b01_0100: begin   to_incr  = 3'b101;
                        add_sub_b = 1'b1;
                end
    6'b01_0101: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b01_0110: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b01_0111: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b01_1000: begin   to_incr  = 3'b101;
                        add_sub_b = 1'b1;
                end
    6'b01_1001: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b01_1010: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b01_1011: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b01_1100: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b01_1101: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b01_1110: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b01_1111: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
 
    6'b10_0000: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b10_0001: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b10_0010: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b10_0011: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b10_0100: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b10_0101: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b10_0110: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b10_0111: begin   to_incr  = 3'b001;
                        add_sub_b = 1'b1;
                end
    6'b10_1000: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b10_1001: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b10_1010: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b10_1011: begin   to_incr  = 3'b001;
                        add_sub_b = 1'b1;
                end
    6'b10_1100: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b10_1101: begin   to_incr  = 3'b001;
                        add_sub_b = 1'b1;
                end
    6'b10_1110: begin   to_incr  = 3'b001;
                        add_sub_b = 1'b1;
                end
    //6'b10_1111: begin   to_incr  = 3'b000; JBG: special case where you add instead
    6'b10_1111: begin   to_incr  = 3'b001;
                        add_sub_b = 1'b1;
                end
    6'b11_0000: begin   to_incr  = 3'b101;
                        add_sub_b = 1'b1;
                end
    6'b11_0001: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b11_0010: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b11_0011: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b11_0100: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b11_0101: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b11_0110: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b11_0111: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b11_1000: begin   to_incr  = 3'b100;
                        add_sub_b = 1'b1;
                end
    6'b11_1001: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b11_1010: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b11_1011: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b11_1100: begin   to_incr  = 3'b011;
                        add_sub_b = 1'b1;
                end
    6'b11_1101: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b11_1110: begin   to_incr  = 3'b010;
                        add_sub_b = 1'b1;
                end
    6'b11_1111: begin   to_incr  = 3'b001;
                        add_sub_b = 1'b1;
                end
    default:  begin   to_incr   = 3'b000;
                      add_sub_b = 1'b1;
              end
    endcase
  end
 
 
  //******************************************************************//
  // Register the outputs.                                            //
  //******************************************************************//
 
 
  reg     [2:0] reg_cor_num;
  reg           reg_inc_dec_b;
  reg           reg_decr_cor;
 
  always @(posedge clk)
  begin
    if (rst)
    begin
      reg_cor_num   <= #FFD 3'b000;   //remove reset to aid timing
      reg_inc_dec_b <= #FFD 1'b0;
      reg_decr_cor  <= #FFD 1'b0;
    end
    else
    begin
      reg_cor_num   <= #FFD to_incr;
 
      reg_inc_dec_b <= #FFD ~(add_input_six_n_d && ~add_input_one_d &&
                              add_input_two_n_d && add_input_three_n_d &&
                              add_input_four_n_d && add_input_five_n_d && decr_cor);
      reg_decr_cor  <= #FFD  (add_input_six_n_d && ~add_input_one_d &&
                              add_input_two_n_d && add_input_three_n_d &&
                              add_input_four_n_d && add_input_five_n_d) ?
                             ~decr_cor : decr_cor;
    end
  end
 
  assign cor_num   = reg_cor_num;
  assign inc_dec_b = reg_inc_dec_b;
 
 
  //******************************************************************//
  //                                                                  //
  //******************************************************************//
 
endmodule

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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [cmm_errman_cor.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dsmv
2			`//-----------------------------------------------------------------------------`
3			`//`
4			`// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.`
5			`//`
6			`// This file contains confidential and proprietary information`
7			`// of Xilinx, Inc. and is protected under U.S. and`
8			`// international copyright and other intellectual property`
9			`// laws.`
10			`//`
11			`// DISCLAIMER`
12			`// This disclaimer is not a license and does not grant any`
13			`// rights to the materials distributed herewith. Except as`
14			`// otherwise provided in a valid license issued to you by`
15			`// Xilinx, and to the maximum extent permitted by applicable`
16			`// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND`
17			`// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES`
18			`// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING`
19			`// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-`
20			`// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and`
21			`// (2) Xilinx shall not be liable (whether in contract or tort,`
22			`// including negligence, or under any other theory of`
23			`// liability) for any loss or damage of any kind or nature`
24			`// related to, arising under or in connection with these`
25			`// materials, including for any direct, or any indirect,`
26			`// special, incidental, or consequential loss or damage`
27			`// (including loss of data, profits, goodwill, or any type of`
28			`// loss or damage suffered as a result of any action brought`
29			`// by a third party) even if such damage or loss was`
30			`// reasonably foreseeable or Xilinx had been advised of the`
31			`// possibility of the same.`
32			`//`
33			`// CRITICAL APPLICATIONS`
34			`// Xilinx products are not designed or intended to be fail-`
35			`// safe, or for use in any application requiring fail-safe`
36			`// performance, such as life-support or safety devices or`
37			`// systems, Class III medical devices, nuclear facilities,`
38			`// applications related to the deployment of airbags, or any`
39			`// other applications that could lead to death, personal`
40			`// injury, or severe property or environmental damage`
41			`// (individually and collectively, "Critical`
42			`// Applications"). Customer assumes the sole risk and`
43			`// liability of any use of Xilinx products in Critical`
44			`// Applications, subject only to applicable laws and`
45			`// regulations governing limitations on product liability.`
46			`//`
47			`// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS`
48			`// PART OF THIS FILE AT ALL TIMES.`
49			`//`
50			`//-----------------------------------------------------------------------------`
51			`// Project : V5-Block Plus for PCI Express`
52			`// File : cmm_errman_cor.v`
53			`//--------------------------------------------------------------------------------`
54			`//--------------------------------------------------------------------------------`
55			`/***********************************************************************`
56
57			`Description:`
58
59			`This module figures out what to do for correctable errors:`
60			`1) count up or count down,`
61			`2) how much to add or to subtract`
62			`It returns the number and a add/subtract_b signals to the error`
63			`tracking counter. The outputs are based on how many errors are`
64			`asserted by the error reporting modules.`
65
66			`***********************************************************************/`
67
68
69			`module cmm_errman_cor (`
70			`cor_num, // Output`
71			`inc_dec_b,`
72			`reg_decr_cor,`
73
74			`add_input_one, // Inputs`
75			`add_input_two_n,`
76			`add_input_three_n,`
77			`add_input_four_n,`
78			`add_input_five_n,`
79			`add_input_six_n,`
80			`decr_cor,`
81			`rst,`
82			`clk`
83			`);`
84
85
86			`output [2:0] cor_num;`
87			`output inc_dec_b; // 1 = increment, 0 = decrement`
88			`output reg_decr_cor;`
89
90			`input add_input_one;`
91			`input add_input_two_n;`
92			`input add_input_three_n;`
93			`input add_input_four_n;`
94			`input add_input_five_n;`
95			`input add_input_six_n;`
96			`input decr_cor;`
97			`input rst;`
98			`input clk;`
99
100
101			`//******************************************************************//`
102			`// Reality check. //`
103			`//******************************************************************//`
104
105			`parameter FFD = 1; // clock to out delay model`
106
107
108			`//******************************************************************//`
109			`// Figure out how many errors to increment. //`
110			`//******************************************************************//`
111
112
113			`reg [2:0] to_incr /* synthesis syn_romstyle = "logic" */;`
114			`reg add_sub_b /* synthesis syn_romstyle = "logic" */;`
115			`reg add_input_one_d;`
116			`reg add_input_two_n_d;`
117			`reg add_input_three_n_d;`
118			`reg add_input_four_n_d;`
119			`reg add_input_five_n_d;`
120			`reg add_input_six_n_d;`
121
122			`always @(posedge clk)`
123			`begin`
124			`if (rst) begin`
125			`add_input_one_d <= #FFD 0;`
126			`add_input_two_n_d <= #FFD 1;`
127			`add_input_three_n_d <= #FFD 1;`
128			`add_input_four_n_d <= #FFD 1;`
129			`add_input_five_n_d <= #FFD 1;`
130			`add_input_six_n_d <= #FFD 1;`
131			`end else begin`
132			`add_input_one_d <= #FFD add_input_one;`
133			`add_input_two_n_d <= #FFD add_input_two_n;`
134			`add_input_three_n_d <= #FFD add_input_three_n;`
135			`add_input_four_n_d <= #FFD add_input_four_n;`
136			`add_input_five_n_d <= #FFD add_input_five_n;`
137			`add_input_six_n_d <= #FFD add_input_six_n;`
138			`end`
139			`end`
140
141			`always @*`
142			`begin`
143			`case ({add_input_six_n_d, add_input_one_d,`
144			`add_input_two_n_d, add_input_three_n_d,`
145			`add_input_four_n_d, add_input_five_n_d}) // synthesis full_case parallel_case`
146			`6'b00_0000: begin to_incr = 3'b101;`
147			`add_sub_b = 1'b1;`
148			`end`
149			`6'b00_0001: begin to_incr = 3'b100;`
150			`add_sub_b = 1'b1;`
151			`end`
152			`6'b00_0010: begin to_incr = 3'b100;`
153			`add_sub_b = 1'b1;`
154			`end`
155			`6'b00_0011: begin to_incr = 3'b011;`
156			`add_sub_b = 1'b1;`
157			`end`
158			`6'b00_0100: begin to_incr = 3'b100;`
159			`add_sub_b = 1'b1;`
160			`end`
161			`6'b00_0101: begin to_incr = 3'b011;`
162			`add_sub_b = 1'b1;`
163			`end`
164			`6'b00_0110: begin to_incr = 3'b011;`
165			`add_sub_b = 1'b1;`
166			`end`
167			`6'b00_0111: begin to_incr = 3'b010;`
168			`add_sub_b = 1'b1;`
169			`end`
170			`6'b00_1000: begin to_incr = 3'b100;`
171			`add_sub_b = 1'b1;`
172			`end`
173			`6'b00_1001: begin to_incr = 3'b011;`
174			`add_sub_b = 1'b1;`
175			`end`
176			`6'b00_1010: begin to_incr = 3'b011;`
177			`add_sub_b = 1'b1;`
178			`end`
179			`6'b00_1011: begin to_incr = 3'b010;`
180			`add_sub_b = 1'b1;`
181			`end`
182			`6'b00_1100: begin to_incr = 3'b011;`
183			`add_sub_b = 1'b1;`
184			`end`
185			`6'b00_1101: begin to_incr = 3'b010;`
186			`add_sub_b = 1'b1;`
187			`end`
188			`6'b00_1110: begin to_incr = 3'b010;`
189			`add_sub_b = 1'b1;`
190			`end`
191			`6'b00_1111: begin to_incr = 3'b001;`
192			`add_sub_b = 1'b1;`
193			`end`
194			`6'b01_0000: begin to_incr = 3'b110;`
195			`add_sub_b = 1'b1;`
196			`end`
197			`6'b01_0001: begin to_incr = 3'b101;`
198			`add_sub_b = 1'b1;`
199			`end`
200			`6'b01_0010: begin to_incr = 3'b101;`
201			`add_sub_b = 1'b1;`
202			`end`
203			`6'b01_0011: begin to_incr = 3'b100;`
204			`add_sub_b = 1'b1;`
205			`end`
206			`6'b01_0100: begin to_incr = 3'b101;`
207			`add_sub_b = 1'b1;`
208			`end`
209			`6'b01_0101: begin to_incr = 3'b100;`
210			`add_sub_b = 1'b1;`
211			`end`
212			`6'b01_0110: begin to_incr = 3'b100;`
213			`add_sub_b = 1'b1;`
214			`end`
215			`6'b01_0111: begin to_incr = 3'b011;`
216			`add_sub_b = 1'b1;`
217			`end`
218			`6'b01_1000: begin to_incr = 3'b101;`
219			`add_sub_b = 1'b1;`
220			`end`
221			`6'b01_1001: begin to_incr = 3'b100;`
222			`add_sub_b = 1'b1;`
223			`end`
224			`6'b01_1010: begin to_incr = 3'b100;`
225			`add_sub_b = 1'b1;`
226			`end`
227			`6'b01_1011: begin to_incr = 3'b011;`
228			`add_sub_b = 1'b1;`
229			`end`
230			`6'b01_1100: begin to_incr = 3'b100;`
231			`add_sub_b = 1'b1;`
232			`end`
233			`6'b01_1101: begin to_incr = 3'b011;`
234			`add_sub_b = 1'b1;`
235			`end`
236			`6'b01_1110: begin to_incr = 3'b011;`
237			`add_sub_b = 1'b1;`
238			`end`
239			`6'b01_1111: begin to_incr = 3'b010;`
240			`add_sub_b = 1'b1;`
241			`end`
242
243			`6'b10_0000: begin to_incr = 3'b100;`
244			`add_sub_b = 1'b1;`
245			`end`
246			`6'b10_0001: begin to_incr = 3'b011;`
247			`add_sub_b = 1'b1;`
248			`end`
249			`6'b10_0010: begin to_incr = 3'b011;`
250			`add_sub_b = 1'b1;`
251			`end`
252			`6'b10_0011: begin to_incr = 3'b010;`
253			`add_sub_b = 1'b1;`
254			`end`
255			`6'b10_0100: begin to_incr = 3'b011;`
256			`add_sub_b = 1'b1;`
257			`end`
258			`6'b10_0101: begin to_incr = 3'b010;`
259			`add_sub_b = 1'b1;`
260			`end`
261			`6'b10_0110: begin to_incr = 3'b010;`
262			`add_sub_b = 1'b1;`
263			`end`
264			`6'b10_0111: begin to_incr = 3'b001;`
265			`add_sub_b = 1'b1;`
266			`end`
267			`6'b10_1000: begin to_incr = 3'b011;`
268			`add_sub_b = 1'b1;`
269			`end`
270			`6'b10_1001: begin to_incr = 3'b010;`
271			`add_sub_b = 1'b1;`
272			`end`
273			`6'b10_1010: begin to_incr = 3'b010;`
274			`add_sub_b = 1'b1;`
275			`end`
276			`6'b10_1011: begin to_incr = 3'b001;`
277			`add_sub_b = 1'b1;`
278			`end`
279			`6'b10_1100: begin to_incr = 3'b010;`
280			`add_sub_b = 1'b1;`
281			`end`
282			`6'b10_1101: begin to_incr = 3'b001;`
283			`add_sub_b = 1'b1;`
284			`end`
285			`6'b10_1110: begin to_incr = 3'b001;`
286			`add_sub_b = 1'b1;`
287			`end`
288			`//6'b10_1111: begin to_incr = 3'b000; JBG: special case where you add instead`
289			`6'b10_1111: begin to_incr = 3'b001;`
290			`add_sub_b = 1'b1;`
291			`end`
292			`6'b11_0000: begin to_incr = 3'b101;`
293			`add_sub_b = 1'b1;`
294			`end`
295			`6'b11_0001: begin to_incr = 3'b100;`
296			`add_sub_b = 1'b1;`
297			`end`
298			`6'b11_0010: begin to_incr = 3'b100;`
299			`add_sub_b = 1'b1;`
300			`end`
301			`6'b11_0011: begin to_incr = 3'b011;`
302			`add_sub_b = 1'b1;`
303			`end`
304			`6'b11_0100: begin to_incr = 3'b100;`
305			`add_sub_b = 1'b1;`
306			`end`
307			`6'b11_0101: begin to_incr = 3'b011;`
308			`add_sub_b = 1'b1;`
309			`end`
310			`6'b11_0110: begin to_incr = 3'b011;`
311			`add_sub_b = 1'b1;`
312			`end`
313			`6'b11_0111: begin to_incr = 3'b010;`
314			`add_sub_b = 1'b1;`
315			`end`
316			`6'b11_1000: begin to_incr = 3'b100;`
317			`add_sub_b = 1'b1;`
318			`end`
319			`6'b11_1001: begin to_incr = 3'b011;`
320			`add_sub_b = 1'b1;`
321			`end`
322			`6'b11_1010: begin to_incr = 3'b011;`
323			`add_sub_b = 1'b1;`
324			`end`
325			`6'b11_1011: begin to_incr = 3'b010;`
326			`add_sub_b = 1'b1;`
327			`end`
328			`6'b11_1100: begin to_incr = 3'b011;`
329			`add_sub_b = 1'b1;`
330			`end`
331			`6'b11_1101: begin to_incr = 3'b010;`
332			`add_sub_b = 1'b1;`
333			`end`
334			`6'b11_1110: begin to_incr = 3'b010;`
335			`add_sub_b = 1'b1;`
336			`end`
337			`6'b11_1111: begin to_incr = 3'b001;`
338			`add_sub_b = 1'b1;`
339			`end`
340			`default: begin to_incr = 3'b000;`
341			`add_sub_b = 1'b1;`
342			`end`
343			`endcase`
344			`end`
345
346
347			`//******************************************************************//`
348			`// Register the outputs. //`
349			`//******************************************************************//`
350
351
352			`reg [2:0] reg_cor_num;`
353			`reg reg_inc_dec_b;`
354			`reg reg_decr_cor;`
355
356			`always @(posedge clk)`
357			`begin`
358			`if (rst)`
359			`begin`
360			`reg_cor_num <= #FFD 3'b000; //remove reset to aid timing`
361			`reg_inc_dec_b <= #FFD 1'b0;`
362			`reg_decr_cor <= #FFD 1'b0;`
363			`end`
364			`else`
365			`begin`
366			`reg_cor_num <= #FFD to_incr;`
367
368			`reg_inc_dec_b <= #FFD ~(add_input_six_n_d && ~add_input_one_d &&`
369			`add_input_two_n_d && add_input_three_n_d &&`
370			`add_input_four_n_d && add_input_five_n_d && decr_cor);`
371			`reg_decr_cor <= #FFD (add_input_six_n_d && ~add_input_one_d &&`
372			`add_input_two_n_d && add_input_three_n_d &&`
373			`add_input_four_n_d && add_input_five_n_d) ?`
374			`~decr_cor : decr_cor;`
375			`end`
376			`end`
377
378			`assign cor_num = reg_cor_num;`
379			`assign inc_dec_b = reg_inc_dec_b;`
380
381
382			`//******************************************************************//`
383			`// //`
384			`//******************************************************************//`
385
386			`endmodule`