Subversion Repositories pcie_ds_dma

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//-----------------------------------------------------------------------------

// Project    : V5-Block Plus for PCI Express

// File       : cmm_errman_cpl.v

//--------------------------------------------------------------------------------

//--------------------------------------------------------------------------------

/***********************************************************************

  Description:

  This module figures out what to do for scheduling Cpl transactions:

    1) count up or count down,

    2) how much to add or to subtract,

    3) it counts the Cpl requested by TLM and USER separately.

  It returns the number and a add/subtract_b signals to the Cpl

  tracking counter. The outputs are based on how many non-posted

  requests have been received by either the TLM or the user.

***********************************************************************/

module cmm_errman_cpl (

                cpl_num,               // Output

                inc_dec_b,

                cmm_err_tlp_posted,    // Inputs

                decr_cpl,

                rst,

                clk

                );

  output  [2:0] cpl_num;

  output        inc_dec_b;             // 1 = increment, 0 = decrement 

  input         cmm_err_tlp_posted;

  input         decr_cpl;

  input         rst;

  input         clk;

  //******************************************************************//

  // Reality check.                                                   //

  //******************************************************************//

  parameter FFD       = 1;        // clock to out delay model

  //******************************************************************//

  // Figure out how many errors to increment.                         //

  //******************************************************************//

  reg     [2:0] mod_to_incr;

  reg           mod_add_sub_b;

  always @(cmm_err_tlp_posted or decr_cpl)

  begin

    case ({cmm_err_tlp_posted, decr_cpl})   // synthesis full_case parallel_case

    2'b00:   begin   mod_to_incr   = 3'b000;

                     mod_add_sub_b = 1'b1;

             end

    2'b01:   begin   mod_to_incr   = 3'b001;

                     mod_add_sub_b = 1'b0;

             end

    2'b10:   begin   mod_to_incr   = 3'b001;

                     mod_add_sub_b = 1'b1;

             end

    2'b11:   begin   mod_to_incr   = 3'b000;

                     mod_add_sub_b = 1'b1;

             end

    default: begin   mod_to_incr   = 3'b000;

                     mod_add_sub_b = 1'b1;

             end

    endcase

  end

  //******************************************************************//

  // Register the outputs.                                            //

  //******************************************************************//

  reg     [2:0] reg_cpl_num;

  reg           reg_inc_dec_b;

  always @(posedge clk or posedge rst)

  begin

    if (rst)

    begin

      reg_cpl_num   <= #FFD 3'b000;

      reg_inc_dec_b <= #FFD 1'b0;

    end

    else

    begin

      reg_cpl_num   <= #FFD mod_to_incr;

      reg_inc_dec_b <= #FFD mod_add_sub_b;

    end

  end

  assign cpl_num   = reg_cpl_num;

  assign inc_dec_b = reg_inc_dec_b;

  //******************************************************************//

  //                                                                  //

  //******************************************************************//

endmodule