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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [cmm_errman_ftl.v] - Blame information for rev 2

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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project    : V5-Block Plus for PCI Express
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// File       : cmm_errman_ftl.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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/***********************************************************************
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  Description:
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  This module figures out what to do for fatal errors:
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    1) count up or count down,
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    2) how much to add or to subtract.
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  It returns the number and a add/subtract_b signals to the error
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  tracking counter. The outputs are based on how many errors are
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  asserted by the error reporting modules.
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***********************************************************************/
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module cmm_errman_ftl (
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                ftl_num,                // Output
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                inc_dec_b,
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                cmmp_training_err,      // Inputs
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                cmml_protocol_err_n,
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                cmmt_err_rbuf_overflow,
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                cmmt_err_fc,
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                cmmt_err_tlp_malformed,
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                decr_ftl,
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                rst,
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                clk
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                );
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  output  [2:0] ftl_num;
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  output        inc_dec_b;              // 1 = increment, 0 = decrement 
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  input         cmmp_training_err;
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  input         cmml_protocol_err_n;
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  input         cmmt_err_rbuf_overflow;
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  input         cmmt_err_fc;
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  input         cmmt_err_tlp_malformed;
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  input         decr_ftl;
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  input         rst;
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  input         clk;
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  //******************************************************************//
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  // Reality check.                                                   //
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  //******************************************************************//
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  parameter FFD       = 1;        // clock to out delay model
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  //******************************************************************//
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  // Figure out how many errors to increment.                         //
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  //******************************************************************//
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  reg     [2:0] to_incr;
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  reg           add_sub_b;
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  always @(cmmt_err_tlp_malformed or
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           cmmp_training_err or
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           cmml_protocol_err_n or
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           cmmt_err_rbuf_overflow or cmmt_err_fc or
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           decr_ftl) begin
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    case ({cmmt_err_tlp_malformed, cmml_protocol_err_n, cmmt_err_rbuf_overflow, cmmp_training_err, cmmt_err_fc,
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           decr_ftl})   // synthesis full_case parallel_case
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    6'b000000: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b000001: begin to_incr = 3'b000; add_sub_b = 1'b1; end
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    6'b000010: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b000011: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b000100: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b000101: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b000110: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b000111: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b001000: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b001001: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b001010: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b001011: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b001100: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b001101: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b001110: begin to_incr = 3'b100; add_sub_b = 1'b1; end
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    6'b001111: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b010000: begin to_incr = 3'b000; add_sub_b = 1'b1; end
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    6'b010001: begin to_incr = 3'b001; add_sub_b = 1'b0; end
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    6'b010010: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b010011: begin to_incr = 3'b000; add_sub_b = 1'b1; end
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    6'b010100: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b010101: begin to_incr = 3'b000; add_sub_b = 1'b1; end
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    6'b010110: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b010111: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b011000: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b011001: begin to_incr = 3'b000; add_sub_b = 1'b1; end
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    6'b011010: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b011011: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b011100: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b011101: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b011110: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b011111: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b100000: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b100001: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b100010: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b100011: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b100100: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b100101: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b100110: begin to_incr = 3'b100; add_sub_b = 1'b1; end
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    6'b100111: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b101000: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b101001: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b101010: begin to_incr = 3'b100; add_sub_b = 1'b1; end
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    6'b101011: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b101100: begin to_incr = 3'b100; add_sub_b = 1'b1; end
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    6'b101101: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b101110: begin to_incr = 3'b101; add_sub_b = 1'b1; end
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    6'b101111: begin to_incr = 3'b100; add_sub_b = 1'b1; end
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    6'b110000: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b110001: begin to_incr = 3'b000; add_sub_b = 1'b1; end
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    6'b110010: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b110011: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b110100: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b110101: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b110110: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b110111: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b111000: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b111001: begin to_incr = 3'b001; add_sub_b = 1'b1; end
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    6'b111010: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b111011: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b111100: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    6'b111101: begin to_incr = 3'b010; add_sub_b = 1'b1; end
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    6'b111110: begin to_incr = 3'b100; add_sub_b = 1'b1; end
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    6'b111111: begin to_incr = 3'b011; add_sub_b = 1'b1; end
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    default:   begin to_incr = 3'b000; add_sub_b = 1'b1; end
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    endcase
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  end
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  //******************************************************************//
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  // Register the outputs.                                            //
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  //******************************************************************//
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  reg     [2:0] reg_ftl_num;
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  reg           reg_inc_dec_b;
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  always @(posedge clk or posedge rst) begin
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    if (rst) begin
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      reg_ftl_num   <= #FFD 3'b000;
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      reg_inc_dec_b <= #FFD 1'b0;
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    end
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    else begin
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      reg_ftl_num   <= #FFD to_incr;
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      reg_inc_dec_b <= #FFD add_sub_b;
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    end
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  end
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  assign ftl_num   = reg_ftl_num;
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  assign inc_dec_b = reg_inc_dec_b;
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endmodule

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