Subversion Repositories pcie_ds_dma

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//-----------------------------------------------------------------------------

// Project    : V5-Block Plus for PCI Express

// File       : cmm_errman_nfl.v

//--------------------------------------------------------------------------------

//--------------------------------------------------------------------------------

/***********************************************************************

  Description:

  This module figures out what to do for non-fatal errors:

    1) count up or count down,

    2) how much to add or to subtract.

  It returns the number and a add/subtract_b signals to the error

  tracking counter. The outputs are based on how many errors are

  asserted by the error reporting modules.

***********************************************************************/

module cmm_errman_nfl (

                nfl_num,                // Output

                inc_dec_b,

                cfg_err_cpl_timeout_n,

                decr_nfl,

                rst,

                clk

                );

  output        nfl_num;

  output        inc_dec_b;              // 1 = increment, 0 = decrement 

  input         cfg_err_cpl_timeout_n;

  input         decr_nfl;

  input         rst;

  input         clk;

  //******************************************************************//

  // Reality check.                                                   //

  //******************************************************************//

  parameter FFD       = 1;        // clock to out delay model

  //******************************************************************//

  // Figure out how many errors to increment.                         //

  //******************************************************************//

  reg           to_incr;

  reg           add_sub_b;

  always @(cfg_err_cpl_timeout_n or decr_nfl) begin

    case ({cfg_err_cpl_timeout_n, decr_nfl})    // synthesis full_case parallel_case

    2'b10: begin   to_incr   = 1'b0;

                   add_sub_b = 1'b1;

           end

    2'b11: begin   to_incr   = 1'b1;

                   add_sub_b = 1'b0;

           end

    2'b00: begin   to_incr   = 1'b1;

                   add_sub_b = 1'b1;

           end

    2'b01: begin   to_incr   = 1'b0;

                   add_sub_b = 1'b1;

           end

    default:  begin   to_incr   = 1'b0;

                      add_sub_b = 1'b1;

              end

    endcase

  end

  //******************************************************************//

  // Register the outputs.                                            //

  //******************************************************************//

  reg      reg_nfl_num;

  reg      reg_inc_dec_b;

  always @(posedge clk or posedge rst)

  begin

    if (rst)

    begin

      reg_nfl_num   <= #FFD 1'b0;

      reg_inc_dec_b <= #FFD 1'b0;

    end

    else

    begin

      reg_nfl_num   <= #FFD to_incr;

      reg_inc_dec_b <= #FFD add_sub_b;

    end

  end

  assign nfl_num   = reg_nfl_num;

  assign inc_dec_b = reg_inc_dec_b;

  //******************************************************************//

  //                                                                  //

  //******************************************************************//

endmodule