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//-----------------------------------------------------------------------------

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//-----------------------------------------------------------------------------

// Project    : V5-Block Plus for PCI Express

// File       : cmm_intr.v

//--------------------------------------------------------------------------------

//--------------------------------------------------------------------------------

`define FFD 1

module cmm_intr (

                signaledint,         // Outputs

                intr_req_valid,

                intr_req_type,

                intr_rdy,

                cfg_interrupt_n,     // Inputs

                cfg_interrupt_assert_n,

                cfg_interrupt_di,

                cfg_interrupt_mmenable,

                msi_data,

                intr_vector,

                command,

                msi_control,

                msi_laddr,

                msi_haddr,

                intr_grant,

                cfg,

                rst,

                clk

                ) /* synthesis syn_hier ="hard"*/;

//This indicates (to Status register) that a Legacy Interrupt has been sent

output         signaledint;          // Outputs

output         intr_req_valid;

output  [1:0]  intr_req_type;

output         intr_rdy;

output [7:0]   intr_vector;

input          cfg_interrupt_assert_n;

input  [7:0]   cfg_interrupt_di;

input  [15:0]  msi_data;

input  [2:0]   cfg_interrupt_mmenable;

input          cfg_interrupt_n;     // Inputs

input  [15:0]  command;

input  [15:0]  msi_control;

input  [31:0]  msi_laddr;

input  [31:0]  msi_haddr;

input          intr_grant;

input [1023:0] cfg;

input          rst;

input          clk;

reg         signaledint;          // Outputs

wire        intr_rdy;

reg         q_intr_req_valid;

reg  [1:0]  q_intr_req_type;

// notes 

// msi_control[0] is msi_mode

// 64 bit address capable bit 7 of message control

// This design supports only one message 

// command [10] is interrupt disable

parameter [1:0] IDLE          = 2'b00;

parameter [1:0] SEND_MSI      = 2'b01;

parameter [1:0] SEND_ASSERT   = 2'b10;

parameter [1:0] SEND_DEASSERT = 2'b11;

wire msi_64;

wire msi_mode;

wire intx_mode;

wire bus_master_en;

wire intr_req;

reg       allow_int;

reg [1:0] state;

reg [1:0] next_state;

assign msi_64 = msi_control[7] &&  (msi_haddr != 0);

assign msi_mode      = msi_control[0];

assign intx_mode     = ~command[10];

assign bus_master_en = command[2];

assign intr_req = !cfg_interrupt_n && allow_int;

reg intr_req_q = 0;

reg intr_rdyx  = 0;

reg cfg_interrupt_assert_n_q = 1;

reg [7:0] cfg_interrupt_di_q = 0;

reg [7:0] intr_vector        = 0;

always @(posedge clk or posedge rst) begin

   if (rst) begin

      intr_req_q <= #`FFD 1'b0;

      allow_int  <= #`FFD 1'b0;

      intr_rdyx  <= #`FFD 1'b0;

      cfg_interrupt_assert_n_q  <= #`FFD 1'b1;

   end else begin

      intr_req_q <= #`FFD intr_req;

      allow_int  <= #`FFD ((msi_mode && bus_master_en) || (!msi_mode && intx_mode));

      intr_rdyx  <= #`FFD (state != IDLE) && intr_grant;

      cfg_interrupt_assert_n_q  <= #`FFD cfg_interrupt_assert_n;

   end

end

always @(posedge clk) begin

   cfg_interrupt_di_q <= #`FFD cfg_interrupt_di;

end

always @(posedge clk) begin

   //This override will permit the user to alter all 8 MSI bits

   if (cfg[467]) begin

     intr_vector          <= #`FFD cfg_interrupt_di_q[7:0];

   end else if (intr_req_q) begin

     casez ({msi_mode,cfg_interrupt_mmenable})

     4'b0???: intr_vector <= #`FFD cfg_interrupt_di_q[7:0];

     4'b1000: intr_vector <= #`FFD msi_data[7:0];

     4'b1001: intr_vector <= #`FFD {msi_data[7:1],cfg_interrupt_di_q[0]};

     4'b1010: intr_vector <= #`FFD {msi_data[7:2],cfg_interrupt_di_q[1:0]};

     4'b1011: intr_vector <= #`FFD {msi_data[7:3],cfg_interrupt_di_q[2:0]};

     4'b1100: intr_vector <= #`FFD {msi_data[7:4],cfg_interrupt_di_q[3:0]};

     4'b1101: intr_vector <= #`FFD {msi_data[7:5],cfg_interrupt_di_q[4:0]};

     default: intr_vector <= #`FFD {msi_data[7:5],cfg_interrupt_di_q[4:0]};

     endcase

   end

end

wire        intr_req_valid = q_intr_req_valid;

wire [1:0]  intr_req_type  = q_intr_req_type;

reg         intr_rdy_q;

always @(posedge clk) begin

   if (rst) begin

      intr_rdy_q     <= #`FFD 0;

   end else begin

      intr_rdy_q     <= #`FFD intr_rdy;

   end

end

wire send_assert;

wire send_deassert;

wire send_msi;

assign send_assert  = !msi_mode && intr_req_q && ~cfg_interrupt_assert_n_q &&

                      ~(intr_rdy || intr_rdy_q);

assign send_deassert= !msi_mode && intr_req_q &&  cfg_interrupt_assert_n_q &&

                      ~(intr_rdy || intr_rdy_q);

assign send_msi     =  msi_mode && intr_req_q &&

                      ~(intr_rdy || intr_rdy_q);

always @(posedge clk) begin

   if (rst) begin

      state          <= #`FFD IDLE;

   end

   else begin

      state          <= #`FFD next_state;

   end

end

always @*

begin

   next_state = IDLE;

   signaledint = 0;

   q_intr_req_type = 0;

   q_intr_req_valid = 0;

   case (state) // synthesis full_case parallel_case 

      IDLE : begin

                q_intr_req_type = 0;

                q_intr_req_valid = 0;

                signaledint = 0;

                if (send_msi) begin

                   next_state = SEND_MSI;

                end

                else if (send_assert) begin

                   next_state = SEND_ASSERT;

                end

                else if (send_deassert) begin

                   next_state = SEND_DEASSERT;

                end

                else begin

                   next_state = IDLE;

                end

             end

  SEND_MSI : begin

                q_intr_req_type = msi_64 ? 2'b11 : 2'b10;

                if (intr_grant) begin

                   q_intr_req_valid = 0;

                   next_state = IDLE;

                   signaledint = 0;

                end

                else begin

                   q_intr_req_valid = 1;

                   next_state = SEND_MSI;

                   signaledint = 0;

                end

             end

 SEND_ASSERT : begin

                q_intr_req_type = 2'b00;

                if (intr_grant) begin

                   q_intr_req_valid = 0;

                   next_state = IDLE;

                   signaledint = 1;

                end

                else begin

                   q_intr_req_valid = 1;

                   next_state = SEND_ASSERT;

                   signaledint = 0;

                end

             end

 SEND_DEASSERT : begin

                q_intr_req_type = 2'b01;

                if (intr_grant) begin

                   q_intr_req_valid = 0;

                   next_state = IDLE;

                   signaledint = 1;

                end

                else begin

                   q_intr_req_valid = 1;

                   next_state = SEND_DEASSERT;

                   signaledint = 0;

                end

             end

   endcase

end

assign intr_rdy = intr_rdyx;

endmodule