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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : cmm_intr.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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`define FFD 1
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module cmm_intr (
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signaledint, // Outputs
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intr_req_valid,
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intr_req_type,
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intr_rdy,
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cfg_interrupt_n, // Inputs
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cfg_interrupt_assert_n,
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cfg_interrupt_di,
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cfg_interrupt_mmenable,
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msi_data,
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intr_vector,
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command,
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msi_control,
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msi_laddr,
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msi_haddr,
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intr_grant,
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cfg,
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rst,
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clk
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) /* synthesis syn_hier ="hard"*/;
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//This indicates (to Status register) that a Legacy Interrupt has been sent
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output signaledint; // Outputs
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output intr_req_valid;
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output [1:0] intr_req_type;
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output intr_rdy;
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output [7:0] intr_vector;
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input cfg_interrupt_assert_n;
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input [7:0] cfg_interrupt_di;
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input [15:0] msi_data;
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input [2:0] cfg_interrupt_mmenable;
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input cfg_interrupt_n; // Inputs
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input [15:0] command;
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input [15:0] msi_control;
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input [31:0] msi_laddr;
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input [31:0] msi_haddr;
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input intr_grant;
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input [1023:0] cfg;
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input rst;
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input clk;
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reg signaledint; // Outputs
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wire intr_rdy;
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reg q_intr_req_valid;
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reg [1:0] q_intr_req_type;
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// notes
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// msi_control[0] is msi_mode
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// 64 bit address capable bit 7 of message control
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// This design supports only one message
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// command [10] is interrupt disable
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parameter [1:0] IDLE = 2'b00;
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parameter [1:0] SEND_MSI = 2'b01;
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parameter [1:0] SEND_ASSERT = 2'b10;
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parameter [1:0] SEND_DEASSERT = 2'b11;
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wire msi_64;
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wire msi_mode;
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wire intx_mode;
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wire bus_master_en;
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wire intr_req;
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reg allow_int;
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reg [1:0] state;
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reg [1:0] next_state;
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assign msi_64 = msi_control[7] && (msi_haddr != 0);
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assign msi_mode = msi_control[0];
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assign intx_mode = ~command[10];
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assign bus_master_en = command[2];
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assign intr_req = !cfg_interrupt_n && allow_int;
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reg intr_req_q = 0;
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reg intr_rdyx = 0;
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reg cfg_interrupt_assert_n_q = 1;
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reg [7:0] cfg_interrupt_di_q = 0;
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reg [7:0] intr_vector = 0;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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intr_req_q <= #`FFD 1'b0;
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allow_int <= #`FFD 1'b0;
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intr_rdyx <= #`FFD 1'b0;
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cfg_interrupt_assert_n_q <= #`FFD 1'b1;
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end else begin
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intr_req_q <= #`FFD intr_req;
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allow_int <= #`FFD ((msi_mode && bus_master_en) || (!msi_mode && intx_mode));
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intr_rdyx <= #`FFD (state != IDLE) && intr_grant;
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cfg_interrupt_assert_n_q <= #`FFD cfg_interrupt_assert_n;
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end
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end
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always @(posedge clk) begin
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cfg_interrupt_di_q <= #`FFD cfg_interrupt_di;
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end
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always @(posedge clk) begin
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//This override will permit the user to alter all 8 MSI bits
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if (cfg[467]) begin
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intr_vector <= #`FFD cfg_interrupt_di_q[7:0];
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end else if (intr_req_q) begin
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casez ({msi_mode,cfg_interrupt_mmenable})
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4'b0???: intr_vector <= #`FFD cfg_interrupt_di_q[7:0];
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4'b1000: intr_vector <= #`FFD msi_data[7:0];
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4'b1001: intr_vector <= #`FFD {msi_data[7:1],cfg_interrupt_di_q[0]};
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4'b1010: intr_vector <= #`FFD {msi_data[7:2],cfg_interrupt_di_q[1:0]};
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4'b1011: intr_vector <= #`FFD {msi_data[7:3],cfg_interrupt_di_q[2:0]};
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4'b1100: intr_vector <= #`FFD {msi_data[7:4],cfg_interrupt_di_q[3:0]};
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4'b1101: intr_vector <= #`FFD {msi_data[7:5],cfg_interrupt_di_q[4:0]};
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default: intr_vector <= #`FFD {msi_data[7:5],cfg_interrupt_di_q[4:0]};
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endcase
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end
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end
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wire intr_req_valid = q_intr_req_valid;
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wire [1:0] intr_req_type = q_intr_req_type;
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reg intr_rdy_q;
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always @(posedge clk) begin
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if (rst) begin
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intr_rdy_q <= #`FFD 0;
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end else begin
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intr_rdy_q <= #`FFD intr_rdy;
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end
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end
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wire send_assert;
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wire send_deassert;
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wire send_msi;
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assign send_assert = !msi_mode && intr_req_q && ~cfg_interrupt_assert_n_q &&
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~(intr_rdy || intr_rdy_q);
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assign send_deassert= !msi_mode && intr_req_q && cfg_interrupt_assert_n_q &&
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~(intr_rdy || intr_rdy_q);
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assign send_msi = msi_mode && intr_req_q &&
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~(intr_rdy || intr_rdy_q);
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always @(posedge clk) begin
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if (rst) begin
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state <= #`FFD IDLE;
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end
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else begin
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state <= #`FFD next_state;
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end
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end
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always @*
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begin
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next_state = IDLE;
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signaledint = 0;
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q_intr_req_type = 0;
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q_intr_req_valid = 0;
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case (state) // synthesis full_case parallel_case
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IDLE : begin
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q_intr_req_type = 0;
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q_intr_req_valid = 0;
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signaledint = 0;
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if (send_msi) begin
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next_state = SEND_MSI;
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end
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else if (send_assert) begin
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next_state = SEND_ASSERT;
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end
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else if (send_deassert) begin
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next_state = SEND_DEASSERT;
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end
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else begin
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next_state = IDLE;
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end
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end
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SEND_MSI : begin
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q_intr_req_type = msi_64 ? 2'b11 : 2'b10;
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if (intr_grant) begin
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q_intr_req_valid = 0;
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next_state = IDLE;
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signaledint = 0;
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end
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else begin
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q_intr_req_valid = 1;
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next_state = SEND_MSI;
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signaledint = 0;
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end
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end
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SEND_ASSERT : begin
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q_intr_req_type = 2'b00;
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if (intr_grant) begin
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q_intr_req_valid = 0;
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next_state = IDLE;
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signaledint = 1;
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end
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else begin
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q_intr_req_valid = 1;
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next_state = SEND_ASSERT;
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signaledint = 0;
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end
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end
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SEND_DEASSERT : begin
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q_intr_req_type = 2'b01;
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if (intr_grant) begin
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q_intr_req_valid = 0;
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next_state = IDLE;
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signaledint = 1;
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end
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else begin
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q_intr_req_valid = 1;
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next_state = SEND_DEASSERT;
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signaledint = 0;
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end
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end
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endcase
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end
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assign intr_rdy = intr_rdyx;
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endmodule
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