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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [ctrl_pcie_x8.v] - Blame information for rev 2

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//-----------------------------------------------------------------------------
2
//
3
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
4
//
5
// This file contains confidential and proprietary information
6
// of Xilinx, Inc. and is protected under U.S. and
7
// international copyright and other intellectual property
8
// laws.
9
//
10
// DISCLAIMER
11
// This disclaimer is not a license and does not grant any
12
// rights to the materials distributed herewith. Except as
13
// otherwise provided in a valid license issued to you by
14
// Xilinx, and to the maximum extent permitted by applicable
15
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20
// (2) Xilinx shall not be liable (whether in contract or tort,
21
// including negligence, or under any other theory of
22
// liability) for any loss or damage of any kind or nature
23
// related to, arising under or in connection with these
24
// materials, including for any direct, or any indirect,
25
// special, incidental, or consequential loss or damage
26
// (including loss of data, profits, goodwill, or any type of
27
// loss or damage suffered as a result of any action brought
28
// by a third party) even if such damage or loss was
29
// reasonably foreseeable or Xilinx had been advised of the
30
// possibility of the same.
31
//
32
// CRITICAL APPLICATIONS
33
// Xilinx products are not designed or intended to be fail-
34
// safe, or for use in any application requiring fail-safe
35
// performance, such as life-support or safety devices or
36
// systems, Class III medical devices, nuclear facilities,
37
// applications related to the deployment of airbags, or any
38
// other applications that could lead to death, personal
39
// injury, or severe property or environmental damage
40
// (individually and collectively, "Critical
41
// Applications"). Customer assumes the sole risk and
42
// liability of any use of Xilinx products in Critical
43
// Applications, subject only to applicable laws and
44
// regulations governing limitations on product liability.
45
//
46
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47
// PART OF THIS FILE AT ALL TIMES.
48
//
49
//-----------------------------------------------------------------------------
50
// Project    : V5-Block Plus for PCI Express
51
// File       : ctrl_pcie_x8.v
52
//--------------------------------------------------------------------------------
53
// Description: This is the top-level PCI Express wrapper.
54
//--------------------------------------------------------------------------------
55
`timescale 1ns/1ns
56
 
57
module ctrl_pcie_x8 # (
58
  parameter        C_XDEVICE = "xc5vsx50t",
59
  parameter        USE_V5FXT = 0,
60
  parameter        PCI_EXP_LINK_WIDTH = 8,
61
  parameter        PCI_EXP_INT_FREQ = 2,
62
  parameter        PCI_EXP_REF_FREQ = 1,
63
  parameter        PCI_EXP_TRN_DATA_WIDTH = 64,
64
  parameter        PCI_EXP_TRN_REM_WIDTH = 8,
65
  parameter        PCI_EXP_TRN_BUF_AV_WIDTH = 4,
66
  parameter        PCI_EXP_BAR_HIT_WIDTH = 7,
67
  parameter        PCI_EXP_FC_HDR_WIDTH = 8,
68
  parameter        PCI_EXP_FC_DATA_WIDTH = 12,
69
  parameter        PCI_EXP_CFG_DATA_WIDTH = 32,
70
  parameter        PCI_EXP_CFG_ADDR_WIDTH = 10,
71
  parameter        PCI_EXP_CFG_CPLHDR_WIDTH = 48,
72
  parameter        PCI_EXP_CFG_BUSNUM_WIDTH = 8,
73
  parameter        PCI_EXP_CFG_DEVNUM_WIDTH = 5,
74
  parameter        PCI_EXP_CFG_FUNNUM_WIDTH = 3,
75
  parameter        PCI_EXP_CFG_CAP_WIDTH = 16,
76
  parameter        PCI_EXP_CFG_WIDTH = 1024,
77
 
78
  parameter        VEN_ID_temp = 32'h00004953,
79
  parameter        VEN_ID = VEN_ID_temp[15 : 0],
80
  parameter        DEV_ID = 16'h5507,
81
  parameter        REV_ID = 8'h20,
82
  parameter        CLASS_CODE = 24'hFFFFFF,
83
  parameter        BAR0 = 32'hFFE00000,
84
  parameter        BAR1 = 32'hFFE00000,
85
  parameter        BAR2 = 32'h00000000,
86
  parameter        BAR3 = 32'h00000000,
87
  parameter        BAR4 = 32'h00000000,
88
  parameter        BAR5 = 32'h00000000,
89
  parameter        CARDBUS_CIS_PTR = 32'h00000000,
90
  parameter        SUBSYS_VEN_ID_temp = 32'h00004953,
91
  parameter        SUBSYS_ID_temp = 32'h00000001,
92
  parameter        SUBSYS_VEN_ID = SUBSYS_VEN_ID_temp[15 : 0],
93
  parameter        SUBSYS_ID = SUBSYS_ID_temp[15 : 0],
94
  parameter        XROM_BAR = 32'hFFF00001,
95
 
96
  parameter        INTR_MSG_NUM = 5'b00000,
97
  parameter        SLT_IMPL = 0,
98
  parameter        DEV_PORT_TYPE = 4'b0000,
99
  parameter        CAP_VER = 4'h1,
100
 
101
  parameter        CAPT_SLT_PWR_LIM_SC = 2'b00,
102
  parameter        CAPT_SLT_PWR_LIM_VA = 8'h00,
103
  parameter        PWR_INDI_PRSNT = 0,
104
  parameter        ATTN_INDI_PRSNT = 0,
105
  parameter        ATTN_BUTN_PRSNT = 0,
106
  parameter        EP_L1_ACCPT_LAT = 3'b111,
107
  parameter        EP_L0s_ACCPT_LAT = 3'b111,
108
  parameter        EXT_TAG_FLD_SUP = 1,
109
  parameter        PHANTM_FUNC_SUP = 2'b01,
110
  parameter        MPS = 3'b001,
111
 
112
  parameter        L1_EXIT_LAT = 3'b111,
113
  parameter        L0s_EXIT_LAT = 3'b111,
114
  parameter        ASPM_SUP = 2'b01,
115
  parameter        MAX_LNK_WDT = 6'b1000,
116
  parameter        MAX_LNK_SPD = 4'b1,
117
 
118
  parameter        ACK_TO = 16'h0204,
119
  parameter        RPLY_TO = 16'h060d,
120
 
121
  parameter        MSI = 4'b0000,
122
 
123
  parameter        PCI_CONFIG_SPACE_ACCESS = 0,
124
  parameter        EXT_CONFIG_SPACE_ACCESS = 0,
125
 
126
  parameter        TRM_TLP_DGST_ECRC = 1,
127
  parameter        FRCE_NOSCRMBL = 0,
128
  parameter        TWO_PLM_ATOCFGR = 0,
129
 
130
  parameter        PME_SUP = 5'h0,
131
  parameter        D2_SUP = 0,
132
  parameter        D1_SUP = 0,
133
  parameter        AUX_CT = 3'b000,
134
  parameter        DSI = 1,
135
  parameter        PME_CLK = 0,
136
  parameter        PM_CAP_VER = 3'b010,
137
 
138
  parameter        PWR_CON_D0_STATE = 8'h0,
139
  parameter        CON_SCL_FCTR_D0_STATE = 8'h0,
140
  parameter        PWR_CON_D1_STATE = 8'h0,
141
  parameter        CON_SCL_FCTR_D1_STATE = 8'h0,
142
  parameter        PWR_CON_D2_STATE = 8'h0,
143
  parameter        CON_SCL_FCTR_D2_STATE = 8'h0,
144
  parameter        PWR_CON_D3_STATE = 8'h0,
145
  parameter        CON_SCL_FCTR_D3_STATE = 8'h0,
146
 
147
  parameter        PWR_DIS_D0_STATE = 8'h0,
148
  parameter        DIS_SCL_FCTR_D0_STATE = 8'h0,
149
  parameter        PWR_DIS_D1_STATE = 8'h0,
150
  parameter        DIS_SCL_FCTR_D1_STATE = 8'h0,
151
  parameter        PWR_DIS_D2_STATE = 8'h0,
152
  parameter        DIS_SCL_FCTR_D2_STATE = 8'h0,
153
  parameter        PWR_DIS_D3_STATE = 8'h0,
154
  parameter        DIS_SCL_FCTR_D3_STATE = 8'h0,
155
 
156
  parameter        CAL_BLK_DISABLE = 0,
157
  parameter        SWAP_A_B_PAIRS = 0,
158
 
159
  parameter        INFINITECOMPLETIONS = "TRUE",
160
  parameter        VC0_CREDITS_PH = 1,
161
  parameter        VC0_CREDITS_NPH = 1,
162
  parameter        CPL_STREAMING_PRIORITIZE_P_NP = 1,
163
 
164
  parameter        SLOT_CLK = "TRUE",
165
 
166
  parameter        TX_DIFF_BOOST = "TRUE",
167
  parameter        TXDIFFCTRL = 3'b100,
168
  parameter        TXBUFDIFFCTRL = 3'b100,
169
  parameter        TXPREEMPHASIS = 3'b111,
170
  parameter        GT_Debug_Ports = 0,
171
  parameter        GTDEBUGPORTS = 0
172
 
173
)
174
(
175
       // PCI Express Fabric Interface
176
    output      [PCI_EXP_LINK_WIDTH-1 : 0]     pci_exp_txp,
177
    output      [PCI_EXP_LINK_WIDTH-1 : 0]     pci_exp_txn,
178
    input       [PCI_EXP_LINK_WIDTH-1 : 0]     pci_exp_rxp,
179
    input       [PCI_EXP_LINK_WIDTH-1 : 0]     pci_exp_rxn,
180
 
181
 
182
 
183
    // Transaction (TRN) Interface
184
    output                                     trn_clk,
185
    output                                     trn_reset_n,
186
    output                                     trn_lnk_up_n,
187
 
188
    // Tx
189
    input       [PCI_EXP_TRN_DATA_WIDTH-1 : 0] trn_td,
190
    input       [PCI_EXP_TRN_REM_WIDTH-1 : 0]  trn_trem_n,
191
    input                                      trn_tsof_n,
192
    input                                      trn_teof_n,
193
    input                                      trn_tsrc_rdy_n,
194
    output                                     trn_tdst_rdy_n,
195
    output                                     trn_tdst_dsc_n,
196
    input                                      trn_tsrc_dsc_n,
197
    input                                      trn_terrfwd_n,
198
    output      [PCI_EXP_TRN_BUF_AV_WIDTH-1:0] trn_tbuf_av,
199
 
200
 
201
    // Rx
202
    output [PCI_EXP_TRN_DATA_WIDTH-1 : 0]      trn_rd,
203
    output [PCI_EXP_TRN_REM_WIDTH-1 : 0]       trn_rrem_n,
204
    output                                     trn_rsof_n,
205
    output                                     trn_reof_n,
206
    output                                     trn_rsrc_rdy_n,
207
    output                                     trn_rsrc_dsc_n,
208
    input                                      trn_rdst_rdy_n,
209
    output                                     trn_rerrfwd_n,
210
    input                                      trn_rnp_ok_n,
211
    output [PCI_EXP_BAR_HIT_WIDTH-1 : 0]       trn_rbar_hit_n,
212
    output [PCI_EXP_FC_HDR_WIDTH-1 : 0]        trn_rfc_nph_av,
213
    output [PCI_EXP_FC_DATA_WIDTH-1 : 0]       trn_rfc_npd_av,
214
    output [PCI_EXP_FC_HDR_WIDTH-1 : 0]        trn_rfc_ph_av,
215
    output [PCI_EXP_FC_DATA_WIDTH-1 : 0]       trn_rfc_pd_av,
216
    input  trn_rcpl_streaming_n,
217
 
218
 
219
    // Host (CFG) Interface
220
    output [PCI_EXP_CFG_DATA_WIDTH-1 : 0]      cfg_do,
221
    output                                     cfg_rd_wr_done_n,
222
    input  [PCI_EXP_CFG_DATA_WIDTH-1 : 0]      cfg_di,
223
    input  [PCI_EXP_CFG_DATA_WIDTH/8-1 : 0]    cfg_byte_en_n,
224
    input  [PCI_EXP_CFG_ADDR_WIDTH-1 : 0]      cfg_dwaddr,
225
    input                                      cfg_wr_en_n,
226
    input                                      cfg_rd_en_n,
227
    input                                      cfg_err_cor_n,
228
    input                                      cfg_err_ur_n,
229
    input                                      cfg_err_ecrc_n,
230
    input                                      cfg_err_cpl_timeout_n,
231
    input                                      cfg_err_cpl_abort_n,
232
    input                                      cfg_err_cpl_unexpect_n,
233
    input                                      cfg_err_posted_n,
234
    input  [PCI_EXP_CFG_CPLHDR_WIDTH-1 : 0]    cfg_err_tlp_cpl_header,
235
 
236
    output                                     cfg_err_cpl_rdy_n,
237
    input                                      cfg_err_locked_n,
238
    input                                      cfg_interrupt_n,
239
    output                                     cfg_interrupt_rdy_n,
240
    input                                      cfg_interrupt_assert_n,
241
    input  [7 : 0]                             cfg_interrupt_di,
242
    output [7 : 0]                             cfg_interrupt_do,
243
    output [2 : 0]                             cfg_interrupt_mmenable,
244
    output                                     cfg_interrupt_msienable,
245
    output                                     cfg_to_turnoff_n,
246
    input                                      cfg_pm_wake_n,
247
    output [2 : 0]                             cfg_pcie_link_state_n,
248
    input                                      cfg_trn_pending_n,
249
    output [PCI_EXP_CFG_BUSNUM_WIDTH-1 : 0]    cfg_bus_number,
250
    output [PCI_EXP_CFG_DEVNUM_WIDTH-1 : 0]    cfg_device_number,
251
    output [PCI_EXP_CFG_FUNNUM_WIDTH-1 : 0]    cfg_function_number,
252
    input  [63 : 0]                            cfg_dsn,
253
    output [PCI_EXP_CFG_CAP_WIDTH-1 : 0]       cfg_status,
254
    output [PCI_EXP_CFG_CAP_WIDTH-1 : 0]       cfg_command,
255
    output [PCI_EXP_CFG_CAP_WIDTH-1 : 0]       cfg_dstatus,
256
    output [PCI_EXP_CFG_CAP_WIDTH-1 : 0]       cfg_dcommand,
257
    output [PCI_EXP_CFG_CAP_WIDTH-1 : 0]       cfg_lstatus,
258
    output [PCI_EXP_CFG_CAP_WIDTH-1 : 0]       cfg_lcommand,
259
    input                                      fast_train_simulation_only,
260
 
261
    // System (SYS) Interface
262
    input                                      sys_clk,
263
    // sys_clk_n              : in  std_logic;
264
    output                                     refclkout,
265
    input                                      sys_reset_n
266
);
267
 
268
 
269
wire [8*16-1 : 0]    gt_do_x;
270
wire [8-1 : 0]       gt_drdy_x;
271
 
272
 
273
  pcie_ep_top   #(
274
 
275
     // G_USE_DCM => 1,
276
     // G_USER_RESETS => 0,
277
     // G_SIM => 0,
278
     // G_CHIPSCOPE => 0,
279
 
280
      .USE_V5FXT ( USE_V5FXT),
281
      .INTF_CLK_FREQ ( PCI_EXP_INT_FREQ),
282
      .REF_CLK_FREQ ( PCI_EXP_REF_FREQ),
283
      .VEN_ID ( VEN_ID),
284
      .DEV_ID ( DEV_ID),
285
      .REV_ID ( REV_ID),
286
      .CLASS_CODE ( CLASS_CODE),
287
      .BAR0 ( BAR0),
288
      .BAR1 ( BAR1),
289
      .BAR2 ( BAR2),
290
      .BAR3 ( BAR3),
291
      .BAR4 ( BAR4),
292
      .BAR5 ( BAR5),
293
      .CARDBUS_CIS_PTR ( CARDBUS_CIS_PTR),
294
      .SUBSYS_VEN_ID ( SUBSYS_VEN_ID),
295
      .SUBSYS_ID ( SUBSYS_ID),
296
      .XROM_BAR ( XROM_BAR),
297
      .INTR_MSG_NUM ( INTR_MSG_NUM),
298
      .SLT_IMPL ( SLT_IMPL),
299
      .DEV_PORT_TYPE ( DEV_PORT_TYPE),
300
      .CAP_VER ( CAP_VER),
301
      .CAPT_SLT_PWR_LIM_SC ( CAPT_SLT_PWR_LIM_SC),
302
      .CAPT_SLT_PWR_LIM_VA ( CAPT_SLT_PWR_LIM_VA),
303
      .PWR_INDI_PRSNT ( PWR_INDI_PRSNT),
304
      .ATTN_INDI_PRSNT ( ATTN_INDI_PRSNT),
305
      .ATTN_BUTN_PRSNT ( ATTN_BUTN_PRSNT),
306
      .EP_L1_ACCPT_LAT ( EP_L1_ACCPT_LAT),
307
      .EP_L0s_ACCPT_LAT ( EP_L0s_ACCPT_LAT),
308
      .EXT_TAG_FLD_SUP ( EXT_TAG_FLD_SUP),
309
      .PHANTM_FUNC_SUP ( PHANTM_FUNC_SUP),
310
      .MPS ( MPS),
311
      .L1_EXIT_LAT ( L1_EXIT_LAT),
312
      .L0s_EXIT_LAT ( L0s_EXIT_LAT),
313
      .ASPM_SUP ( ASPM_SUP),
314
      .MAX_LNK_WDT ( MAX_LNK_WDT),
315
      .MAX_LNK_SPD ( MAX_LNK_SPD),
316
      .TRM_TLP_DGST_ECRC ( TRM_TLP_DGST_ECRC),
317
      .FRCE_NOSCRMBL ( FRCE_NOSCRMBL),
318
      .INFINITECOMPLETIONS ( INFINITECOMPLETIONS),
319
      .VC0_CREDITS_PH ( VC0_CREDITS_PH),
320
      .VC0_CREDITS_NPH ( VC0_CREDITS_NPH),
321
      .CPL_STREAMING_PRIORITIZE_P_NP ( CPL_STREAMING_PRIORITIZE_P_NP),
322
      .SLOT_CLOCK_CONFIG ( SLOT_CLK),
323
      .PME_SUP ( PME_SUP),
324
      .D2_SUP ( D2_SUP),
325
      .D1_SUP ( D1_SUP),
326
      .AUX_CT ( AUX_CT),
327
      .DSI ( DSI),
328
      .PME_CLK ( PME_CLK),
329
      .PM_CAP_VER ( PM_CAP_VER),
330
      .MSI_VECTOR ( MSI[2:0]),
331
      .MSI_8BIT_EN ( MSI[3]),
332
      .PWR_CON_D0_STATE ( PWR_CON_D0_STATE),
333
      .CON_SCL_FCTR_D0_STATE ( CON_SCL_FCTR_D0_STATE),
334
      .PWR_CON_D1_STATE ( PWR_CON_D1_STATE),
335
      .CON_SCL_FCTR_D1_STATE ( CON_SCL_FCTR_D1_STATE),
336
      .PWR_CON_D2_STATE ( PWR_CON_D2_STATE),
337
      .CON_SCL_FCTR_D2_STATE ( CON_SCL_FCTR_D2_STATE),
338
      .PWR_CON_D3_STATE ( PWR_CON_D3_STATE),
339
      .CON_SCL_FCTR_D3_STATE ( CON_SCL_FCTR_D3_STATE),
340
      .PWR_DIS_D0_STATE ( PWR_DIS_D0_STATE),
341
      .DIS_SCL_FCTR_D0_STATE ( DIS_SCL_FCTR_D0_STATE),
342
      .PWR_DIS_D1_STATE ( PWR_DIS_D1_STATE),
343
      .DIS_SCL_FCTR_D1_STATE ( DIS_SCL_FCTR_D1_STATE),
344
      .PWR_DIS_D2_STATE ( PWR_DIS_D2_STATE),
345
      .DIS_SCL_FCTR_D2_STATE ( DIS_SCL_FCTR_D2_STATE),
346
      .PWR_DIS_D3_STATE ( PWR_DIS_D3_STATE),
347
      .DIS_SCL_FCTR_D3_STATE ( DIS_SCL_FCTR_D3_STATE),
348
      .TXDIFFBOOST ( TX_DIFF_BOOST),
349
      .GTDEBUGPORTS ( GTDEBUGPORTS)
350
      )
351
  pcie_ep0 (
352
 
353
    // PCI Express Fabric Interface
354
    .pci_exp_txp            ( pci_exp_txp),
355
    .pci_exp_txn            ( pci_exp_txn),
356
    .pci_exp_rxp            ( pci_exp_rxp),
357
    .pci_exp_rxn            ( pci_exp_rxn),
358
 
359
`ifdef GTP_DEBUG
360
    .GTPCLK_bufg(GTPCLK_bufg),
361
    .REFCLK_OUT_bufg(REFCLK_OUT_bufg),
362
    .LINK_UP(LINK_UP),
363
    .clock_lock(clock_lock),
364
    .pll_lock(pll_lock),
365
    .core_clk(core_clk),
366
    .user_clk(user_clk),
367
`endif
368
 
369
    // GTP/X Debug ports
370
 
371
    .gt_txdiffctrl_0        ( TXDIFFCTRL),
372
    .gt_txdiffctrl_1        ( TXDIFFCTRL),
373
    .gt_txbuffctrl_0        ( TXBUFDIFFCTRL),
374
    .gt_txbuffctrl_1        ( TXBUFDIFFCTRL),
375
    .gt_txpreemphesis_0     ( TXPREEMPHASIS),
376
    .gt_txpreemphesis_1     ( TXPREEMPHASIS),
377
 
378
 
379
    .gt_dclk                ( 1'b0),
380
    .gt_daddr               ( 0),
381
    .gt_den                 ( 0),
382
    .gt_dwen                ( 0),
383
    .gt_di                  ( 0),
384
 
385
    .gt_do                  ( gt_do_x),
386
    .gt_drdy                ( gt_drdy_x),
387
 
388
 
389
    // Transaction (TRN) Interface
390
    .trn_clk                ( trn_clk),
391
    .trn_reset_n            ( trn_reset_n),
392
    .trn_lnk_up_n           ( trn_lnk_up_n),
393
 
394
    // Tx
395
    .trn_td                 ( trn_td),
396
 
397
    .trn_trem_n             ( trn_trem_n),
398
    .trn_tsof_n             ( trn_tsof_n),
399
    .trn_teof_n             ( trn_teof_n),
400
    .trn_tsrc_rdy_n         ( trn_tsrc_rdy_n),
401
    .trn_tdst_rdy_n         ( trn_tdst_rdy_n),
402
    .trn_tdst_dsc_n         ( trn_tdst_dsc_n),
403
    .trn_tsrc_dsc_n         ( trn_tsrc_dsc_n),
404
    .trn_terrfwd_n          ( trn_terrfwd_n),
405
    .trn_tbuf_av            ( trn_tbuf_av),
406
 
407
 
408
    // Rx
409
    .trn_rd                 ( trn_rd),
410
 
411
    .trn_rrem_n             ( trn_rrem_n),
412
    .trn_rsof_n             ( trn_rsof_n),
413
    .trn_reof_n             ( trn_reof_n),
414
    .trn_rsrc_rdy_n         ( trn_rsrc_rdy_n),
415
    .trn_rsrc_dsc_n         ( trn_rsrc_dsc_n),
416
    .trn_rdst_rdy_n         ( trn_rdst_rdy_n),
417
    .trn_rerrfwd_n          ( trn_rerrfwd_n),
418
    .trn_rnp_ok_n           ( trn_rnp_ok_n),
419
    .trn_rbar_hit_n         ( trn_rbar_hit_n),
420
    .trn_rfc_nph_av         ( trn_rfc_nph_av),
421
    .trn_rfc_npd_av         ( trn_rfc_npd_av),
422
    .trn_rfc_ph_av          ( trn_rfc_ph_av),
423
    .trn_rfc_pd_av          ( trn_rfc_pd_av),
424
//    trn_rfc_cplh_av        => trn_rfc_cplh_av,
425
//    trn_rfc_cpld_av        => trn_rfc_cpld_av,
426
//    trn_pfc_nph_cl         => trn_pfc_nph_cl,
427
//    trn_pfc_npd_cl         => trn_pfc_npd_cl,
428
//    trn_pfc_ph_cl          => trn_pfc_ph_cl,
429
//    trn_pfc_pd_cl          => trn_pfc_pd_cl,
430
//    trn_pfc_cplh_cl        => trn_pfc_cplh_cl,
431
//    trn_pfc_cpld_cl        => trn_pfc_cpld_cl,
432
    .trn_rcpl_streaming_n   ( trn_rcpl_streaming_n),
433
 
434
    // Host (CFG) Interface
435
    .cfg_do                 ( cfg_do),
436
    .cfg_rd_wr_done_n       ( cfg_rd_wr_done_n),
437
    .cfg_di                 ( cfg_di),
438
    .cfg_byte_en_n          ( cfg_byte_en_n),
439
    .cfg_dwaddr             ( cfg_dwaddr),
440
    .cfg_wr_en_n            ( cfg_wr_en_n),
441
    .cfg_rd_en_n            ( cfg_rd_en_n),
442
    .cfg_err_cor_n          ( cfg_err_cor_n),
443
    .cfg_err_ur_n           ( cfg_err_ur_n),
444
    .cfg_err_ecrc_n         ( cfg_err_ecrc_n),
445
    .cfg_err_cpl_timeout_n  ( cfg_err_cpl_timeout_n),
446
    .cfg_err_cpl_abort_n    ( cfg_err_cpl_abort_n),
447
    .cfg_err_cpl_unexpect_n ( cfg_err_cpl_unexpect_n),
448
    .cfg_err_posted_n       ( cfg_err_posted_n),
449
    .cfg_err_locked_n       ( cfg_err_locked_n),
450
    .cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header),
451
    .cfg_err_cpl_rdy_n      ( cfg_err_cpl_rdy_n),
452
    .cfg_interrupt_n        ( cfg_interrupt_n),
453
    .cfg_interrupt_rdy_n    ( cfg_interrupt_rdy_n),
454
    .cfg_interrupt_assert_n ( cfg_interrupt_assert_n),
455
    .cfg_interrupt_di       ( cfg_interrupt_di),
456
    .cfg_interrupt_do       ( cfg_interrupt_do),
457
    .cfg_interrupt_mmenable ( cfg_interrupt_mmenable),
458
    .cfg_interrupt_msienable ( cfg_interrupt_msienable),
459
    .cfg_turnoff_ok_n       ( 1'b1),
460
    .cfg_to_turnoff_n       ( cfg_to_turnoff_n),
461
    .cfg_pm_wake_n          ( cfg_pm_wake_n),
462
    .cfg_pcie_link_state_n  ( cfg_pcie_link_state_n),
463
    .cfg_trn_pending_n      ( cfg_trn_pending_n),
464
    .cfg_bus_number         ( cfg_bus_number),
465
    .cfg_device_number      ( cfg_device_number),
466
    .cfg_function_number    ( cfg_function_number),
467
    .cfg_dsn                ( cfg_dsn),
468
    .cfg_status             ( cfg_status),
469
    .cfg_command            ( cfg_command),
470
    .cfg_dstatus            ( cfg_dstatus),
471
    .cfg_dcommand           ( cfg_dcommand),
472
    .cfg_lstatus            ( cfg_lstatus),
473
    .cfg_lcommand           ( cfg_lcommand),
474
 
475
    // System (SYS) Interface
476
    .sys_clk              ( sys_clk),
477
    .refclkout              ( refclkout),
478
    .sys_reset_n            ( sys_reset_n),
479
    .fast_train_simulation_only ( fast_train_simulation_only)
480
  );
481
 
482
 
483
 
484
endmodule

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