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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : ctrl_pcie_x8.v
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//--------------------------------------------------------------------------------
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// Description: This is the top-level PCI Express wrapper.
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module ctrl_pcie_x8 # (
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parameter C_XDEVICE = "xc5vsx50t",
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parameter USE_V5FXT = 0,
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parameter PCI_EXP_LINK_WIDTH = 8,
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parameter PCI_EXP_INT_FREQ = 2,
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parameter PCI_EXP_REF_FREQ = 1,
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parameter PCI_EXP_TRN_DATA_WIDTH = 64,
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parameter PCI_EXP_TRN_REM_WIDTH = 8,
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parameter PCI_EXP_TRN_BUF_AV_WIDTH = 4,
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parameter PCI_EXP_BAR_HIT_WIDTH = 7,
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parameter PCI_EXP_FC_HDR_WIDTH = 8,
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parameter PCI_EXP_FC_DATA_WIDTH = 12,
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parameter PCI_EXP_CFG_DATA_WIDTH = 32,
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parameter PCI_EXP_CFG_ADDR_WIDTH = 10,
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parameter PCI_EXP_CFG_CPLHDR_WIDTH = 48,
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parameter PCI_EXP_CFG_BUSNUM_WIDTH = 8,
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parameter PCI_EXP_CFG_DEVNUM_WIDTH = 5,
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parameter PCI_EXP_CFG_FUNNUM_WIDTH = 3,
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parameter PCI_EXP_CFG_CAP_WIDTH = 16,
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parameter PCI_EXP_CFG_WIDTH = 1024,
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parameter VEN_ID_temp = 32'h00004953,
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parameter VEN_ID = VEN_ID_temp[15 : 0],
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parameter DEV_ID = 16'h5507,
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parameter REV_ID = 8'h20,
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parameter CLASS_CODE = 24'hFFFFFF,
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parameter BAR0 = 32'hFFE00000,
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parameter BAR1 = 32'hFFE00000,
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parameter BAR2 = 32'h00000000,
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parameter BAR3 = 32'h00000000,
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parameter BAR4 = 32'h00000000,
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parameter BAR5 = 32'h00000000,
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parameter CARDBUS_CIS_PTR = 32'h00000000,
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parameter SUBSYS_VEN_ID_temp = 32'h00004953,
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parameter SUBSYS_ID_temp = 32'h00000001,
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parameter SUBSYS_VEN_ID = SUBSYS_VEN_ID_temp[15 : 0],
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parameter SUBSYS_ID = SUBSYS_ID_temp[15 : 0],
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parameter XROM_BAR = 32'hFFF00001,
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parameter INTR_MSG_NUM = 5'b00000,
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parameter SLT_IMPL = 0,
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parameter DEV_PORT_TYPE = 4'b0000,
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parameter CAP_VER = 4'h1,
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parameter CAPT_SLT_PWR_LIM_SC = 2'b00,
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parameter CAPT_SLT_PWR_LIM_VA = 8'h00,
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parameter PWR_INDI_PRSNT = 0,
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parameter ATTN_INDI_PRSNT = 0,
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parameter ATTN_BUTN_PRSNT = 0,
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parameter EP_L1_ACCPT_LAT = 3'b111,
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parameter EP_L0s_ACCPT_LAT = 3'b111,
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parameter EXT_TAG_FLD_SUP = 1,
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parameter PHANTM_FUNC_SUP = 2'b01,
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parameter MPS = 3'b001,
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parameter L1_EXIT_LAT = 3'b111,
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parameter L0s_EXIT_LAT = 3'b111,
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parameter ASPM_SUP = 2'b01,
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parameter MAX_LNK_WDT = 6'b1000,
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parameter MAX_LNK_SPD = 4'b1,
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parameter ACK_TO = 16'h0204,
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parameter RPLY_TO = 16'h060d,
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parameter MSI = 4'b0000,
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parameter PCI_CONFIG_SPACE_ACCESS = 0,
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parameter EXT_CONFIG_SPACE_ACCESS = 0,
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parameter TRM_TLP_DGST_ECRC = 1,
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parameter FRCE_NOSCRMBL = 0,
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parameter TWO_PLM_ATOCFGR = 0,
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parameter PME_SUP = 5'h0,
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parameter D2_SUP = 0,
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parameter D1_SUP = 0,
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parameter AUX_CT = 3'b000,
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parameter DSI = 1,
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parameter PME_CLK = 0,
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parameter PM_CAP_VER = 3'b010,
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parameter PWR_CON_D0_STATE = 8'h0,
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parameter CON_SCL_FCTR_D0_STATE = 8'h0,
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parameter PWR_CON_D1_STATE = 8'h0,
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parameter CON_SCL_FCTR_D1_STATE = 8'h0,
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parameter PWR_CON_D2_STATE = 8'h0,
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parameter CON_SCL_FCTR_D2_STATE = 8'h0,
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parameter PWR_CON_D3_STATE = 8'h0,
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parameter CON_SCL_FCTR_D3_STATE = 8'h0,
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parameter PWR_DIS_D0_STATE = 8'h0,
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parameter DIS_SCL_FCTR_D0_STATE = 8'h0,
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parameter PWR_DIS_D1_STATE = 8'h0,
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parameter DIS_SCL_FCTR_D1_STATE = 8'h0,
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parameter PWR_DIS_D2_STATE = 8'h0,
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parameter DIS_SCL_FCTR_D2_STATE = 8'h0,
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parameter PWR_DIS_D3_STATE = 8'h0,
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parameter DIS_SCL_FCTR_D3_STATE = 8'h0,
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parameter CAL_BLK_DISABLE = 0,
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parameter SWAP_A_B_PAIRS = 0,
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parameter INFINITECOMPLETIONS = "TRUE",
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parameter VC0_CREDITS_PH = 1,
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parameter VC0_CREDITS_NPH = 1,
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parameter CPL_STREAMING_PRIORITIZE_P_NP = 1,
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parameter SLOT_CLK = "TRUE",
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parameter TX_DIFF_BOOST = "TRUE",
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parameter TXDIFFCTRL = 3'b100,
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parameter TXBUFDIFFCTRL = 3'b100,
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parameter TXPREEMPHASIS = 3'b111,
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parameter GT_Debug_Ports = 0,
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parameter GTDEBUGPORTS = 0
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)
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(
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// PCI Express Fabric Interface
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output [PCI_EXP_LINK_WIDTH-1 : 0] pci_exp_txp,
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output [PCI_EXP_LINK_WIDTH-1 : 0] pci_exp_txn,
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input [PCI_EXP_LINK_WIDTH-1 : 0] pci_exp_rxp,
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input [PCI_EXP_LINK_WIDTH-1 : 0] pci_exp_rxn,
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// Transaction (TRN) Interface
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output trn_clk,
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output trn_reset_n,
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output trn_lnk_up_n,
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// Tx
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input [PCI_EXP_TRN_DATA_WIDTH-1 : 0] trn_td,
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input [PCI_EXP_TRN_REM_WIDTH-1 : 0] trn_trem_n,
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input trn_tsof_n,
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input trn_teof_n,
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input trn_tsrc_rdy_n,
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output trn_tdst_rdy_n,
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output trn_tdst_dsc_n,
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input trn_tsrc_dsc_n,
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input trn_terrfwd_n,
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output [PCI_EXP_TRN_BUF_AV_WIDTH-1:0] trn_tbuf_av,
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// Rx
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output [PCI_EXP_TRN_DATA_WIDTH-1 : 0] trn_rd,
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output [PCI_EXP_TRN_REM_WIDTH-1 : 0] trn_rrem_n,
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output trn_rsof_n,
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output trn_reof_n,
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output trn_rsrc_rdy_n,
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output trn_rsrc_dsc_n,
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input trn_rdst_rdy_n,
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output trn_rerrfwd_n,
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input trn_rnp_ok_n,
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output [PCI_EXP_BAR_HIT_WIDTH-1 : 0] trn_rbar_hit_n,
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output [PCI_EXP_FC_HDR_WIDTH-1 : 0] trn_rfc_nph_av,
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output [PCI_EXP_FC_DATA_WIDTH-1 : 0] trn_rfc_npd_av,
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output [PCI_EXP_FC_HDR_WIDTH-1 : 0] trn_rfc_ph_av,
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output [PCI_EXP_FC_DATA_WIDTH-1 : 0] trn_rfc_pd_av,
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input trn_rcpl_streaming_n,
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// Host (CFG) Interface
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output [PCI_EXP_CFG_DATA_WIDTH-1 : 0] cfg_do,
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output cfg_rd_wr_done_n,
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input [PCI_EXP_CFG_DATA_WIDTH-1 : 0] cfg_di,
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input [PCI_EXP_CFG_DATA_WIDTH/8-1 : 0] cfg_byte_en_n,
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input [PCI_EXP_CFG_ADDR_WIDTH-1 : 0] cfg_dwaddr,
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input cfg_wr_en_n,
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input cfg_rd_en_n,
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input cfg_err_cor_n,
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input cfg_err_ur_n,
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input cfg_err_ecrc_n,
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input cfg_err_cpl_timeout_n,
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input cfg_err_cpl_abort_n,
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input cfg_err_cpl_unexpect_n,
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input cfg_err_posted_n,
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input [PCI_EXP_CFG_CPLHDR_WIDTH-1 : 0] cfg_err_tlp_cpl_header,
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output cfg_err_cpl_rdy_n,
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input cfg_err_locked_n,
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input cfg_interrupt_n,
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output cfg_interrupt_rdy_n,
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input cfg_interrupt_assert_n,
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input [7 : 0] cfg_interrupt_di,
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output [7 : 0] cfg_interrupt_do,
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output [2 : 0] cfg_interrupt_mmenable,
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output cfg_interrupt_msienable,
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output cfg_to_turnoff_n,
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input cfg_pm_wake_n,
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output [2 : 0] cfg_pcie_link_state_n,
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input cfg_trn_pending_n,
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output [PCI_EXP_CFG_BUSNUM_WIDTH-1 : 0] cfg_bus_number,
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| 250 |
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output [PCI_EXP_CFG_DEVNUM_WIDTH-1 : 0] cfg_device_number,
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output [PCI_EXP_CFG_FUNNUM_WIDTH-1 : 0] cfg_function_number,
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input [63 : 0] cfg_dsn,
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output [PCI_EXP_CFG_CAP_WIDTH-1 : 0] cfg_status,
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output [PCI_EXP_CFG_CAP_WIDTH-1 : 0] cfg_command,
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output [PCI_EXP_CFG_CAP_WIDTH-1 : 0] cfg_dstatus,
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output [PCI_EXP_CFG_CAP_WIDTH-1 : 0] cfg_dcommand,
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output [PCI_EXP_CFG_CAP_WIDTH-1 : 0] cfg_lstatus,
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output [PCI_EXP_CFG_CAP_WIDTH-1 : 0] cfg_lcommand,
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input fast_train_simulation_only,
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// System (SYS) Interface
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input sys_clk,
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// sys_clk_n : in std_logic;
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output refclkout,
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input sys_reset_n
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);
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| 268 |
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| 269 |
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wire [8*16-1 : 0] gt_do_x;
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wire [8-1 : 0] gt_drdy_x;
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| 272 |
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| 273 |
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pcie_ep_top #(
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// G_USE_DCM => 1,
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// G_USER_RESETS => 0,
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// G_SIM => 0,
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// G_CHIPSCOPE => 0,
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.USE_V5FXT ( USE_V5FXT),
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.INTF_CLK_FREQ ( PCI_EXP_INT_FREQ),
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.REF_CLK_FREQ ( PCI_EXP_REF_FREQ),
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.VEN_ID ( VEN_ID),
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.DEV_ID ( DEV_ID),
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.REV_ID ( REV_ID),
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.CLASS_CODE ( CLASS_CODE),
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.BAR0 ( BAR0),
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.BAR1 ( BAR1),
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.BAR2 ( BAR2),
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.BAR3 ( BAR3),
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.BAR4 ( BAR4),
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.BAR5 ( BAR5),
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.CARDBUS_CIS_PTR ( CARDBUS_CIS_PTR),
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.SUBSYS_VEN_ID ( SUBSYS_VEN_ID),
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.SUBSYS_ID ( SUBSYS_ID),
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.XROM_BAR ( XROM_BAR),
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.INTR_MSG_NUM ( INTR_MSG_NUM),
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.SLT_IMPL ( SLT_IMPL),
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.DEV_PORT_TYPE ( DEV_PORT_TYPE),
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.CAP_VER ( CAP_VER),
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.CAPT_SLT_PWR_LIM_SC ( CAPT_SLT_PWR_LIM_SC),
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| 302 |
|
|
.CAPT_SLT_PWR_LIM_VA ( CAPT_SLT_PWR_LIM_VA),
|
| 303 |
|
|
.PWR_INDI_PRSNT ( PWR_INDI_PRSNT),
|
| 304 |
|
|
.ATTN_INDI_PRSNT ( ATTN_INDI_PRSNT),
|
| 305 |
|
|
.ATTN_BUTN_PRSNT ( ATTN_BUTN_PRSNT),
|
| 306 |
|
|
.EP_L1_ACCPT_LAT ( EP_L1_ACCPT_LAT),
|
| 307 |
|
|
.EP_L0s_ACCPT_LAT ( EP_L0s_ACCPT_LAT),
|
| 308 |
|
|
.EXT_TAG_FLD_SUP ( EXT_TAG_FLD_SUP),
|
| 309 |
|
|
.PHANTM_FUNC_SUP ( PHANTM_FUNC_SUP),
|
| 310 |
|
|
.MPS ( MPS),
|
| 311 |
|
|
.L1_EXIT_LAT ( L1_EXIT_LAT),
|
| 312 |
|
|
.L0s_EXIT_LAT ( L0s_EXIT_LAT),
|
| 313 |
|
|
.ASPM_SUP ( ASPM_SUP),
|
| 314 |
|
|
.MAX_LNK_WDT ( MAX_LNK_WDT),
|
| 315 |
|
|
.MAX_LNK_SPD ( MAX_LNK_SPD),
|
| 316 |
|
|
.TRM_TLP_DGST_ECRC ( TRM_TLP_DGST_ECRC),
|
| 317 |
|
|
.FRCE_NOSCRMBL ( FRCE_NOSCRMBL),
|
| 318 |
|
|
.INFINITECOMPLETIONS ( INFINITECOMPLETIONS),
|
| 319 |
|
|
.VC0_CREDITS_PH ( VC0_CREDITS_PH),
|
| 320 |
|
|
.VC0_CREDITS_NPH ( VC0_CREDITS_NPH),
|
| 321 |
|
|
.CPL_STREAMING_PRIORITIZE_P_NP ( CPL_STREAMING_PRIORITIZE_P_NP),
|
| 322 |
|
|
.SLOT_CLOCK_CONFIG ( SLOT_CLK),
|
| 323 |
|
|
.PME_SUP ( PME_SUP),
|
| 324 |
|
|
.D2_SUP ( D2_SUP),
|
| 325 |
|
|
.D1_SUP ( D1_SUP),
|
| 326 |
|
|
.AUX_CT ( AUX_CT),
|
| 327 |
|
|
.DSI ( DSI),
|
| 328 |
|
|
.PME_CLK ( PME_CLK),
|
| 329 |
|
|
.PM_CAP_VER ( PM_CAP_VER),
|
| 330 |
|
|
.MSI_VECTOR ( MSI[2:0]),
|
| 331 |
|
|
.MSI_8BIT_EN ( MSI[3]),
|
| 332 |
|
|
.PWR_CON_D0_STATE ( PWR_CON_D0_STATE),
|
| 333 |
|
|
.CON_SCL_FCTR_D0_STATE ( CON_SCL_FCTR_D0_STATE),
|
| 334 |
|
|
.PWR_CON_D1_STATE ( PWR_CON_D1_STATE),
|
| 335 |
|
|
.CON_SCL_FCTR_D1_STATE ( CON_SCL_FCTR_D1_STATE),
|
| 336 |
|
|
.PWR_CON_D2_STATE ( PWR_CON_D2_STATE),
|
| 337 |
|
|
.CON_SCL_FCTR_D2_STATE ( CON_SCL_FCTR_D2_STATE),
|
| 338 |
|
|
.PWR_CON_D3_STATE ( PWR_CON_D3_STATE),
|
| 339 |
|
|
.CON_SCL_FCTR_D3_STATE ( CON_SCL_FCTR_D3_STATE),
|
| 340 |
|
|
.PWR_DIS_D0_STATE ( PWR_DIS_D0_STATE),
|
| 341 |
|
|
.DIS_SCL_FCTR_D0_STATE ( DIS_SCL_FCTR_D0_STATE),
|
| 342 |
|
|
.PWR_DIS_D1_STATE ( PWR_DIS_D1_STATE),
|
| 343 |
|
|
.DIS_SCL_FCTR_D1_STATE ( DIS_SCL_FCTR_D1_STATE),
|
| 344 |
|
|
.PWR_DIS_D2_STATE ( PWR_DIS_D2_STATE),
|
| 345 |
|
|
.DIS_SCL_FCTR_D2_STATE ( DIS_SCL_FCTR_D2_STATE),
|
| 346 |
|
|
.PWR_DIS_D3_STATE ( PWR_DIS_D3_STATE),
|
| 347 |
|
|
.DIS_SCL_FCTR_D3_STATE ( DIS_SCL_FCTR_D3_STATE),
|
| 348 |
|
|
.TXDIFFBOOST ( TX_DIFF_BOOST),
|
| 349 |
|
|
.GTDEBUGPORTS ( GTDEBUGPORTS)
|
| 350 |
|
|
)
|
| 351 |
|
|
pcie_ep0 (
|
| 352 |
|
|
|
| 353 |
|
|
// PCI Express Fabric Interface
|
| 354 |
|
|
.pci_exp_txp ( pci_exp_txp),
|
| 355 |
|
|
.pci_exp_txn ( pci_exp_txn),
|
| 356 |
|
|
.pci_exp_rxp ( pci_exp_rxp),
|
| 357 |
|
|
.pci_exp_rxn ( pci_exp_rxn),
|
| 358 |
|
|
|
| 359 |
|
|
`ifdef GTP_DEBUG
|
| 360 |
|
|
.GTPCLK_bufg(GTPCLK_bufg),
|
| 361 |
|
|
.REFCLK_OUT_bufg(REFCLK_OUT_bufg),
|
| 362 |
|
|
.LINK_UP(LINK_UP),
|
| 363 |
|
|
.clock_lock(clock_lock),
|
| 364 |
|
|
.pll_lock(pll_lock),
|
| 365 |
|
|
.core_clk(core_clk),
|
| 366 |
|
|
.user_clk(user_clk),
|
| 367 |
|
|
`endif
|
| 368 |
|
|
|
| 369 |
|
|
// GTP/X Debug ports
|
| 370 |
|
|
|
| 371 |
|
|
.gt_txdiffctrl_0 ( TXDIFFCTRL),
|
| 372 |
|
|
.gt_txdiffctrl_1 ( TXDIFFCTRL),
|
| 373 |
|
|
.gt_txbuffctrl_0 ( TXBUFDIFFCTRL),
|
| 374 |
|
|
.gt_txbuffctrl_1 ( TXBUFDIFFCTRL),
|
| 375 |
|
|
.gt_txpreemphesis_0 ( TXPREEMPHASIS),
|
| 376 |
|
|
.gt_txpreemphesis_1 ( TXPREEMPHASIS),
|
| 377 |
|
|
|
| 378 |
|
|
|
| 379 |
|
|
.gt_dclk ( 1'b0),
|
| 380 |
|
|
.gt_daddr ( 0),
|
| 381 |
|
|
.gt_den ( 0),
|
| 382 |
|
|
.gt_dwen ( 0),
|
| 383 |
|
|
.gt_di ( 0),
|
| 384 |
|
|
|
| 385 |
|
|
.gt_do ( gt_do_x),
|
| 386 |
|
|
.gt_drdy ( gt_drdy_x),
|
| 387 |
|
|
|
| 388 |
|
|
|
| 389 |
|
|
// Transaction (TRN) Interface
|
| 390 |
|
|
.trn_clk ( trn_clk),
|
| 391 |
|
|
.trn_reset_n ( trn_reset_n),
|
| 392 |
|
|
.trn_lnk_up_n ( trn_lnk_up_n),
|
| 393 |
|
|
|
| 394 |
|
|
// Tx
|
| 395 |
|
|
.trn_td ( trn_td),
|
| 396 |
|
|
|
| 397 |
|
|
.trn_trem_n ( trn_trem_n),
|
| 398 |
|
|
.trn_tsof_n ( trn_tsof_n),
|
| 399 |
|
|
.trn_teof_n ( trn_teof_n),
|
| 400 |
|
|
.trn_tsrc_rdy_n ( trn_tsrc_rdy_n),
|
| 401 |
|
|
.trn_tdst_rdy_n ( trn_tdst_rdy_n),
|
| 402 |
|
|
.trn_tdst_dsc_n ( trn_tdst_dsc_n),
|
| 403 |
|
|
.trn_tsrc_dsc_n ( trn_tsrc_dsc_n),
|
| 404 |
|
|
.trn_terrfwd_n ( trn_terrfwd_n),
|
| 405 |
|
|
.trn_tbuf_av ( trn_tbuf_av),
|
| 406 |
|
|
|
| 407 |
|
|
|
| 408 |
|
|
// Rx
|
| 409 |
|
|
.trn_rd ( trn_rd),
|
| 410 |
|
|
|
| 411 |
|
|
.trn_rrem_n ( trn_rrem_n),
|
| 412 |
|
|
.trn_rsof_n ( trn_rsof_n),
|
| 413 |
|
|
.trn_reof_n ( trn_reof_n),
|
| 414 |
|
|
.trn_rsrc_rdy_n ( trn_rsrc_rdy_n),
|
| 415 |
|
|
.trn_rsrc_dsc_n ( trn_rsrc_dsc_n),
|
| 416 |
|
|
.trn_rdst_rdy_n ( trn_rdst_rdy_n),
|
| 417 |
|
|
.trn_rerrfwd_n ( trn_rerrfwd_n),
|
| 418 |
|
|
.trn_rnp_ok_n ( trn_rnp_ok_n),
|
| 419 |
|
|
.trn_rbar_hit_n ( trn_rbar_hit_n),
|
| 420 |
|
|
.trn_rfc_nph_av ( trn_rfc_nph_av),
|
| 421 |
|
|
.trn_rfc_npd_av ( trn_rfc_npd_av),
|
| 422 |
|
|
.trn_rfc_ph_av ( trn_rfc_ph_av),
|
| 423 |
|
|
.trn_rfc_pd_av ( trn_rfc_pd_av),
|
| 424 |
|
|
// trn_rfc_cplh_av => trn_rfc_cplh_av,
|
| 425 |
|
|
// trn_rfc_cpld_av => trn_rfc_cpld_av,
|
| 426 |
|
|
// trn_pfc_nph_cl => trn_pfc_nph_cl,
|
| 427 |
|
|
// trn_pfc_npd_cl => trn_pfc_npd_cl,
|
| 428 |
|
|
// trn_pfc_ph_cl => trn_pfc_ph_cl,
|
| 429 |
|
|
// trn_pfc_pd_cl => trn_pfc_pd_cl,
|
| 430 |
|
|
// trn_pfc_cplh_cl => trn_pfc_cplh_cl,
|
| 431 |
|
|
// trn_pfc_cpld_cl => trn_pfc_cpld_cl,
|
| 432 |
|
|
.trn_rcpl_streaming_n ( trn_rcpl_streaming_n),
|
| 433 |
|
|
|
| 434 |
|
|
// Host (CFG) Interface
|
| 435 |
|
|
.cfg_do ( cfg_do),
|
| 436 |
|
|
.cfg_rd_wr_done_n ( cfg_rd_wr_done_n),
|
| 437 |
|
|
.cfg_di ( cfg_di),
|
| 438 |
|
|
.cfg_byte_en_n ( cfg_byte_en_n),
|
| 439 |
|
|
.cfg_dwaddr ( cfg_dwaddr),
|
| 440 |
|
|
.cfg_wr_en_n ( cfg_wr_en_n),
|
| 441 |
|
|
.cfg_rd_en_n ( cfg_rd_en_n),
|
| 442 |
|
|
.cfg_err_cor_n ( cfg_err_cor_n),
|
| 443 |
|
|
.cfg_err_ur_n ( cfg_err_ur_n),
|
| 444 |
|
|
.cfg_err_ecrc_n ( cfg_err_ecrc_n),
|
| 445 |
|
|
.cfg_err_cpl_timeout_n ( cfg_err_cpl_timeout_n),
|
| 446 |
|
|
.cfg_err_cpl_abort_n ( cfg_err_cpl_abort_n),
|
| 447 |
|
|
.cfg_err_cpl_unexpect_n ( cfg_err_cpl_unexpect_n),
|
| 448 |
|
|
.cfg_err_posted_n ( cfg_err_posted_n),
|
| 449 |
|
|
.cfg_err_locked_n ( cfg_err_locked_n),
|
| 450 |
|
|
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header),
|
| 451 |
|
|
.cfg_err_cpl_rdy_n ( cfg_err_cpl_rdy_n),
|
| 452 |
|
|
.cfg_interrupt_n ( cfg_interrupt_n),
|
| 453 |
|
|
.cfg_interrupt_rdy_n ( cfg_interrupt_rdy_n),
|
| 454 |
|
|
.cfg_interrupt_assert_n ( cfg_interrupt_assert_n),
|
| 455 |
|
|
.cfg_interrupt_di ( cfg_interrupt_di),
|
| 456 |
|
|
.cfg_interrupt_do ( cfg_interrupt_do),
|
| 457 |
|
|
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable),
|
| 458 |
|
|
.cfg_interrupt_msienable ( cfg_interrupt_msienable),
|
| 459 |
|
|
.cfg_turnoff_ok_n ( 1'b1),
|
| 460 |
|
|
.cfg_to_turnoff_n ( cfg_to_turnoff_n),
|
| 461 |
|
|
.cfg_pm_wake_n ( cfg_pm_wake_n),
|
| 462 |
|
|
.cfg_pcie_link_state_n ( cfg_pcie_link_state_n),
|
| 463 |
|
|
.cfg_trn_pending_n ( cfg_trn_pending_n),
|
| 464 |
|
|
.cfg_bus_number ( cfg_bus_number),
|
| 465 |
|
|
.cfg_device_number ( cfg_device_number),
|
| 466 |
|
|
.cfg_function_number ( cfg_function_number),
|
| 467 |
|
|
.cfg_dsn ( cfg_dsn),
|
| 468 |
|
|
.cfg_status ( cfg_status),
|
| 469 |
|
|
.cfg_command ( cfg_command),
|
| 470 |
|
|
.cfg_dstatus ( cfg_dstatus),
|
| 471 |
|
|
.cfg_dcommand ( cfg_dcommand),
|
| 472 |
|
|
.cfg_lstatus ( cfg_lstatus),
|
| 473 |
|
|
.cfg_lcommand ( cfg_lcommand),
|
| 474 |
|
|
|
| 475 |
|
|
// System (SYS) Interface
|
| 476 |
|
|
.sys_clk ( sys_clk),
|
| 477 |
|
|
.refclkout ( refclkout),
|
| 478 |
|
|
.sys_reset_n ( sys_reset_n),
|
| 479 |
|
|
.fast_train_simulation_only ( fast_train_simulation_only)
|
| 480 |
|
|
);
|
| 481 |
|
|
|
| 482 |
|
|
|
| 483 |
|
|
|
| 484 |
|
|
endmodule
|
