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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [pcie_blk_cf.v] - Blame information for rev 2

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2
//-----------------------------------------------------------------------------
3
//
4
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
5
//
6
// This file contains confidential and proprietary information
7
// of Xilinx, Inc. and is protected under U.S. and
8
// international copyright and other intellectual property
9
// laws.
10
//
11
// DISCLAIMER
12
// This disclaimer is not a license and does not grant any
13
// rights to the materials distributed herewith. Except as
14
// otherwise provided in a valid license issued to you by
15
// Xilinx, and to the maximum extent permitted by applicable
16
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
17
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
18
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
19
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
20
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
21
// (2) Xilinx shall not be liable (whether in contract or tort,
22
// including negligence, or under any other theory of
23
// liability) for any loss or damage of any kind or nature
24
// related to, arising under or in connection with these
25
// materials, including for any direct, or any indirect,
26
// special, incidental, or consequential loss or damage
27
// (including loss of data, profits, goodwill, or any type of
28
// loss or damage suffered as a result of any action brought
29
// by a third party) even if such damage or loss was
30
// reasonably foreseeable or Xilinx had been advised of the
31
// possibility of the same.
32
//
33
// CRITICAL APPLICATIONS
34
// Xilinx products are not designed or intended to be fail-
35
// safe, or for use in any application requiring fail-safe
36
// performance, such as life-support or safety devices or
37
// systems, Class III medical devices, nuclear facilities,
38
// applications related to the deployment of airbags, or any
39
// other applications that could lead to death, personal
40
// injury, or severe property or environmental damage
41
// (individually and collectively, "Critical
42
// Applications"). Customer assumes the sole risk and
43
// liability of any use of Xilinx products in Critical
44
// Applications, subject only to applicable laws and
45
// regulations governing limitations on product liability.
46
//
47
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
48
// PART OF THIS FILE AT ALL TIMES.
49
//
50
//-----------------------------------------------------------------------------
51
// Project    : V5-Block Plus for PCI Express
52
// File       : pcie_blk_cf.v
53
//--------------------------------------------------------------------------------
54
//--------------------------------------------------------------------------------
55
//--
56
//-- Description: PCIe Block Configuration Interface
57
//--
58
//--             
59
//--
60
//--------------------------------------------------------------------------------
61
 
62
`timescale 1ns/1ns
63
 
64
`ifndef Tcq
65
  `define Tcq 1
66
`endif
67
 
68
module pcie_blk_cf
69
(
70
       // PCIe Block clock and reset
71
 
72
       input wire         clk,
73
       input wire         rst_n,
74
 
75
       // PCIe Transaction Link Up
76
 
77
       output             trn_lnk_up_n,
78
 
79
       // PCIe Block Misc Inputs
80
 
81
       input wire         mac_link_up,
82
       input wire   [3:0] mac_negotiated_link_width,
83
       input wire   [7:0] llk_tc_status,
84
 
85
       // PCIe Block Cfg Interface
86
 
87
       input wire         io_space_enable,
88
       input wire         mem_space_enable,
89
       input wire         bus_master_enable,
90
       input wire         parity_error_response,
91
       input wire         serr_enable,
92
       input wire         msi_enable,
93
       input wire  [12:0] completer_id,
94
       input wire   [2:0] max_read_request_size,
95
       input wire   [2:0] max_payload_size,
96
 
97
       output             legacy_int_request,
98
       output             transactions_pending,
99
 
100
       output       [3:0] msi_request,
101
       input              cfg_interrupt_assert_n, // select between assert 
102
                                        // and deassert message type in legacy
103
                                        // mode
104
       input       [7:0]  cfg_interrupt_di,
105
       output      [2:0]  cfg_interrupt_mmenable, //number of MSI vectors avail
106
                                                  // from conviguration
107
       output             cfg_interrupt_msienable, // indiacates msi or legacy
108
                                                // enabled 
109
       output      [7:0]  cfg_interrupt_do,      // indiacates lowest 8bits of
110
       input              msi_8bit_en,
111
 
112
       // PCIe Block Management Interface
113
 
114
       output wire [10:0] mgmt_addr,
115
       output wire        mgmt_wren,
116
       output wire        mgmt_rden,
117
       output wire [31:0] mgmt_wdata,
118
       output wire [3:0]  mgmt_bwren,
119
       input  wire [31:0] mgmt_rdata,
120
       input  wire [16:0] mgmt_pso,
121
       //// These signals go to mgmt block to implement a workaround
122
       input  wire [63:0] llk_rx_data_d,
123
       input  wire        llk_rx_src_rdy_n,
124
       input  wire        l0_stats_cfg_received,
125
       input  wire        l0_stats_cfg_transmitted,
126
 
127
       // PCIe Soft Macro Cfg Interface
128
 
129
       output wire [31:0] cfg_do,
130
       input wire  [31:0] cfg_di,
131
       input wire  [63:0] cfg_dsn,
132
       input wire   [3:0] cfg_byte_en_n,
133
       input wire  [11:0] cfg_dwaddr,
134
       output wire        cfg_rd_wr_done_n,
135
       input wire         cfg_wr_en_n,
136
       input wire         cfg_rd_en_n,
137
       input wire         cfg_err_cor_n,
138
       input wire         cfg_err_ur_n,
139
       input wire         cfg_err_ecrc_n,
140
       input wire         cfg_err_cpl_timeout_n,
141
       input wire         cfg_err_cpl_abort_n,
142
       input wire         cfg_err_cpl_unexpect_n,
143
       input wire         cfg_err_posted_n,
144
       input wire         cfg_err_locked_n,
145
       input wire         cfg_interrupt_n,
146
       output wire        cfg_interrupt_rdy_n,
147
       input wire         cfg_turnoff_ok_n,
148
       output wire        cfg_to_turnoff_n,
149
       input wire         cfg_pm_wake_n,
150
       input wire  [47:0] cfg_err_tlp_cpl_header,
151
       output wire        cfg_err_cpl_rdy_n,
152
       input wire         cfg_trn_pending_n,
153
       output wire [31:0] cfg_rx_bar0,
154
       output wire [31:0] cfg_rx_bar1,
155
       output wire [31:0] cfg_rx_bar2,
156
       output wire [31:0] cfg_rx_bar3,
157
       output wire [31:0] cfg_rx_bar4,
158
       output wire [31:0] cfg_rx_bar5,
159
       output wire [31:0] cfg_rx_xrom,
160
       output wire [15:0] cfg_status,
161
       output wire [15:0] cfg_command,
162
       output wire [15:0] cfg_dstatus,
163
       output wire [15:0] cfg_dcommand,
164
       output wire [15:0] cfg_lstatus,
165
       output wire [15:0] cfg_lcommand,
166
       output wire [31:0] cfg_pmcsr,
167
       output wire [31:0] cfg_dcap,
168
       output wire  [7:0] cfg_bus_number,
169
       output wire  [4:0] cfg_device_number,
170
       output wire  [2:0] cfg_function_number,
171
       output wire  [2:0] cfg_pcie_link_state_n,
172
 
173
       input              rx_err_cpl_ep_n, //Rx Completion
174
       input              tx_err_wr_ep_n,  //Tx Write
175
       input              rx_err_ep_n,     //Any
176
       input              rx_err_tlp_poisoned_n,
177
       input              rx_err_cpl_abort_n,
178
       input              rx_err_cpl_ur_n,
179
       input              rx_err_tlp_ur_n,
180
       input              rx_err_tlp_ur_lock_n,
181
       input              rx_err_tlp_p_cpl_n,
182
       input              rx_err_tlp_malformed_n,
183
       input       [47:0] rx_err_tlp_hdr,
184
 
185
       output wire [63:0] cfg_arb_td,
186
       output wire  [7:0] cfg_arb_trem_n,
187
       output wire        cfg_arb_tsof_n,
188
       output wire        cfg_arb_teof_n,
189
       output wire        cfg_arb_tsrc_rdy_n,
190
       input              cfg_arb_tdst_rdy_n,
191
 
192
       input        [6:0] l0_dll_error_vector,
193
       input        [1:0] l0_rx_mac_link_error,
194
       output wire        l0_set_unsupported_request_other_error,
195
       output wire        l0_set_detected_fatal_error,
196
       output wire        l0_set_detected_nonfatal_error,
197
       output wire        l0_set_detected_corr_error,
198
       output wire        l0_set_user_system_error,
199
       output wire        l0_set_user_master_data_parity,
200
       output wire        l0_set_user_signaled_target_abort,
201
       output wire        l0_set_user_received_target_abort,
202
       output wire        l0_set_user_received_master_abort,
203
       output wire        l0_set_user_detected_parity_error,
204
 
205
       input        [3:0] l0_ltssm_state,
206
       input              l0_pwr_turn_off_req,
207
       output wire        l0_pme_req_in,
208
       input              l0_pme_ack
209
 
210
);
211
 
212
 
213
 assign transactions_pending = ~cfg_trn_pending_n;
214
 
215
 assign cfg_pcie_link_state_n = {~(l0_ltssm_state == 4'b0110),  //L1
216
                                 ~(l0_ltssm_state == 4'b0101),  //L0s
217
                                 ~(l0_ltssm_state == 4'b0100)}; //L0
218
 
219
 wire  [49:0] cmt_rd_hdr;
220
 wire  [49:0] cfg_rd_hdr;
221
 wire  [49:0] request_data;
222
 wire  [15:0] cfg_msgctrl;
223
 wire  [31:0] cfg_msgladdr;
224
 wire  [31:0] cfg_msguaddr;
225
 wire  [15:0] cfg_msgdata;
226
 wire         send_cor;
227
 wire         send_nfl;
228
 wire         send_ftl;
229
 wire         send_cplt;
230
 wire         send_cplu;
231
 wire         send_pmeack;
232
 wire         send_intr32;
233
 wire         send_intr64;
234
 wire         grant;
235
 wire         cs_is_cplu;
236
 wire         cs_is_cplt;
237
 wire         cs_is_cor;
238
 wire         cs_is_nfl;
239
 wire         cs_is_ftl;
240
 wire         cs_is_pm;
241
 wire         cs_is_intr;
242
 reg   [12:0] completer_id_reg = 0;
243
 reg          llk_tc_status_reg;
244
 wire  [31:0] mis_laddr;
245
 wire  [31:0] mis_haddr;
246
 
247
   wire [7:0] intr_vector;
248
   wire [1:0] intr_req_type;
249
 
250
always @(posedge clk) begin
251
  completer_id_reg <= #`Tcq completer_id;
252
  llk_tc_status_reg <= #`Tcq llk_tc_status[0];
253
end
254
 
255
assign trn_lnk_up_n = ~llk_tc_status_reg;
256
 
257
 
258
pcie_blk_cf_mgmt management_interface
259
(
260
       .clk                 ( clk ),
261
       .rst_n               ( rst_n ),
262
       .completer_id        ( completer_id_reg ),
263
       .mgmt_addr           ( mgmt_addr ),
264
       .mgmt_wren           ( mgmt_wren ),
265
       .mgmt_rden           ( mgmt_rden ),
266
       .mgmt_wdata          ( mgmt_wdata ),
267
       .mgmt_bwren          ( mgmt_bwren ),
268
       .mgmt_rdata          ( mgmt_rdata ),
269
       .mgmt_pso            ( mgmt_pso ),
270
       .cfg_dsn             ( cfg_dsn ),
271
       .cfg_do              ( cfg_do ),
272
       .cfg_rd_wr_done_n    ( cfg_rd_wr_done_n ),
273
       .cfg_dwaddr          ( cfg_dwaddr ),
274
       .cfg_rd_en_n         ( cfg_rd_en_n ),
275
       .cfg_rx_bar0         ( cfg_rx_bar0 ),
276
       .cfg_rx_bar1         ( cfg_rx_bar1 ),
277
       .cfg_rx_bar2         ( cfg_rx_bar2 ),
278
       .cfg_rx_bar3         ( cfg_rx_bar3 ),
279
       .cfg_rx_bar4         ( cfg_rx_bar4 ),
280
       .cfg_rx_bar5         ( cfg_rx_bar5 ),
281
       .cfg_rx_xrom         ( cfg_rx_xrom ),
282
       .cfg_status          ( cfg_status ),
283
       .cfg_command         ( cfg_command ),
284
       .cfg_dstatus         ( cfg_dstatus ),
285
       .cfg_dcommand        ( cfg_dcommand ),
286
       .cfg_lstatus         ( cfg_lstatus ),
287
       .cfg_lcommand        ( cfg_lcommand ),
288
       .cfg_pmcsr           ( cfg_pmcsr ),
289
       .cfg_dcap            ( cfg_dcap ),
290
       .cfg_msgctrl         ( cfg_msgctrl ),
291
       .cfg_msgladdr        ( cfg_msgladdr ),
292
       .cfg_msguaddr        ( cfg_msguaddr ),
293
       .cfg_msgdata         ( cfg_msgdata ),
294
       .cfg_bus_number      ( cfg_bus_number ),
295
       .cfg_device_number   ( cfg_device_number ),
296
       .cfg_function_number ( cfg_function_number ),
297
       //// These signals go to mgmt block to implement a workaround
298
       .llk_rx_data_d            ( llk_rx_data_d ),
299
       .llk_rx_src_rdy_n         ( llk_rx_src_rdy_n ),
300
       .l0_dll_error_vector      ( l0_dll_error_vector ),
301
       .l0_rx_mac_link_error     ( l0_rx_mac_link_error ),
302
       .l0_stats_cfg_received    ( l0_stats_cfg_received ),
303
       .l0_stats_cfg_transmitted ( l0_stats_cfg_transmitted ),
304
       .l0_set_unsupported_request_other_error( l0_set_unsupported_request_other_error ),
305
       .l0_set_detected_corr_error            ( l0_set_detected_corr_error )
306
 
307
);
308
 
309
pcie_blk_cf_err error_manager
310
(
311
       .clk                    ( clk ),
312
       .rst_n                  ( rst_n ),
313
       .cfg_err_cor_n          ( cfg_err_cor_n ),
314
       .cfg_err_ur_n           ( cfg_err_ur_n ),
315
       .cfg_err_ecrc_n         ( cfg_err_ecrc_n ),
316
       .cfg_err_cpl_timeout_n  ( cfg_err_cpl_timeout_n ),
317
       .cfg_err_cpl_abort_n    ( cfg_err_cpl_abort_n ),
318
       .cfg_err_cpl_unexpect_n ( cfg_err_cpl_unexpect_n ),
319
       .cfg_err_posted_n       ( cfg_err_posted_n ),
320
       .cfg_err_locked_n       ( cfg_err_locked_n ),
321
       .cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
322
       .cfg_err_cpl_rdy_n      ( cfg_err_cpl_rdy_n ),
323
       .rx_err_cpl_ep_n        ( rx_err_cpl_ep_n ),
324
       .tx_err_wr_ep_n         ( tx_err_wr_ep_n ),
325
       .rx_err_ep_n            ( rx_err_ep_n ),
326
       .rx_err_tlp_poisoned_n  ( rx_err_tlp_poisoned_n ),
327
       .rx_err_cpl_abort_n     ( rx_err_cpl_abort_n ),
328
       .rx_err_cpl_ur_n        ( rx_err_cpl_ur_n ),
329
       .rx_err_tlp_ur_n        ( rx_err_tlp_ur_n ),
330
       .rx_err_tlp_ur_lock_n   ( rx_err_tlp_ur_lock_n ),
331
       .rx_err_tlp_p_cpl_n     ( rx_err_tlp_p_cpl_n ),
332
       .rx_err_tlp_malformed_n ( rx_err_tlp_malformed_n ),
333
       .rx_err_tlp_hdr         ( rx_err_tlp_hdr ),
334
       .send_cor               ( send_cor ),
335
       .send_nfl               ( send_nfl ),
336
       .send_ftl               ( send_ftl ),
337
       .send_cplt              ( send_cplt ),
338
       .send_cplu              ( send_cplu ),
339
       .cmt_rd_hdr             ( cmt_rd_hdr ),
340
       .cfg_rd_hdr             ( cfg_rd_hdr ),
341
       .request_data           ( request_data ),
342
       .grant                  ( grant ),
343
       .cs_is_cplu             ( cs_is_cplu ),
344
       .cs_is_cplt             ( cs_is_cplt ),
345
       .cs_is_cor              ( cs_is_cor ),
346
       .cs_is_nfl              ( cs_is_nfl ),
347
       .cs_is_ftl              ( cs_is_ftl ),
348
       .l0_dll_error_vector               ( l0_dll_error_vector ),
349
       .l0_rx_mac_link_error              ( l0_rx_mac_link_error ),
350
       .l0_mac_link_up                    ( mac_link_up ),
351
       .l0_set_unsupported_request_other_error( l0_set_unsupported_request_other_error ),
352
       .l0_set_detected_fatal_error       ( l0_set_detected_fatal_error ),
353
       .l0_set_detected_nonfatal_error    ( l0_set_detected_nonfatal_error ),
354
       .l0_set_detected_corr_error        ( l0_set_detected_corr_error ),
355
       .l0_set_user_system_error          ( l0_set_user_system_error ),
356
       .l0_set_user_master_data_parity    ( l0_set_user_master_data_parity ),
357
       .l0_set_user_signaled_target_abort ( l0_set_user_signaled_target_abort ),
358
       .l0_set_user_received_target_abort ( l0_set_user_received_target_abort ),
359
       .l0_set_user_received_master_abort ( l0_set_user_received_master_abort ),
360
       .l0_set_user_detected_parity_error ( l0_set_user_detected_parity_error ),
361
       .cfg_dcommand           ( cfg_dcommand ),
362
       .cfg_command            ( cfg_command ),
363
       .serr_en                ( serr_enable )
364
);
365
 
366
pcie_blk_cf_arb cfg_arb
367
(
368
       .clk                    ( clk ),
369
       .rst_n                  ( rst_n ),
370
       .cfg_bus_number         ( cfg_bus_number ),
371
       .cfg_device_number      ( cfg_device_number ),
372
       .cfg_function_number    ( cfg_function_number ),
373
       .msi_data               ( cfg_msgdata ),
374
       .msi_laddr              ( cfg_msgladdr ),
375
       .msi_haddr              ( cfg_msguaddr ),
376
       .send_cor               ( send_cor ),
377
       .send_nfl               ( send_nfl ),
378
       .send_ftl               ( send_ftl ),
379
       .send_cplt              ( send_cplt ),
380
       .send_cplu              ( send_cplu ),
381
       .send_pmeack            ( send_pmeack ),
382
       .cmt_rd_hdr             ( cmt_rd_hdr ),
383
       .cfg_rd_hdr             ( cfg_rd_hdr ),
384
       .request_data           ( request_data ),
385
       .grant                  ( grant ),
386
       .cs_is_cplu             ( cs_is_cplu ),
387
       .cs_is_cplt             ( cs_is_cplt ),
388
       .cs_is_cor              ( cs_is_cor ),
389
       .cs_is_nfl              ( cs_is_nfl ),
390
       .cs_is_ftl              ( cs_is_ftl ),
391
       .cs_is_pm               ( cs_is_pm ),
392
       .cs_is_intr             ( cs_is_intr ),
393
       .intr_vector( intr_vector ),
394
       .intr_req_type( intr_req_type ),
395
       .intr_req_valid         ( intr_req_valid ),
396
       .cfg_arb_td             ( cfg_arb_td ),
397
       .cfg_arb_trem_n         ( cfg_arb_trem_n ),
398
       .cfg_arb_tsof_n         ( cfg_arb_tsof_n ),
399
       .cfg_arb_teof_n         ( cfg_arb_teof_n ),
400
       .cfg_arb_tsrc_rdy_n     ( cfg_arb_tsrc_rdy_n ),
401
       .cfg_arb_tdst_rdy_n     ( cfg_arb_tdst_rdy_n )
402
);
403
 
404
pcie_blk_cf_pwr pwr_interface
405
(
406
       .clk                ( clk ),
407
       .rst_n              ( rst_n ),
408
       .cfg_turnoff_ok_n   ( cfg_turnoff_ok_n ),
409
       .cfg_to_turnoff_n   ( cfg_to_turnoff_n ),
410
       .cfg_pm_wake_n      ( cfg_pm_wake_n ),
411
       .send_pmeack        ( send_pmeack ),
412
       .cs_is_pm           ( cs_is_pm ),
413
       .grant              ( grant ),
414
       .l0_pwr_turn_off_req ( l0_pwr_turn_off_req ),
415
       .l0_pme_req_in      ( l0_pme_req_in ),
416
       .l0_pme_ack         ( l0_pme_ack )
417
);
418
 
419
pcie_soft_cf_int interrupt_interface
420
(
421
       // Clock & Reset
422
       .clk                 ( clk ),                               // I
423
       .rst_n               ( rst_n ),                             // I
424
       // Interface to Arbitor
425
       .cs_is_intr          ( cs_is_intr ),
426
       .grant               ( grant ),
427
       .cfg_msguaddr        ( cfg_msguaddr ),
428
       // PCIe Block Interrupt Ports
429
       .msi_enable          ( msi_enable ),                        // I
430
       .msi_request         ( msi_request ),                       // O[3:0]
431
       .legacy_int_request  ( legacy_int_request ),                // O
432
       // LocalLink Interrupt Ports
433
       .cfg_interrupt_n     ( cfg_interrupt_n ),                   // I
434
       .cfg_interrupt_rdy_n ( cfg_interrupt_rdy_n ),                // O
435
 
436
       .cfg_interrupt_assert_n(cfg_interrupt_assert_n),            // I
437
       .cfg_interrupt_di(cfg_interrupt_di),                        // I[7:0]
438
 
439
       .cfg_interrupt_mmenable(cfg_interrupt_mmenable),            // O[2:0]
440
       .cfg_interrupt_do(cfg_interrupt_do),                        // O[7:0]
441
       .cfg_interrupt_msienable(cfg_interrupt_msienable),          // O
442
       .intr_vector(intr_vector),                                  // O[7:0]
443
       .msi_8bit_en(msi_8bit_en),                                     // I
444
       .msi_laddr(cfg_msgladdr),                                   // I[31:0]
445
       .msi_haddr(cfg_msguaddr),                                   // I[31:0]
446
 
447
       .cfg_command(cfg_command),
448
       .cfg_msgctrl(cfg_msgctrl),
449
       .cfg_msgdata(cfg_msgdata),
450
 
451
       .signaledint(signaledint),
452
       .intr_req_valid(intr_req_valid),
453
       .intr_req_type(intr_req_type)
454
 
455
 
456
);
457
 
458
endmodule // pcie_blk_cf

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