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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : pcie_blk_cf.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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//--
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//-- Description: PCIe Block Configuration Interface
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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`ifndef Tcq
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`define Tcq 1
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`endif
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module pcie_blk_cf
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(
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// PCIe Block clock and reset
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input wire clk,
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input wire rst_n,
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// PCIe Transaction Link Up
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output trn_lnk_up_n,
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// PCIe Block Misc Inputs
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input wire mac_link_up,
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input wire [3:0] mac_negotiated_link_width,
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input wire [7:0] llk_tc_status,
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// PCIe Block Cfg Interface
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input wire io_space_enable,
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input wire mem_space_enable,
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input wire bus_master_enable,
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input wire parity_error_response,
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input wire serr_enable,
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input wire msi_enable,
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input wire [12:0] completer_id,
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input wire [2:0] max_read_request_size,
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input wire [2:0] max_payload_size,
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output legacy_int_request,
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output transactions_pending,
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output [3:0] msi_request,
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input cfg_interrupt_assert_n, // select between assert
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// and deassert message type in legacy
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// mode
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input [7:0] cfg_interrupt_di,
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output [2:0] cfg_interrupt_mmenable, //number of MSI vectors avail
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// from conviguration
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output cfg_interrupt_msienable, // indiacates msi or legacy
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// enabled
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output [7:0] cfg_interrupt_do, // indiacates lowest 8bits of
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input msi_8bit_en,
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// PCIe Block Management Interface
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output wire [10:0] mgmt_addr,
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output wire mgmt_wren,
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output wire mgmt_rden,
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output wire [31:0] mgmt_wdata,
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output wire [3:0] mgmt_bwren,
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input wire [31:0] mgmt_rdata,
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input wire [16:0] mgmt_pso,
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//// These signals go to mgmt block to implement a workaround
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input wire [63:0] llk_rx_data_d,
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input wire llk_rx_src_rdy_n,
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input wire l0_stats_cfg_received,
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input wire l0_stats_cfg_transmitted,
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// PCIe Soft Macro Cfg Interface
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output wire [31:0] cfg_do,
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input wire [31:0] cfg_di,
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input wire [63:0] cfg_dsn,
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input wire [3:0] cfg_byte_en_n,
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input wire [11:0] cfg_dwaddr,
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output wire cfg_rd_wr_done_n,
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input wire cfg_wr_en_n,
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input wire cfg_rd_en_n,
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input wire cfg_err_cor_n,
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input wire cfg_err_ur_n,
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input wire cfg_err_ecrc_n,
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input wire cfg_err_cpl_timeout_n,
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input wire cfg_err_cpl_abort_n,
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input wire cfg_err_cpl_unexpect_n,
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input wire cfg_err_posted_n,
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input wire cfg_err_locked_n,
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input wire cfg_interrupt_n,
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output wire cfg_interrupt_rdy_n,
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input wire cfg_turnoff_ok_n,
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output wire cfg_to_turnoff_n,
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input wire cfg_pm_wake_n,
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input wire [47:0] cfg_err_tlp_cpl_header,
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output wire cfg_err_cpl_rdy_n,
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input wire cfg_trn_pending_n,
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output wire [31:0] cfg_rx_bar0,
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output wire [31:0] cfg_rx_bar1,
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output wire [31:0] cfg_rx_bar2,
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output wire [31:0] cfg_rx_bar3,
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output wire [31:0] cfg_rx_bar4,
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output wire [31:0] cfg_rx_bar5,
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output wire [31:0] cfg_rx_xrom,
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output wire [15:0] cfg_status,
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output wire [15:0] cfg_command,
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output wire [15:0] cfg_dstatus,
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output wire [15:0] cfg_dcommand,
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output wire [15:0] cfg_lstatus,
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output wire [15:0] cfg_lcommand,
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output wire [31:0] cfg_pmcsr,
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output wire [31:0] cfg_dcap,
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output wire [7:0] cfg_bus_number,
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output wire [4:0] cfg_device_number,
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output wire [2:0] cfg_function_number,
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output wire [2:0] cfg_pcie_link_state_n,
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input rx_err_cpl_ep_n, //Rx Completion
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input tx_err_wr_ep_n, //Tx Write
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input rx_err_ep_n, //Any
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input rx_err_tlp_poisoned_n,
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input rx_err_cpl_abort_n,
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input rx_err_cpl_ur_n,
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input rx_err_tlp_ur_n,
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input rx_err_tlp_ur_lock_n,
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input rx_err_tlp_p_cpl_n,
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input rx_err_tlp_malformed_n,
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input [47:0] rx_err_tlp_hdr,
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output wire [63:0] cfg_arb_td,
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output wire [7:0] cfg_arb_trem_n,
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output wire cfg_arb_tsof_n,
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output wire cfg_arb_teof_n,
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output wire cfg_arb_tsrc_rdy_n,
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input cfg_arb_tdst_rdy_n,
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input [6:0] l0_dll_error_vector,
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input [1:0] l0_rx_mac_link_error,
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output wire l0_set_unsupported_request_other_error,
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output wire l0_set_detected_fatal_error,
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output wire l0_set_detected_nonfatal_error,
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output wire l0_set_detected_corr_error,
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output wire l0_set_user_system_error,
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output wire l0_set_user_master_data_parity,
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output wire l0_set_user_signaled_target_abort,
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output wire l0_set_user_received_target_abort,
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output wire l0_set_user_received_master_abort,
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output wire l0_set_user_detected_parity_error,
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input [3:0] l0_ltssm_state,
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input l0_pwr_turn_off_req,
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output wire l0_pme_req_in,
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input l0_pme_ack
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);
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assign transactions_pending = ~cfg_trn_pending_n;
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assign cfg_pcie_link_state_n = {~(l0_ltssm_state == 4'b0110), //L1
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~(l0_ltssm_state == 4'b0101), //L0s
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~(l0_ltssm_state == 4'b0100)}; //L0
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wire [49:0] cmt_rd_hdr;
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wire [49:0] cfg_rd_hdr;
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wire [49:0] request_data;
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wire [15:0] cfg_msgctrl;
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wire [31:0] cfg_msgladdr;
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wire [31:0] cfg_msguaddr;
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wire [15:0] cfg_msgdata;
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wire send_cor;
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wire send_nfl;
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wire send_ftl;
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wire send_cplt;
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wire send_cplu;
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wire send_pmeack;
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wire send_intr32;
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wire send_intr64;
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wire grant;
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wire cs_is_cplu;
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wire cs_is_cplt;
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wire cs_is_cor;
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wire cs_is_nfl;
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wire cs_is_ftl;
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wire cs_is_pm;
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wire cs_is_intr;
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reg [12:0] completer_id_reg = 0;
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reg llk_tc_status_reg;
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wire [31:0] mis_laddr;
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wire [31:0] mis_haddr;
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wire [7:0] intr_vector;
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wire [1:0] intr_req_type;
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always @(posedge clk) begin
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completer_id_reg <= #`Tcq completer_id;
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llk_tc_status_reg <= #`Tcq llk_tc_status[0];
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end
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assign trn_lnk_up_n = ~llk_tc_status_reg;
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pcie_blk_cf_mgmt management_interface
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(
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.clk ( clk ),
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| 261 |
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.rst_n ( rst_n ),
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| 262 |
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.completer_id ( completer_id_reg ),
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| 263 |
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.mgmt_addr ( mgmt_addr ),
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| 264 |
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.mgmt_wren ( mgmt_wren ),
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| 265 |
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.mgmt_rden ( mgmt_rden ),
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| 266 |
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.mgmt_wdata ( mgmt_wdata ),
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| 267 |
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.mgmt_bwren ( mgmt_bwren ),
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| 268 |
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.mgmt_rdata ( mgmt_rdata ),
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| 269 |
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.mgmt_pso ( mgmt_pso ),
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| 270 |
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.cfg_dsn ( cfg_dsn ),
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| 271 |
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.cfg_do ( cfg_do ),
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| 272 |
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.cfg_rd_wr_done_n ( cfg_rd_wr_done_n ),
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| 273 |
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.cfg_dwaddr ( cfg_dwaddr ),
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| 274 |
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.cfg_rd_en_n ( cfg_rd_en_n ),
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| 275 |
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.cfg_rx_bar0 ( cfg_rx_bar0 ),
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| 276 |
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.cfg_rx_bar1 ( cfg_rx_bar1 ),
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| 277 |
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.cfg_rx_bar2 ( cfg_rx_bar2 ),
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| 278 |
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.cfg_rx_bar3 ( cfg_rx_bar3 ),
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| 279 |
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.cfg_rx_bar4 ( cfg_rx_bar4 ),
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| 280 |
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.cfg_rx_bar5 ( cfg_rx_bar5 ),
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| 281 |
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.cfg_rx_xrom ( cfg_rx_xrom ),
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| 282 |
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.cfg_status ( cfg_status ),
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| 283 |
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.cfg_command ( cfg_command ),
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| 284 |
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.cfg_dstatus ( cfg_dstatus ),
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| 285 |
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.cfg_dcommand ( cfg_dcommand ),
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| 286 |
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.cfg_lstatus ( cfg_lstatus ),
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| 287 |
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.cfg_lcommand ( cfg_lcommand ),
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| 288 |
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.cfg_pmcsr ( cfg_pmcsr ),
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| 289 |
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.cfg_dcap ( cfg_dcap ),
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| 290 |
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.cfg_msgctrl ( cfg_msgctrl ),
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| 291 |
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.cfg_msgladdr ( cfg_msgladdr ),
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| 292 |
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.cfg_msguaddr ( cfg_msguaddr ),
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| 293 |
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.cfg_msgdata ( cfg_msgdata ),
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| 294 |
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.cfg_bus_number ( cfg_bus_number ),
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| 295 |
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.cfg_device_number ( cfg_device_number ),
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| 296 |
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.cfg_function_number ( cfg_function_number ),
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| 297 |
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//// These signals go to mgmt block to implement a workaround
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| 298 |
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.llk_rx_data_d ( llk_rx_data_d ),
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| 299 |
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.llk_rx_src_rdy_n ( llk_rx_src_rdy_n ),
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| 300 |
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.l0_dll_error_vector ( l0_dll_error_vector ),
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| 301 |
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.l0_rx_mac_link_error ( l0_rx_mac_link_error ),
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| 302 |
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.l0_stats_cfg_received ( l0_stats_cfg_received ),
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| 303 |
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.l0_stats_cfg_transmitted ( l0_stats_cfg_transmitted ),
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| 304 |
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.l0_set_unsupported_request_other_error( l0_set_unsupported_request_other_error ),
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| 305 |
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.l0_set_detected_corr_error ( l0_set_detected_corr_error )
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| 306 |
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| 307 |
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);
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| 308 |
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| 309 |
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pcie_blk_cf_err error_manager
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| 310 |
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(
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| 311 |
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.clk ( clk ),
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| 312 |
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.rst_n ( rst_n ),
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| 313 |
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.cfg_err_cor_n ( cfg_err_cor_n ),
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| 314 |
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.cfg_err_ur_n ( cfg_err_ur_n ),
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| 315 |
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.cfg_err_ecrc_n ( cfg_err_ecrc_n ),
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| 316 |
|
|
.cfg_err_cpl_timeout_n ( cfg_err_cpl_timeout_n ),
|
| 317 |
|
|
.cfg_err_cpl_abort_n ( cfg_err_cpl_abort_n ),
|
| 318 |
|
|
.cfg_err_cpl_unexpect_n ( cfg_err_cpl_unexpect_n ),
|
| 319 |
|
|
.cfg_err_posted_n ( cfg_err_posted_n ),
|
| 320 |
|
|
.cfg_err_locked_n ( cfg_err_locked_n ),
|
| 321 |
|
|
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
|
| 322 |
|
|
.cfg_err_cpl_rdy_n ( cfg_err_cpl_rdy_n ),
|
| 323 |
|
|
.rx_err_cpl_ep_n ( rx_err_cpl_ep_n ),
|
| 324 |
|
|
.tx_err_wr_ep_n ( tx_err_wr_ep_n ),
|
| 325 |
|
|
.rx_err_ep_n ( rx_err_ep_n ),
|
| 326 |
|
|
.rx_err_tlp_poisoned_n ( rx_err_tlp_poisoned_n ),
|
| 327 |
|
|
.rx_err_cpl_abort_n ( rx_err_cpl_abort_n ),
|
| 328 |
|
|
.rx_err_cpl_ur_n ( rx_err_cpl_ur_n ),
|
| 329 |
|
|
.rx_err_tlp_ur_n ( rx_err_tlp_ur_n ),
|
| 330 |
|
|
.rx_err_tlp_ur_lock_n ( rx_err_tlp_ur_lock_n ),
|
| 331 |
|
|
.rx_err_tlp_p_cpl_n ( rx_err_tlp_p_cpl_n ),
|
| 332 |
|
|
.rx_err_tlp_malformed_n ( rx_err_tlp_malformed_n ),
|
| 333 |
|
|
.rx_err_tlp_hdr ( rx_err_tlp_hdr ),
|
| 334 |
|
|
.send_cor ( send_cor ),
|
| 335 |
|
|
.send_nfl ( send_nfl ),
|
| 336 |
|
|
.send_ftl ( send_ftl ),
|
| 337 |
|
|
.send_cplt ( send_cplt ),
|
| 338 |
|
|
.send_cplu ( send_cplu ),
|
| 339 |
|
|
.cmt_rd_hdr ( cmt_rd_hdr ),
|
| 340 |
|
|
.cfg_rd_hdr ( cfg_rd_hdr ),
|
| 341 |
|
|
.request_data ( request_data ),
|
| 342 |
|
|
.grant ( grant ),
|
| 343 |
|
|
.cs_is_cplu ( cs_is_cplu ),
|
| 344 |
|
|
.cs_is_cplt ( cs_is_cplt ),
|
| 345 |
|
|
.cs_is_cor ( cs_is_cor ),
|
| 346 |
|
|
.cs_is_nfl ( cs_is_nfl ),
|
| 347 |
|
|
.cs_is_ftl ( cs_is_ftl ),
|
| 348 |
|
|
.l0_dll_error_vector ( l0_dll_error_vector ),
|
| 349 |
|
|
.l0_rx_mac_link_error ( l0_rx_mac_link_error ),
|
| 350 |
|
|
.l0_mac_link_up ( mac_link_up ),
|
| 351 |
|
|
.l0_set_unsupported_request_other_error( l0_set_unsupported_request_other_error ),
|
| 352 |
|
|
.l0_set_detected_fatal_error ( l0_set_detected_fatal_error ),
|
| 353 |
|
|
.l0_set_detected_nonfatal_error ( l0_set_detected_nonfatal_error ),
|
| 354 |
|
|
.l0_set_detected_corr_error ( l0_set_detected_corr_error ),
|
| 355 |
|
|
.l0_set_user_system_error ( l0_set_user_system_error ),
|
| 356 |
|
|
.l0_set_user_master_data_parity ( l0_set_user_master_data_parity ),
|
| 357 |
|
|
.l0_set_user_signaled_target_abort ( l0_set_user_signaled_target_abort ),
|
| 358 |
|
|
.l0_set_user_received_target_abort ( l0_set_user_received_target_abort ),
|
| 359 |
|
|
.l0_set_user_received_master_abort ( l0_set_user_received_master_abort ),
|
| 360 |
|
|
.l0_set_user_detected_parity_error ( l0_set_user_detected_parity_error ),
|
| 361 |
|
|
.cfg_dcommand ( cfg_dcommand ),
|
| 362 |
|
|
.cfg_command ( cfg_command ),
|
| 363 |
|
|
.serr_en ( serr_enable )
|
| 364 |
|
|
);
|
| 365 |
|
|
|
| 366 |
|
|
pcie_blk_cf_arb cfg_arb
|
| 367 |
|
|
(
|
| 368 |
|
|
.clk ( clk ),
|
| 369 |
|
|
.rst_n ( rst_n ),
|
| 370 |
|
|
.cfg_bus_number ( cfg_bus_number ),
|
| 371 |
|
|
.cfg_device_number ( cfg_device_number ),
|
| 372 |
|
|
.cfg_function_number ( cfg_function_number ),
|
| 373 |
|
|
.msi_data ( cfg_msgdata ),
|
| 374 |
|
|
.msi_laddr ( cfg_msgladdr ),
|
| 375 |
|
|
.msi_haddr ( cfg_msguaddr ),
|
| 376 |
|
|
.send_cor ( send_cor ),
|
| 377 |
|
|
.send_nfl ( send_nfl ),
|
| 378 |
|
|
.send_ftl ( send_ftl ),
|
| 379 |
|
|
.send_cplt ( send_cplt ),
|
| 380 |
|
|
.send_cplu ( send_cplu ),
|
| 381 |
|
|
.send_pmeack ( send_pmeack ),
|
| 382 |
|
|
.cmt_rd_hdr ( cmt_rd_hdr ),
|
| 383 |
|
|
.cfg_rd_hdr ( cfg_rd_hdr ),
|
| 384 |
|
|
.request_data ( request_data ),
|
| 385 |
|
|
.grant ( grant ),
|
| 386 |
|
|
.cs_is_cplu ( cs_is_cplu ),
|
| 387 |
|
|
.cs_is_cplt ( cs_is_cplt ),
|
| 388 |
|
|
.cs_is_cor ( cs_is_cor ),
|
| 389 |
|
|
.cs_is_nfl ( cs_is_nfl ),
|
| 390 |
|
|
.cs_is_ftl ( cs_is_ftl ),
|
| 391 |
|
|
.cs_is_pm ( cs_is_pm ),
|
| 392 |
|
|
.cs_is_intr ( cs_is_intr ),
|
| 393 |
|
|
.intr_vector( intr_vector ),
|
| 394 |
|
|
.intr_req_type( intr_req_type ),
|
| 395 |
|
|
.intr_req_valid ( intr_req_valid ),
|
| 396 |
|
|
.cfg_arb_td ( cfg_arb_td ),
|
| 397 |
|
|
.cfg_arb_trem_n ( cfg_arb_trem_n ),
|
| 398 |
|
|
.cfg_arb_tsof_n ( cfg_arb_tsof_n ),
|
| 399 |
|
|
.cfg_arb_teof_n ( cfg_arb_teof_n ),
|
| 400 |
|
|
.cfg_arb_tsrc_rdy_n ( cfg_arb_tsrc_rdy_n ),
|
| 401 |
|
|
.cfg_arb_tdst_rdy_n ( cfg_arb_tdst_rdy_n )
|
| 402 |
|
|
);
|
| 403 |
|
|
|
| 404 |
|
|
pcie_blk_cf_pwr pwr_interface
|
| 405 |
|
|
(
|
| 406 |
|
|
.clk ( clk ),
|
| 407 |
|
|
.rst_n ( rst_n ),
|
| 408 |
|
|
.cfg_turnoff_ok_n ( cfg_turnoff_ok_n ),
|
| 409 |
|
|
.cfg_to_turnoff_n ( cfg_to_turnoff_n ),
|
| 410 |
|
|
.cfg_pm_wake_n ( cfg_pm_wake_n ),
|
| 411 |
|
|
.send_pmeack ( send_pmeack ),
|
| 412 |
|
|
.cs_is_pm ( cs_is_pm ),
|
| 413 |
|
|
.grant ( grant ),
|
| 414 |
|
|
.l0_pwr_turn_off_req ( l0_pwr_turn_off_req ),
|
| 415 |
|
|
.l0_pme_req_in ( l0_pme_req_in ),
|
| 416 |
|
|
.l0_pme_ack ( l0_pme_ack )
|
| 417 |
|
|
);
|
| 418 |
|
|
|
| 419 |
|
|
pcie_soft_cf_int interrupt_interface
|
| 420 |
|
|
(
|
| 421 |
|
|
// Clock & Reset
|
| 422 |
|
|
.clk ( clk ), // I
|
| 423 |
|
|
.rst_n ( rst_n ), // I
|
| 424 |
|
|
// Interface to Arbitor
|
| 425 |
|
|
.cs_is_intr ( cs_is_intr ),
|
| 426 |
|
|
.grant ( grant ),
|
| 427 |
|
|
.cfg_msguaddr ( cfg_msguaddr ),
|
| 428 |
|
|
// PCIe Block Interrupt Ports
|
| 429 |
|
|
.msi_enable ( msi_enable ), // I
|
| 430 |
|
|
.msi_request ( msi_request ), // O[3:0]
|
| 431 |
|
|
.legacy_int_request ( legacy_int_request ), // O
|
| 432 |
|
|
// LocalLink Interrupt Ports
|
| 433 |
|
|
.cfg_interrupt_n ( cfg_interrupt_n ), // I
|
| 434 |
|
|
.cfg_interrupt_rdy_n ( cfg_interrupt_rdy_n ), // O
|
| 435 |
|
|
|
| 436 |
|
|
.cfg_interrupt_assert_n(cfg_interrupt_assert_n), // I
|
| 437 |
|
|
.cfg_interrupt_di(cfg_interrupt_di), // I[7:0]
|
| 438 |
|
|
|
| 439 |
|
|
.cfg_interrupt_mmenable(cfg_interrupt_mmenable), // O[2:0]
|
| 440 |
|
|
.cfg_interrupt_do(cfg_interrupt_do), // O[7:0]
|
| 441 |
|
|
.cfg_interrupt_msienable(cfg_interrupt_msienable), // O
|
| 442 |
|
|
.intr_vector(intr_vector), // O[7:0]
|
| 443 |
|
|
.msi_8bit_en(msi_8bit_en), // I
|
| 444 |
|
|
.msi_laddr(cfg_msgladdr), // I[31:0]
|
| 445 |
|
|
.msi_haddr(cfg_msguaddr), // I[31:0]
|
| 446 |
|
|
|
| 447 |
|
|
.cfg_command(cfg_command),
|
| 448 |
|
|
.cfg_msgctrl(cfg_msgctrl),
|
| 449 |
|
|
.cfg_msgdata(cfg_msgdata),
|
| 450 |
|
|
|
| 451 |
|
|
.signaledint(signaledint),
|
| 452 |
|
|
.intr_req_valid(intr_req_valid),
|
| 453 |
|
|
.intr_req_type(intr_req_type)
|
| 454 |
|
|
|
| 455 |
|
|
|
| 456 |
|
|
);
|
| 457 |
|
|
|
| 458 |
|
|
endmodule // pcie_blk_cf
|
