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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [pcie_blk_cf_arb.v] - Blame information for rev 2

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2
//-----------------------------------------------------------------------------
3
//
4
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
5
//
6
// This file contains confidential and proprietary information
7
// of Xilinx, Inc. and is protected under U.S. and
8
// international copyright and other intellectual property
9
// laws.
10
//
11
// DISCLAIMER
12
// This disclaimer is not a license and does not grant any
13
// rights to the materials distributed herewith. Except as
14
// otherwise provided in a valid license issued to you by
15
// Xilinx, and to the maximum extent permitted by applicable
16
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
17
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
18
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
19
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
20
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
21
// (2) Xilinx shall not be liable (whether in contract or tort,
22
// including negligence, or under any other theory of
23
// liability) for any loss or damage of any kind or nature
24
// related to, arising under or in connection with these
25
// materials, including for any direct, or any indirect,
26
// special, incidental, or consequential loss or damage
27
// (including loss of data, profits, goodwill, or any type of
28
// loss or damage suffered as a result of any action brought
29
// by a third party) even if such damage or loss was
30
// reasonably foreseeable or Xilinx had been advised of the
31
// possibility of the same.
32
//
33
// CRITICAL APPLICATIONS
34
// Xilinx products are not designed or intended to be fail-
35
// safe, or for use in any application requiring fail-safe
36
// performance, such as life-support or safety devices or
37
// systems, Class III medical devices, nuclear facilities,
38
// applications related to the deployment of airbags, or any
39
// other applications that could lead to death, personal
40
// injury, or severe property or environmental damage
41
// (individually and collectively, "Critical
42
// Applications"). Customer assumes the sole risk and
43
// liability of any use of Xilinx products in Critical
44
// Applications, subject only to applicable laws and
45
// regulations governing limitations on product liability.
46
//
47
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
48
// PART OF THIS FILE AT ALL TIMES.
49
//
50
//-----------------------------------------------------------------------------
51
// Project    : V5-Block Plus for PCI Express
52
// File       : pcie_blk_cf_arb.v
53
//--------------------------------------------------------------------------------
54
//--------------------------------------------------------------------------------
55
//--
56
//-- Description: CFG Arbiter. This module will send messages as triggered
57
//--  by the err manager, power interface, or bar hit/miss logic. It sends
58
//--  the messages to the Tx arbiter.
59
//--
60
//--------------------------------------------------------------------------------
61
 
62
`timescale 1ns/1ns
63
 
64
`ifndef Tcq
65
  `define Tcq 1
66
`endif
67
 
68
module pcie_blk_cf_arb
69
(
70
       // PCIe Block clock and reset
71
 
72
       input wire         clk,
73
       input wire         rst_n,
74
 
75
       // Device,Bus,Func#
76
       input        [7:0] cfg_bus_number,
77
       input        [4:0] cfg_device_number,
78
       input        [2:0] cfg_function_number,
79
       input       [15:0] msi_data,
80
       input       [31:0] msi_laddr,
81
       input       [31:0] msi_haddr,
82
 
83
 
84
       // Interface to Error Manager
85
       input              send_cor,
86
       input              send_nfl,
87
       input              send_ftl,
88
       input              send_cplt,
89
       input              send_cplu,
90
       input       [49:0] cmt_rd_hdr,
91
       input       [49:0] cfg_rd_hdr,
92
       output reg  [49:0] request_data = 0,
93
       output reg         grant        = 0,
94
       output reg         cs_is_cplu   = 0,
95
       output reg         cs_is_cplt   = 0,
96
       output reg         cs_is_cor    = 0,
97
       output reg         cs_is_nfl    = 0,
98
       output reg         cs_is_ftl    = 0,
99
       output reg         cs_is_pm     = 0,
100
 
101
       // Interface from Power Manager
102
       input              send_pmeack,
103
       output reg         cs_is_intr   = 0,
104
 
105
       input        [7:0] intr_vector,
106
       input        [1:0] intr_req_type,
107
       input              intr_req_valid,
108
 
109
       // Output to Tx Block (via arbiter) to generate message/UR Completions
110
       output reg  [63:0] cfg_arb_td   = 0,
111
       output reg   [7:0] cfg_arb_trem_n = 1,
112
       output reg         cfg_arb_tsof_n = 1,
113
       output reg         cfg_arb_teof_n = 1,
114
       output reg         cfg_arb_tsrc_rdy_n = 1,
115
       input              cfg_arb_tdst_rdy_n
116
);
117
 
118
  reg     [3:0] cs_fsm;  // current state
119
  reg     [1:0] state;
120
parameter [3:0] st_reset       = 0,
121
                st_clear_count = 9,  // Added these three
122
                st_clear_send  = 10, // states 'cos counter takes 2 cycles to clear!
123
                st_cleared_all = 11, // and "send_***" signals are flopped; so 1 more-cycle is needed
124
                st_cplu_req    = 1,
125
                st_cplt_req    = 2,
126
                st_ftl_req     = 3,
127
                st_nfl_req     = 4,
128
                st_cor_req     = 5,
129
                st_send_pm     = 6,
130
                st_send_msi_32 = 7,
131
                st_send_msi_64 = 8,
132
                st_code_send_asrt = 12,
133
                st_code_send_d_asrt = 13;
134
 
135
 
136
parameter type_msg_intr = 5'b10100;
137
 
138
parameter           UR                                      = 1'b0;
139
parameter           CA                                      = 1'b1;
140
parameter           LOCK                                    = 1'b0;
141
parameter           rsvd_BYTE0                              = 1'b0;
142
parameter           fmt_mwr_3dwhdr_data                     = 2'b10;
143
parameter           fmt_mwr_4dwhdr_data                     = 2'b11;
144
parameter           fmt_msg                                 = 2'b01;        // Table 2-3
145
parameter           fmt_cpl                                 = 2'b00;        // Table 2-3
146
parameter           type_mwr                                = 5'b0_0000;
147
parameter           type_msg                                = 5'b1_0000;    // all msgs routed to root-complex (Table 2-11)
148
parameter           type_cpl                                = 5'b0_1010;    // all msgs routed to root-complex (Table 2-11)
149
parameter           type_cpllock                            = 5'b0_1011;
150
parameter           rsvd_msb_BYTE1                          = 1'b0;
151
parameter           tc_param                                = 3'b000;
152
parameter           rsvd_BYTE1                              = 4'b0000;
153
parameter           td                                      = 1'b0;
154
parameter           ep                                      = 1'b0;
155
parameter           attr_param                              = 2'b00;
156
parameter           rsvd_BYTE2                              = 2'b00;
157
parameter           len_98                                  = 2'b00;
158
parameter           len_70_BYTE3                            = 8'b0000_0000;
159
parameter           len_70_mwrd_BYTE3                       = 8'b0000_0001;
160
 
161
wire      [7:0]     completer_id_BYTE4                      = cfg_bus_number[7:0];
162
wire      [7:0]     completer_id_BYTE5                      = {cfg_device_number[4:0],cfg_function_number[2:0]};
163
parameter           compl_status_sc                         = 3'b000;
164
parameter           compl_status_ur                         = 3'b001;
165
parameter           compl_status_ca                         = 3'b100;
166
parameter           bcm                                     = 1'b0;
167
parameter           msg_code_err_cor_BYTE7                  = 8'b0011_0000;
168
parameter           msg_code_err_nfl_BYTE7                  = 8'b0011_0001;
169
parameter           msg_code_err_ftl_BYTE7                  = 8'b0011_0011;
170
parameter           rsvd_BYTE11                             = 1'b0;
171
parameter           msg_code_pm_pme_BYTE7                   = 8'b0001_1000;
172
parameter           msg_code_pme_to_ack_BYTE7               = 8'b0001_1011;
173
parameter           type_msg_pme_to_ack                     = 5'b1_0101;
174
parameter           last_dw_byte_enable_BYTE7               = 4'b0000;
175
parameter           first_dw_byte_enable_BYTE7              = 4'b1111;
176
 
177
parameter           msg_code_asrt_inta_BYTE7                = 8'b0010_0000;
178
parameter           msg_code_asrt_intb_BYTE7                = 8'b0010_0001;
179
parameter           msg_code_asrt_intc_BYTE7                = 8'b0010_0010;
180
parameter           msg_code_asrt_intd_BYTE7                = 8'b0010_0011;
181
parameter           msg_code_d_asrt_inta_BYTE7              = 8'b0010_0100;
182
parameter           msg_code_d_asrt_intb_BYTE7              = 8'b0010_0101;
183
parameter           msg_code_d_asrt_intc_BYTE7              = 8'b0010_0110;
184
parameter           msg_code_d_asrt_intd_BYTE7              = 8'b0010_0111;
185
 
186
wire     [31:0]     swizzle_msi_data                        = { intr_vector[7:0]    // Byte0
187
                                                               ,msi_data[15:8]   // Byte1
188
                                                               ,8'h0             // Byte2
189
                                                               ,8'h0             // Byte3
190
                                                               };
191
 
192
 
193
reg   [7:0] byte_00, byte_01, byte_02, byte_03,
194
            byte_04, byte_05, byte_06, byte_07,
195
            byte_08, byte_09, byte_10, byte_11;
196
 
197
reg  [31:0] bytes_12_to_15 = 0;
198
reg         reg_req_pkt_tx = 0;
199
reg   [1:0] wait_cntr      = 0;
200
 
201
 
202
  always @(posedge clk) begin
203
    if (~rst_n) begin
204
      cs_fsm            <= #`Tcq 4'b0000;
205
      request_data      <= #`Tcq 0;
206
      cs_is_cplu        <= #`Tcq 1'b0;
207
      cs_is_cplt        <= #`Tcq 1'b0;
208
      cs_is_cor         <= #`Tcq 1'b0;
209
      cs_is_nfl         <= #`Tcq 1'b0;
210
      cs_is_ftl         <= #`Tcq 1'b0;
211
      cs_is_pm          <= #`Tcq 1'b0;
212
      cs_is_intr        <= #`Tcq 1'b0;
213
      byte_00           <= #`Tcq 0;
214
      byte_01           <= #`Tcq 0;
215
      byte_02           <= #`Tcq 0;
216
      byte_03           <= #`Tcq 0;
217
      byte_04           <= #`Tcq 0;
218
      byte_05           <= #`Tcq 0;
219
      byte_06           <= #`Tcq 0;
220
      byte_07           <= #`Tcq 0;
221
      byte_08           <= #`Tcq 0;
222
      byte_09           <= #`Tcq 0;
223
      byte_10           <= #`Tcq 0;
224
      byte_11           <= #`Tcq 0;
225
      bytes_12_to_15    <= #`Tcq 0;
226
      reg_req_pkt_tx    <= #`Tcq 1'b0;
227
    end
228
    else begin
229
      case (cs_fsm) // synthesis full_case parallel_case
230
        st_reset: begin
231
            if (send_cplu)
232
              cs_fsm            <= #`Tcq st_cplu_req;
233
            else if (send_cplt)
234
              cs_fsm            <= #`Tcq st_cplt_req;
235
            else if (send_ftl)
236
              cs_fsm            <= #`Tcq st_ftl_req;
237
            else if (send_nfl)
238
              cs_fsm            <= #`Tcq st_nfl_req;
239
            else if (send_cor)
240
              cs_fsm            <= #`Tcq st_cor_req;
241
            else if (send_pmeack)
242
              cs_fsm            <= #`Tcq st_send_pm;
243
            else if (intr_req_valid)
244
            begin
245
               if (intr_req_type == 2'b00)
246
                  cs_fsm            <= #`Tcq st_code_send_asrt;
247
               else if (intr_req_type == 2'b01)
248
                  cs_fsm            <= #`Tcq st_code_send_d_asrt;
249
               else if (intr_req_type == 2'b10)
250
                  cs_fsm            <= #`Tcq st_send_msi_32;
251
               else if (intr_req_type == 2'b11)
252
                  cs_fsm            <= #`Tcq st_send_msi_64;
253
            end
254
            else
255
              cs_fsm            <= #`Tcq st_reset;
256
            request_data      <= #`Tcq 0;
257
            cs_is_cplu        <= #`Tcq 1'b0;
258
            cs_is_cplt        <= #`Tcq 1'b0;
259
            cs_is_cor         <= #`Tcq 1'b0;
260
            cs_is_nfl         <= #`Tcq 1'b0;
261
            cs_is_ftl         <= #`Tcq 1'b0;
262
            cs_is_pm          <= #`Tcq 1'b0;
263
            cs_is_intr        <= #`Tcq 1'b0;
264
            reg_req_pkt_tx    <= #`Tcq 1'b0;
265
        end
266
 
267
        st_cplu_req: begin
268
            if (grant)
269
              cs_fsm            <= #`Tcq st_clear_count;
270
            else
271
              cs_fsm            <= #`Tcq st_cplu_req;
272
            request_data      <= #`Tcq cfg_rd_hdr;
273
            cs_is_cplu        <= #`Tcq 1'b1;
274
            cs_is_cplt        <= #`Tcq 1'b0;
275
            cs_is_cor         <= #`Tcq 1'b0;
276
            cs_is_nfl         <= #`Tcq 1'b0;
277
            cs_is_ftl         <= #`Tcq 1'b0;
278
            cs_is_pm          <= #`Tcq 1'b0;
279
            cs_is_intr        <= #`Tcq 1'b0;
280
            ////
281
            if (cfg_rd_hdr[49] == LOCK) begin
282
              byte_00           <= #`Tcq {rsvd_BYTE0,fmt_cpl,type_cpllock};
283
            end else begin
284
              byte_00           <= #`Tcq {rsvd_BYTE0,fmt_cpl,type_cpl};
285
            end
286
            byte_03           <= #`Tcq {len_70_BYTE3};
287
            byte_04           <= #`Tcq {completer_id_BYTE4};
288
            byte_05           <= #`Tcq {completer_id_BYTE5};
289
            //byte_07           <= #`Tcq {byte_count_cpln_BYTE7};
290
            byte_07           <= #`Tcq {cfg_rd_hdr[36:29]};
291
            //byte_08           <= #`Tcq {msg_requester_id_BYTE4};
292
            byte_08           <= #`Tcq {cfg_rd_hdr[23:16]};
293
            //byte_09           <= #`Tcq {msg_requester_id_BYTE5};
294
            byte_09           <= #`Tcq {cfg_rd_hdr[15:8]};
295
            byte_10           <= #`Tcq cfg_rd_hdr[7:0];
296
            //byte_11           <= #`Tcq {rsvd_BYTE11,lower_address_cpln};
297
            byte_11           <= #`Tcq {rsvd_BYTE11,cfg_rd_hdr[47:41]};
298
            bytes_12_to_15    <= #`Tcq 0;
299
            reg_req_pkt_tx    <= #`Tcq 1'b1;
300
            if (cfg_rd_hdr[48] == UR) begin
301
              //byte_01           <= #`Tcq {rsvd_msb_BYTE1,tc_ur,rsvd_BYTE1};
302
              byte_01           <= #`Tcq {rsvd_msb_BYTE1,cfg_rd_hdr[28:26],rsvd_BYTE1};
303
              //byte_02           <= #`Tcq {td,ep,attr_ur,rsvd_BYTE2,len_98};
304
              byte_02           <= #`Tcq {td,ep,cfg_rd_hdr[25:24],rsvd_BYTE2,len_98};
305
              //byte_06           <= #`Tcq {compl_status_ur,bcm,byte_count_cpln_BYTE6}; 
306
              byte_06           <= #`Tcq {compl_status_ur,bcm,cfg_rd_hdr[40:37]};
307
            end else begin     // CA
308
              //byte_01           <= #`Tcq {rsvd_msb_BYTE1,tc_ur,rsvd_BYTE1};
309
              byte_01           <= #`Tcq {rsvd_msb_BYTE1,cfg_rd_hdr[28:26],rsvd_BYTE1};
310
              //byte_02           <= #`Tcq {td,ep,attr_ur,rsvd_BYTE2,len_98};
311
              byte_02           <= #`Tcq {td,ep,cfg_rd_hdr[25:24],rsvd_BYTE2,len_98};
312
              //byte_06           <= #`Tcq {compl_status_ca,bcm,byte_count_cpln_BYTE6}; 
313
              byte_06           <= #`Tcq {compl_status_ca,bcm,cfg_rd_hdr[40:37]};
314
            end
315
        end
316
        st_cplt_req: begin
317
            if (grant)
318
              cs_fsm            <= #`Tcq st_clear_count;
319
            else
320
              cs_fsm            <= #`Tcq st_cplt_req;
321
            request_data      <= #`Tcq cmt_rd_hdr;
322
            cs_is_cplt        <= #`Tcq 1'b1;
323
            cs_is_cplu        <= #`Tcq 1'b0;
324
            cs_is_cor         <= #`Tcq 1'b0;
325
            cs_is_nfl         <= #`Tcq 1'b0;
326
            cs_is_ftl         <= #`Tcq 1'b0;
327
            cs_is_pm          <= #`Tcq 1'b0;
328
            cs_is_intr        <= #`Tcq 1'b0;
329
            ////
330
            if (cmt_rd_hdr[49] == LOCK) begin
331
              byte_00           <= #`Tcq {rsvd_BYTE0,fmt_cpl,type_cpllock};
332
            end else begin
333
              byte_00           <= #`Tcq {rsvd_BYTE0,fmt_cpl,type_cpl};
334
            end
335
            byte_03           <= #`Tcq {len_70_BYTE3};
336
            byte_04           <= #`Tcq {completer_id_BYTE4};
337
            byte_05           <= #`Tcq {completer_id_BYTE5};
338
            byte_07           <= #`Tcq {cmt_rd_hdr[36:29]};
339
            byte_08           <= #`Tcq {cmt_rd_hdr[23:16]};
340
            byte_09           <= #`Tcq {cmt_rd_hdr[15:8]};
341
            byte_10           <= #`Tcq cmt_rd_hdr[7:0];
342
            byte_11           <= #`Tcq {rsvd_BYTE11,cmt_rd_hdr[47:41]};
343
            bytes_12_to_15    <= #`Tcq 0;
344
            reg_req_pkt_tx    <= #`Tcq 1'b1;
345
            if (cmt_rd_hdr[48] == UR) begin
346
              byte_01           <= #`Tcq {rsvd_msb_BYTE1,cmt_rd_hdr[28:26],rsvd_BYTE1};
347
              byte_02           <= #`Tcq {td,ep,cmt_rd_hdr[25:24],rsvd_BYTE2,len_98};
348
              byte_06           <= #`Tcq {compl_status_ur,bcm,cmt_rd_hdr[40:37]};
349
            end else begin     // CA
350
              byte_01           <= #`Tcq {rsvd_msb_BYTE1,cmt_rd_hdr[28:26],rsvd_BYTE1};
351
              byte_02           <= #`Tcq {td,ep,cmt_rd_hdr[25:24],rsvd_BYTE2,len_98};
352
              byte_06           <= #`Tcq {compl_status_ca,bcm,cmt_rd_hdr[40:37]};
353
            end
354
        end
355
        st_ftl_req:  begin
356
            if (grant)
357
              cs_fsm            <= #`Tcq st_clear_count;
358
            else
359
              cs_fsm            <= #`Tcq st_ftl_req;
360
            request_data      <= #`Tcq 0;
361
            cs_is_ftl         <= #`Tcq 1'b1;
362
            cs_is_cplu        <= #`Tcq 1'b0;
363
            cs_is_cplt        <= #`Tcq 1'b0;
364
            cs_is_cor         <= #`Tcq 1'b0;
365
            cs_is_nfl         <= #`Tcq 1'b0;
366
            cs_is_pm          <= #`Tcq 1'b0;
367
            cs_is_intr        <= #`Tcq 1'b0;
368
            ////
369
            byte_00           <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg};
370
            byte_01           <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
371
            byte_02           <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
372
            byte_03           <= #`Tcq {len_70_BYTE3};
373
            byte_04           <= #`Tcq {completer_id_BYTE4};
374
            byte_05           <= #`Tcq {completer_id_BYTE5};
375
            byte_06           <= #`Tcq 8'h0;
376
            byte_07           <= #`Tcq {msg_code_err_ftl_BYTE7};
377
            byte_08           <= #`Tcq 0;
378
            byte_09           <= #`Tcq 0;
379
            byte_10           <= #`Tcq 0;
380
            byte_11           <= #`Tcq 0;
381
            bytes_12_to_15    <= #`Tcq 0;
382
            reg_req_pkt_tx    <= #`Tcq 1'b1;
383
        end
384
        st_nfl_req:  begin
385
            if (grant)
386
              cs_fsm            <= #`Tcq st_clear_count;
387
            else
388
              cs_fsm            <= #`Tcq st_nfl_req;
389
            request_data      <= #`Tcq 0;
390
            cs_is_nfl         <= #`Tcq 1'b1;
391
            cs_is_cplu        <= #`Tcq 1'b0;
392
            cs_is_cplt        <= #`Tcq 1'b0;
393
            cs_is_cor         <= #`Tcq 1'b0;
394
            cs_is_ftl         <= #`Tcq 1'b0;
395
            cs_is_pm          <= #`Tcq 1'b0;
396
            cs_is_intr        <= #`Tcq 1'b0;
397
            ////
398
            byte_00           <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg};
399
            byte_01           <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
400
            byte_02           <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
401
            byte_03           <= #`Tcq {len_70_BYTE3};
402
            byte_04           <= #`Tcq {completer_id_BYTE4};
403
            byte_05           <= #`Tcq {completer_id_BYTE5};
404
            byte_06           <= #`Tcq 8'h0;
405
            byte_07           <= #`Tcq {msg_code_err_nfl_BYTE7};
406
            byte_08           <= #`Tcq 0;
407
            byte_09           <= #`Tcq 0;
408
            byte_10           <= #`Tcq 0;
409
            byte_11           <= #`Tcq 0;
410
            bytes_12_to_15    <= #`Tcq 0;
411
            reg_req_pkt_tx    <= #`Tcq 1'b1;
412
        end
413
        st_cor_req:  begin
414
            if (grant)
415
              cs_fsm            <= #`Tcq st_clear_count;
416
            else
417
              cs_fsm            <= #`Tcq st_cor_req;
418
            request_data      <= #`Tcq 0;
419
            cs_is_cor         <= #`Tcq 1'b1;
420
            cs_is_cplu        <= #`Tcq 1'b0;
421
            cs_is_cplt        <= #`Tcq 1'b0;
422
            cs_is_nfl         <= #`Tcq 1'b0;
423
            cs_is_ftl         <= #`Tcq 1'b0;
424
            cs_is_pm          <= #`Tcq 1'b0;
425
            cs_is_intr        <= #`Tcq 1'b0;
426
            ////
427
            byte_00           <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg};
428
            byte_01           <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
429
            byte_02           <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
430
            byte_03           <= #`Tcq {len_70_BYTE3};
431
            byte_04           <= #`Tcq {completer_id_BYTE4};
432
            byte_05           <= #`Tcq {completer_id_BYTE5};
433
            byte_06           <= #`Tcq 8'h0;
434
            byte_07           <= #`Tcq {msg_code_err_cor_BYTE7};
435
            byte_08           <= #`Tcq 0;
436
            byte_09           <= #`Tcq 0;
437
            byte_10           <= #`Tcq 0;
438
            byte_11           <= #`Tcq 0;
439
            bytes_12_to_15    <= #`Tcq 0;
440
            reg_req_pkt_tx    <= #`Tcq 1'b1;
441
        end
442
        st_send_pm: begin
443
            if (grant)
444
              cs_fsm            <= #`Tcq st_clear_count;
445
            else
446
              cs_fsm            <= #`Tcq st_send_pm;
447
            request_data      <= #`Tcq 0;
448
            cs_is_cor         <= #`Tcq 1'b0;
449
            cs_is_cplu        <= #`Tcq 1'b0;
450
            cs_is_cplt        <= #`Tcq 1'b0;
451
            cs_is_nfl         <= #`Tcq 1'b0;
452
            cs_is_ftl         <= #`Tcq 1'b0;
453
            cs_is_pm          <= #`Tcq 1'b1;
454
            cs_is_intr        <= #`Tcq 1'b0;
455
            ////
456
            byte_01           <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
457
            byte_02           <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
458
            byte_03           <= #`Tcq {len_70_BYTE3};
459
            byte_04           <= #`Tcq {completer_id_BYTE4};
460
            byte_05           <= #`Tcq {completer_id_BYTE5};
461
            byte_06           <= #`Tcq 8'h0;
462
            byte_08           <= #`Tcq 0;
463
            byte_09           <= #`Tcq 0;
464
            byte_10           <= #`Tcq 0;
465
            byte_11           <= #`Tcq 0;
466
            bytes_12_to_15    <= #`Tcq 0;
467
          //if (pme_ack_bar) begin
468
          //  byte_07           <= #`Tcq {msg_code_pm_pme_BYTE7};
469
          //  byte_00           <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg};
470
          //end
471
          //else begin
472
            byte_07           <= #`Tcq {msg_code_pme_to_ack_BYTE7};
473
            byte_00           <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg_pme_to_ack};
474
          //end
475
            reg_req_pkt_tx    <= #`Tcq 1'b1;
476
        end
477
 
478
 
479
        st_code_send_asrt: begin
480
            if (grant)
481
              cs_fsm            <= #`Tcq st_clear_count;
482
            else
483
              cs_fsm            <= #`Tcq st_code_send_asrt;
484
            request_data      <= #`Tcq 0;
485
            cs_is_cor         <= #`Tcq 1'b0;
486
            cs_is_cplu        <= #`Tcq 1'b0;
487
            cs_is_cplt        <= #`Tcq 1'b0;
488
            cs_is_nfl         <= #`Tcq 1'b0;
489
            cs_is_ftl         <= #`Tcq 1'b0;
490
            cs_is_pm          <= #`Tcq 1'b0;
491
            cs_is_intr        <= #`Tcq 1'b1;
492
            ////
493
            byte_00           <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg_intr};
494
            byte_01           <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
495
            byte_02           <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
496
            byte_03           <= #`Tcq {len_70_BYTE3};
497
            byte_04           <= #`Tcq {completer_id_BYTE4};
498
            byte_05           <= #`Tcq {completer_id_BYTE5};
499
            byte_06           <= #`Tcq 8'h0;
500
            byte_08           <= #`Tcq 0;
501
            byte_09           <= #`Tcq 0;
502
            byte_10           <= #`Tcq 0;
503
            byte_11           <= #`Tcq 0;
504
            bytes_12_to_15    <= #`Tcq 0;
505
            reg_req_pkt_tx    <= #`Tcq 1'b1;
506
          case (intr_vector[1:0])  // synthesis full_case parallel_case
507
            2'b00: byte_07          <= #`Tcq {msg_code_asrt_inta_BYTE7};
508
            2'b01: byte_07          <= #`Tcq {msg_code_asrt_intb_BYTE7};
509
            2'b10: byte_07          <= #`Tcq {msg_code_asrt_intc_BYTE7};
510
            2'b11: byte_07          <= #`Tcq {msg_code_asrt_intd_BYTE7};
511
          endcase
512
        end
513
 
514
        st_code_send_d_asrt: begin
515
            if (grant)
516
              cs_fsm            <= #`Tcq st_clear_count;
517
            else
518
              cs_fsm            <= #`Tcq st_code_send_d_asrt;
519
            request_data      <= #`Tcq 0;
520
            cs_is_cor         <= #`Tcq 1'b0;
521
            cs_is_cplu        <= #`Tcq 1'b0;
522
            cs_is_cplt        <= #`Tcq 1'b0;
523
            cs_is_nfl         <= #`Tcq 1'b0;
524
            cs_is_ftl         <= #`Tcq 1'b0;
525
            cs_is_pm          <= #`Tcq 1'b0;
526
            cs_is_intr        <= #`Tcq 1'b1;
527
            ////
528
            byte_00           <= #`Tcq {rsvd_BYTE0,fmt_msg,type_msg_intr};
529
            byte_01           <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
530
            byte_02           <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
531
            byte_03           <= #`Tcq {len_70_BYTE3};
532
            byte_04           <= #`Tcq {completer_id_BYTE4};
533
            byte_05           <= #`Tcq {completer_id_BYTE5};
534
            byte_06           <= #`Tcq 8'h0;
535
            byte_08           <= #`Tcq 0;
536
            byte_09           <= #`Tcq 0;
537
            byte_10           <= #`Tcq 0;
538
            byte_11           <= #`Tcq 0;
539
            bytes_12_to_15    <= #`Tcq 0;
540
            reg_req_pkt_tx    <= #`Tcq 1'b1;
541
          case (intr_vector[1:0])  // synthesis full_case parallel_case
542
            2'b00: byte_07          <= #`Tcq {msg_code_d_asrt_inta_BYTE7};
543
            2'b01: byte_07          <= #`Tcq {msg_code_d_asrt_intb_BYTE7};
544
            2'b10: byte_07          <= #`Tcq {msg_code_d_asrt_intc_BYTE7};
545
            2'b11: byte_07          <= #`Tcq {msg_code_d_asrt_intd_BYTE7};
546
          endcase
547
        end
548
 
549
        st_send_msi_32: begin
550
            if (grant)
551
              cs_fsm            <= #`Tcq st_clear_count;
552
            else
553
              cs_fsm            <= #`Tcq st_send_msi_32;
554
            request_data      <= #`Tcq 0;
555
            cs_is_cor         <= #`Tcq 1'b0;
556
            cs_is_cplu        <= #`Tcq 1'b0;
557
            cs_is_cplt        <= #`Tcq 1'b0;
558
            cs_is_nfl         <= #`Tcq 1'b0;
559
            cs_is_ftl         <= #`Tcq 1'b0;
560
            cs_is_pm          <= #`Tcq 1'b0;
561
            cs_is_intr        <= #`Tcq 1'b1;
562
            ////
563
            byte_00           <= #`Tcq {rsvd_BYTE0,fmt_mwr_3dwhdr_data,type_mwr};
564
            byte_01           <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
565
            byte_02           <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
566
            byte_03           <= #`Tcq {len_70_mwrd_BYTE3};
567
            byte_04           <= #`Tcq {completer_id_BYTE4};
568
            byte_05           <= #`Tcq {completer_id_BYTE5};
569
            byte_06           <= #`Tcq 8'h0;
570
            byte_07           <= #`Tcq {last_dw_byte_enable_BYTE7,first_dw_byte_enable_BYTE7};
571
            byte_08           <= #`Tcq msi_laddr[31:24];
572
            byte_09           <= #`Tcq msi_laddr[23:16];
573
            byte_10           <= #`Tcq msi_laddr[15:08];
574
            byte_11           <= #`Tcq {msi_laddr[07:02],2'b00};
575
            bytes_12_to_15    <= #`Tcq swizzle_msi_data;
576
            reg_req_pkt_tx    <= #`Tcq 1'b1;
577
        end
578
        st_send_msi_64: begin
579
            if (grant)
580
              cs_fsm            <= #`Tcq st_clear_count;
581
            else
582
              cs_fsm            <= #`Tcq st_send_msi_64;
583
            request_data      <= #`Tcq 0;
584
            cs_is_cor         <= #`Tcq 1'b0;
585
            cs_is_cplu        <= #`Tcq 1'b0;
586
            cs_is_cplt        <= #`Tcq 1'b0;
587
            cs_is_nfl         <= #`Tcq 1'b0;
588
            cs_is_ftl         <= #`Tcq 1'b0;
589
            cs_is_pm          <= #`Tcq 1'b0;
590
            cs_is_intr        <= #`Tcq 1'b1;
591
            ////
592
            byte_00           <= #`Tcq {rsvd_BYTE0,fmt_mwr_4dwhdr_data,type_mwr};
593
            byte_01           <= #`Tcq {rsvd_msb_BYTE1,tc_param,rsvd_BYTE1};
594
            byte_02           <= #`Tcq {td,ep,attr_param,rsvd_BYTE2,len_98};
595
            byte_03           <= #`Tcq {len_70_mwrd_BYTE3};
596
            byte_04           <= #`Tcq {completer_id_BYTE4};
597
            byte_05           <= #`Tcq {completer_id_BYTE5};
598
            byte_06           <= #`Tcq 8'h0;
599
            byte_07           <= #`Tcq {last_dw_byte_enable_BYTE7,first_dw_byte_enable_BYTE7};
600
            byte_08           <= #`Tcq msi_haddr[31:24];
601
            byte_09           <= #`Tcq msi_haddr[23:16];
602
            byte_10           <= #`Tcq msi_haddr[15:08];
603
            byte_11           <= #`Tcq msi_haddr[07:00];
604
            bytes_12_to_15    <= #`Tcq {msi_laddr[31:2],2'b00};
605
            reg_req_pkt_tx    <= #`Tcq 1'b1;
606
        end
607
        st_clear_count: begin
608
            cs_fsm            <= #`Tcq st_clear_send;
609
            request_data      <= #`Tcq 0;
610
            cs_is_cplu        <= #`Tcq 1'b0;
611
            cs_is_cplt        <= #`Tcq 1'b0;
612
            cs_is_cor         <= #`Tcq 1'b0;
613
            cs_is_nfl         <= #`Tcq 1'b0;
614
            cs_is_ftl         <= #`Tcq 1'b0;
615
            cs_is_pm          <= #`Tcq 1'b0;
616
            cs_is_intr        <= #`Tcq 1'b0;
617
            reg_req_pkt_tx    <= #`Tcq 1'b0;
618
        end
619
        st_clear_send: begin
620
            cs_fsm            <= #`Tcq st_cleared_all;
621
            request_data      <= #`Tcq 0;
622
            cs_is_cplu        <= #`Tcq 1'b0;
623
            cs_is_cplt        <= #`Tcq 1'b0;
624
            cs_is_cor         <= #`Tcq 1'b0;
625
            cs_is_nfl         <= #`Tcq 1'b0;
626
            cs_is_ftl         <= #`Tcq 1'b0;
627
            cs_is_pm          <= #`Tcq 1'b0;
628
            cs_is_intr        <= #`Tcq 1'b0;
629
            reg_req_pkt_tx    <= #`Tcq 1'b0;
630
        end
631
        st_cleared_all: begin
632
            cs_fsm            <= #`Tcq st_reset;
633
            request_data      <= #`Tcq 0;
634
            cs_is_cplu        <= #`Tcq 1'b0;
635
            cs_is_cplt        <= #`Tcq 1'b0;
636
            cs_is_cor         <= #`Tcq 1'b0;
637
            cs_is_nfl         <= #`Tcq 1'b0;
638
            cs_is_ftl         <= #`Tcq 1'b0;
639
            cs_is_pm          <= #`Tcq 1'b0;
640
            cs_is_intr        <= #`Tcq 1'b0;
641
            reg_req_pkt_tx    <= #`Tcq 1'b0;
642
        end
643
        default: begin
644
            cs_fsm            <= #`Tcq st_reset;
645
            request_data      <= #`Tcq 0;
646
            cs_is_cplu        <= #`Tcq 1'b0;
647
            cs_is_cplt        <= #`Tcq 1'b0;
648
            cs_is_cor         <= #`Tcq 1'b0;
649
            cs_is_nfl         <= #`Tcq 1'b0;
650
            cs_is_ftl         <= #`Tcq 1'b0;
651
            cs_is_pm          <= #`Tcq 1'b0;
652
            cs_is_intr        <= #`Tcq 1'b0;
653
            reg_req_pkt_tx    <= #`Tcq 1'b0;
654
        end
655
      endcase
656
    end
657
  end
658
 
659
 
660
  wire [159:0] tlp_data= {swizzle_msi_data,
661
                          bytes_12_to_15,
662
                          byte_08,byte_09,byte_10,byte_11,
663
                          byte_04,byte_05,byte_06,byte_07,
664
                          byte_00,byte_01,byte_02,byte_03};
665
 
666
  wire pkt_3dw = (tlp_data[30:29]==2'b00);  // fmt type is pkt_3dw tlp 
667
  wire pkt_5dw = (tlp_data[30:29]==2'b11);  // fmt type is pkt_5dw tlp 
668
 
669
  parameter TX_IDLE     = 2'b00;
670
  parameter TX_DW1      = 2'b01;
671
  parameter TX_DW3      = 2'b10;
672
  parameter SEND_GRANT  = 2'b11;
673
 
674
 
675
  always @(posedge clk)
676
  begin
677
     if (~rst_n) begin
678
        cfg_arb_tsof_n  <= #`Tcq 1;
679
        cfg_arb_teof_n  <= #`Tcq 1;
680
        cfg_arb_td      <= #`Tcq 64'h0000_0000;
681
        cfg_arb_trem_n  <= #`Tcq 8'hff;
682
        cfg_arb_tsrc_rdy_n <= #`Tcq 1;
683
        grant           <= #`Tcq 0;
684
        state           <= #`Tcq TX_IDLE;
685
     end
686
     else
687
     case (state) //synthesis full_case parallel_case  
688
        TX_IDLE : begin
689
                     grant             <= #`Tcq 0;
690
                     cfg_arb_td[31:0]  <= #`Tcq tlp_data[63:32];
691
                     cfg_arb_td[63:32] <= #`Tcq tlp_data[31:0];
692
                     cfg_arb_teof_n    <= #`Tcq 1;
693
                     cfg_arb_trem_n    <= #`Tcq 8'h00;
694
                     if (reg_req_pkt_tx && (~|wait_cntr)) begin
695
                        cfg_arb_tsrc_rdy_n   <= #`Tcq 0;
696
                        cfg_arb_tsof_n    <= #`Tcq 0;
697
                     end
698
                     else begin
699
                        cfg_arb_tsrc_rdy_n   <= #`Tcq 1;
700
                        cfg_arb_tsof_n    <= #`Tcq 1;
701
                     end
702
                     if (reg_req_pkt_tx && (~|wait_cntr)) begin
703
                        state        <= #`Tcq TX_DW1;
704
                     end
705
                  end
706
        TX_DW1  : begin
707
                     cfg_arb_tsrc_rdy_n <= #`Tcq 0;
708
                     cfg_arb_trem_n     <= #`Tcq pkt_3dw ? 8'h0f : 8'h00 ;
709
                     if (!cfg_arb_tdst_rdy_n) begin
710
                        cfg_arb_td[31:0]  <= #`Tcq tlp_data[127:96];
711
                        cfg_arb_td[63:32] <= #`Tcq tlp_data[95:64];
712
                        cfg_arb_tsof_n    <= #`Tcq 1;
713
                        cfg_arb_teof_n    <= #`Tcq pkt_5dw;
714
                        state             <= #`Tcq pkt_5dw ? TX_DW3 : SEND_GRANT;
715
                        grant             <= #`Tcq 0;
716
                     end
717
                     else begin
718
                        cfg_arb_td[31:0]  <= #`Tcq tlp_data[63:32];
719
                        cfg_arb_td[63:32] <= #`Tcq tlp_data[31:0];
720
                        cfg_arb_tsof_n    <= #`Tcq 0;
721
                        cfg_arb_teof_n    <= #`Tcq 1;
722
                        state             <= #`Tcq TX_DW1;
723
                        grant             <= #`Tcq 0;
724
                     end
725
                  end
726
        TX_DW3  : begin
727
                     cfg_arb_tsrc_rdy_n <= #`Tcq 0;
728
                     cfg_arb_trem_n     <= #`Tcq 8'h0f;
729
                     if (!cfg_arb_tdst_rdy_n) begin
730
                        cfg_arb_td[31:0]  <= #`Tcq 32'h0;
731
                        cfg_arb_td[63:32] <= #`Tcq tlp_data[159:128];
732
                        cfg_arb_tsof_n    <= #`Tcq 1;
733
                        cfg_arb_teof_n    <= #`Tcq 0;
734
                        state             <= #`Tcq SEND_GRANT;
735
                        grant             <= #`Tcq 0;
736
                     end
737
                     else begin
738
                        cfg_arb_td[31:0]  <= #`Tcq tlp_data[127:96];
739
                        cfg_arb_td[63:32] <= #`Tcq tlp_data[95:64];
740
                        cfg_arb_tsof_n    <= #`Tcq 1;
741
                        cfg_arb_teof_n    <= #`Tcq 1;
742
                        state             <= #`Tcq TX_DW3;
743
                        grant             <= #`Tcq 0;
744
                     end
745
                  end
746
    SEND_GRANT  : begin
747
                     if (!cfg_arb_tdst_rdy_n) begin
748
                        cfg_arb_tsrc_rdy_n<= #`Tcq 1;
749
                        cfg_arb_tsof_n    <= #`Tcq 1;
750
                        cfg_arb_teof_n    <= #`Tcq 1;
751
                        state             <= #`Tcq TX_IDLE;
752
                        grant             <= #`Tcq 1;
753
                     end
754
                     else begin
755
                        cfg_arb_tsrc_rdy_n<= #`Tcq 0;
756
                        cfg_arb_tsof_n    <= #`Tcq 1;
757
                        cfg_arb_teof_n    <= #`Tcq 0;
758
                        state             <= #`Tcq SEND_GRANT;
759
                        grant             <= #`Tcq 0;
760
                     end
761
                  end
762
     endcase
763
  end
764
 
765
  always @(posedge clk)
766
  begin
767
     if (~rst_n) begin
768
       wait_cntr <= #`Tcq 0;
769
     end else if (state == SEND_GRANT) begin
770
       wait_cntr <= #`Tcq 2'b10;
771
     end else if (|wait_cntr) begin
772
       wait_cntr <= #`Tcq wait_cntr - 1;
773
     end
774
  end
775
 
776
endmodule // pcie_blk_cf_arb

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