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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : pcie_blk_cf_err.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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//--
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//-- Description: Error Manager. This module will generate error messages to be
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//-- sent by the Tx block, and it will set appropriate error bits in register
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//-- space.
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//--
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//--------------------------------------------------------------------------------
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`ifndef Tcq
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`define Tcq 1
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`endif
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`timescale 1ns/1ns
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module pcie_blk_cf_err
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(
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// PCIe Block clock and reset
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input wire clk,
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input wire rst_n,
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// PCIe Soft Macro Cfg Interface
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input cfg_err_cor_n,
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input cfg_err_ur_n,
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input cfg_err_ecrc_n,
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input cfg_err_cpl_timeout_n,
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input cfg_err_cpl_abort_n,
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input cfg_err_cpl_unexpect_n,
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input cfg_err_posted_n,
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input cfg_err_locked_n,
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input [47:0] cfg_err_tlp_cpl_header,
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output cfg_err_cpl_rdy_n,
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// Rx/Tx indicates Poisoned TLP
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input rx_err_cpl_ep_n, //Rx Completion
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input tx_err_wr_ep_n, //Tx Write
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input rx_err_ep_n, //Any
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input rx_err_tlp_poisoned_n,
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// Rx indicates Competion Abort
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input rx_err_cpl_abort_n,
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// Rx indicates Unsupported Request
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input rx_err_cpl_ur_n,
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input rx_err_tlp_ur_n, //Bar miss, format problem
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input rx_err_tlp_ur_lock_n, //UR due to Lock
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input rx_err_tlp_p_cpl_n,
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// Rx indicates Malformed packet
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input rx_err_tlp_malformed_n,
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// Header info from Rx
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input [47:0] rx_err_tlp_hdr,
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// Output to Tx Block (via arbiter) to generate message/UR Completions
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output reg send_cor = 0,
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output reg send_nfl = 0,
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output reg send_ftl = 0,
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output reg send_cplt = 0,
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output reg send_cplu = 0,
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output wire [49:0] cmt_rd_hdr,
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output wire [49:0] cfg_rd_hdr,
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input wire [49:0] request_data,
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input grant,
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input cs_is_cplu,
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input cs_is_cplt,
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input cs_is_cor,
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input cs_is_nfl,
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input cs_is_ftl,
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// Input from the PCIe Block
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input [6:0] l0_dll_error_vector,
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input [1:0] l0_rx_mac_link_error,
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input l0_mac_link_up,
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// Output to PCIe Block, to set
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output wire l0_set_unsupported_request_other_error,
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output wire l0_set_detected_fatal_error,
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output wire l0_set_detected_nonfatal_error,
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output wire l0_set_detected_corr_error,
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output wire l0_set_user_system_error,
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output wire l0_set_user_master_data_parity,
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output wire l0_set_user_signaled_target_abort,
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output wire l0_set_user_received_target_abort,
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output wire l0_set_user_received_master_abort,
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output wire l0_set_user_detected_parity_error,
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// Inputs fromthe Shadow Registers
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input [15:0] cfg_dcommand,
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input [15:0] cfg_command,
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// Inputs from the PCIe Block
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input serr_en
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);
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parameter UR = 1'b0,
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CA = 1'b1;
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wire decr_cplu;
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wire decr_cplt;
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wire decr_cor;
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wire decr_nfl;
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wire decr_ftl;
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wire tlp_posted;
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wire cfg_posted;
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wire tlp_is_np_and_ur;
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wire cfg_is_np_and_ur;
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wire cfg_is_np_and_cpl_abort, cfg_is_p_and_cpl_abort, cfg_is_p_and_cpl_abort_and_send_nfl;
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wire masterdataparityerror;
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wire signaledtargetabort;
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wire receivedtargetabort;
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wire receivedmasterabort;
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wire detectedparityerror;
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wire signaledsystemerror;
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wire unsupportedreq;
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wire detectedfatal;
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wire detectednonfatal;
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wire detectedcorrectable;
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wire [3:0] cnt_cplt;
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wire [3:0] cnt_cplu;
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wire [3:0] cnt_ftl;
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wire [3:0] cnt_nfl;
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wire [3:0] cnt_cor;
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wire [49:0] cmt_wr_hdr;
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wire [49:0] cfg_wr_hdr;
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wire incr_cplu, incr_cplt;
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reg [49:0] reg_cmt_wr_hdr;
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reg [49:0] reg_cfg_wr_hdr;
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reg [3:0] cs_fsm; // current state
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reg [1:0] reg_cmt_wp, reg_cmt_rp;
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reg [2:0] reg_cfg_wp, reg_cfg_rp;
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reg reg_masterdataparityerror;
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reg reg_signaledtargetabort;
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reg reg_receivedtargetabort;
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reg reg_receivedmasterabort;
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reg reg_detectedparityerror;
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reg reg_signaledsystemerror;
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reg reg_detectedcorrectable;
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reg reg_detectedfatal;
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reg reg_detectednonfatal;
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reg reg_unsupportedreq;
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reg reg_incr_cplu, reg_incr_cplt;
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wire [2:0] cor_num_int;
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wire [2:0] cor_num;
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wire [2:0] ftl_num;
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wire [2:0] nfl_num_int;
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wire [2:0] nfl_num;
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wire [2:0] cplt_num;
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wire [2:0] cplu_num;
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wire [1:0] cmt_wp;
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wire [1:0] cmt_rp;
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wire [2:0] cfg_wp;
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wire [2:0] cfg_rp;
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wire reg_decr_nfl;
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wire reg_decr_cor;
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//******************************************************************//
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// Decode the error report masking capabilities and error severity. //
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//******************************************************************//
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wire serr_en_cmd = cfg_command[8];
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wire [3:0] x_dcmd = cfg_dcommand[3:0];
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wire err_cor_en = x_dcmd[0];
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wire err_nfl_en = x_dcmd[1] | serr_en_cmd;
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wire err_ftl_en = x_dcmd[2] | serr_en_cmd;
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wire err_ur_en = x_dcmd[3];
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wire err_ur_nfl_en = x_dcmd[3] & x_dcmd[1];
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//******************************************************************//
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// ??? Need to drive these signals when errors are detected. ??? //
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// There is no clear instruction in the PCI Express Base Spec, //
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// Rev. 1.0 how the PCI Express errors are mapped to PCI errors, //
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// all the following PCI error reporting signals are tied to logic //
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// zero until further clarify by the PCI SIG. (7/2/02) //
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//******************************************************************//
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always @(posedge clk) begin
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if (~rst_n)
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reg_signaledsystemerror <= #`Tcq 1'b0;
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else if (serr_en_cmd & grant)
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// If NFL message is sent 'cos of a NP UR.
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if ((request_data[48] == UR) && (cs_is_cplu || cs_is_cplt) && grant && err_ur_en)
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reg_signaledsystemerror <= #`Tcq 1'b1;
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// If NFL message is sent 'cos of a P UR
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else if (cs_is_cplu)
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reg_signaledsystemerror <= #`Tcq 1'b1;
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// If NFL | FTL message is sent 'cos of ERROR Non-Fatal | Fatal
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else if (cs_is_nfl|cs_is_ftl)
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reg_signaledsystemerror <= #`Tcq 1'b1;
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else
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reg_signaledsystemerror <= #`Tcq 1'b0;
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else
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reg_signaledsystemerror <= #`Tcq 1'b0;
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end
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wire parity_err_resp = cfg_command[6];
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always @(posedge clk) begin
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if (~rst_n) begin
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reg_masterdataparityerror <= #`Tcq 1'b0;
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reg_signaledtargetabort <= #`Tcq 1'b0;
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reg_receivedtargetabort <= #`Tcq 1'b0;
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reg_receivedmasterabort <= #`Tcq 1'b0;
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reg_detectedparityerror <= #`Tcq 1'b0;
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reg_detectedcorrectable <= #`Tcq 1'b0;
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reg_detectedfatal <= #`Tcq 1'b0;
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reg_detectednonfatal <= #`Tcq 1'b0;
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reg_unsupportedreq <= #`Tcq 1'b0;
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end
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else begin
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// This bit is set by Requestor if the Parity Error Enable
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// bit is set and either of the following two conditions occurs:
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// --> Requestor receives completion marked poisoned
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// --> Requestor poisons a write Request
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284 |
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// If the Parity Error Enable bit is cleared, this bit is never set.
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285 |
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// Default value of this field is 0.
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reg_masterdataparityerror <= #`Tcq parity_err_resp ? (~rx_err_cpl_ep_n | ~tx_err_wr_ep_n) : 1'b0;
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288 |
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// This bit is set when the device completes a Request using completer Abort completion Status
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// Default value of this field is 0.
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290 |
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reg_signaledtargetabort <= #`Tcq cfg_is_np_and_cpl_abort;
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291 |
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292 |
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// This bit is set when a Requestor receives a Completion with completer Abort completion Status
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293 |
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// Default value of this field is 0.
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294 |
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reg_receivedtargetabort <= #`Tcq ~rx_err_cpl_abort_n;
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295 |
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296 |
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// This bit is set when a Requestor receives a completion with Unsupported Request completion status
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297 |
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// Default value of this field is 0.
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298 |
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reg_receivedmasterabort <= #`Tcq ~rx_err_cpl_ur_n;
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299 |
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300 |
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// This bit is set by a device whenever it receives a Poisoned TLP, regardless of the state of
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301 |
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// the Parity Error Enable bit.
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302 |
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// Default value of this field is 0.
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303 |
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reg_detectedparityerror <= #`Tcq ~rx_err_ep_n;
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304 |
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305 |
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306 |
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// Refer Sec 6.2.6 Error Listing Rules for this classification
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307 |
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reg_detectedcorrectable <= #`Tcq ~cfg_err_cor_n;
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308 |
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309 |
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reg_detectedfatal <= #`Tcq ~rx_err_tlp_malformed_n;
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310 |
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311 |
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//Modified to NFL, other than UR or Posted Completer Abort
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reg_detectednonfatal <= #`Tcq ~cfg_err_ecrc_n | // Not a AFE, User detects a ECRC error for a TLP
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~cfg_err_cpl_timeout_n; // Not a ANFE, User detects that Cpln has not arrived
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314 |
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reg_unsupportedreq <= #`Tcq (~rx_err_tlp_ur_n & ~rx_err_tlp_p_cpl_n) |
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316 |
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(~cfg_err_ur_n & ~cfg_err_posted_n) ; // Not a ANFE, User detects a UR for a posted TLP
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317 |
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// so send a NFL message and record the UR in the
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318 |
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// status here.
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319 |
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end
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320 |
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end
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321 |
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322 |
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323 |
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// Instantiate the error count-up/count-down modules
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324 |
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// Correctible error handling: parse, count, send_request through a priorotised arbiter
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325 |
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cmm_errman_cor wtd_cor (
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326 |
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.cor_num (cor_num_int)
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327 |
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,.inc_dec_b (cor_add_sub_b)
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328 |
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,.reg_decr_cor (reg_decr_cor)
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329 |
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,.add_input_one (1'b0) //l0_rx_mac_link_error[1] & l0_mac_link_up)
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330 |
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,.add_input_two_n (1'b1) //~l0_dll_error_vector[2])
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331 |
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|
,.add_input_three_n (1'b1) //~l0_dll_error_vector[3])
|
332 |
|
|
,.add_input_four_n (1'b1) //~l0_dll_error_vector[1])
|
333 |
|
|
,.add_input_five_n (1'b1) //~l0_dll_error_vector[0])
|
334 |
|
|
,.add_input_six_n (1'b1) ////cfg_err_cor_n)
|
335 |
|
|
,.decr_cor (decr_cor)
|
336 |
|
|
,.rst (~rst_n)
|
337 |
|
|
,.clk (clk)
|
338 |
|
|
);
|
339 |
|
|
|
340 |
|
|
assign cor_num = cor_num_int - reg_decr_cor;
|
341 |
|
|
|
342 |
|
|
cmm_errman_cnt_en cor_cntr (
|
343 |
|
|
.count (cnt_cor)
|
344 |
|
|
,.index (cor_num)
|
345 |
|
|
,.inc_dec_b (cor_add_sub_b)
|
346 |
|
|
,.enable (err_cor_en)
|
347 |
|
|
,.rst (~rst_n)
|
348 |
|
|
,.clk (clk)
|
349 |
|
|
);
|
350 |
|
|
|
351 |
|
|
|
352 |
|
|
|
353 |
|
|
// Non-Fatal error handling: parse, count, send_request through a priorotised arbiter
|
354 |
|
|
cmm_errman_cor wtd_nfl (
|
355 |
|
|
.cor_num (nfl_num_int)
|
356 |
|
|
,.inc_dec_b (nfl_add_sub_b)
|
357 |
|
|
,.reg_decr_cor (reg_decr_nfl)
|
358 |
|
|
// Posted TLP that causes a UR, the NFL message is sent if
|
359 |
|
|
// the UR&NFL are enabled together, or if the SERR is enabled.
|
360 |
|
|
// Ref: Fig6-2, PCIe Base Spec v1.1
|
361 |
|
|
,.add_input_one (1'b0)////~rx_err_tlp_ur_n & ~rx_err_tlp_p_cpl_n & (err_ur_nfl_en | serr_en) )
|
362 |
|
|
,.add_input_two_n (1'b1)////err_nfl_en ? cfg_err_cpl_timeout_n : 1'b1)
|
363 |
|
|
,.add_input_three_n (err_nfl_en ? rx_err_tlp_poisoned_n : 1'b1)
|
364 |
|
|
,.add_input_four_n (1'b1)////err_nfl_en ? cfg_err_ecrc_n : 1'b1)
|
365 |
|
|
,.add_input_five_n (1'b1)////~(~cfg_err_ur_n & ~cfg_err_posted_n & (err_ur_nfl_en|serr_en)))
|
366 |
|
|
,.add_input_six_n (1'b1)
|
367 |
|
|
,.decr_cor (decr_nfl)
|
368 |
|
|
,.rst (~rst_n)
|
369 |
|
|
,.clk (clk)
|
370 |
|
|
);
|
371 |
|
|
|
372 |
|
|
assign nfl_num = nfl_num_int - reg_decr_nfl;
|
373 |
|
|
|
374 |
|
|
cmm_errman_cnt_en nfl_cntr (
|
375 |
|
|
.count (cnt_nfl)
|
376 |
|
|
,.index (nfl_num)
|
377 |
|
|
,.inc_dec_b (nfl_add_sub_b)
|
378 |
|
|
,.enable (1'b1)
|
379 |
|
|
,.rst (~rst_n)
|
380 |
|
|
,.clk (clk)
|
381 |
|
|
);
|
382 |
|
|
|
383 |
|
|
// Fatal error handling: parse, count, send_request through a priorotised arbiter
|
384 |
|
|
cmm_errman_ftl wtd_ftl (
|
385 |
|
|
.ftl_num (ftl_num)
|
386 |
|
|
,.inc_dec_b (ftl_add_sub_b)
|
387 |
|
|
,.cmmp_training_err (1'b0)
|
388 |
|
|
,.cmml_protocol_err_n (1'b1) //~l0_dll_error_vector[6])
|
389 |
|
|
,.cmmt_err_rbuf_overflow (1'b0)
|
390 |
|
|
,.cmmt_err_fc (1'b0)
|
391 |
|
|
,.cmmt_err_tlp_malformed (1'b0)
|
392 |
|
|
,.decr_ftl (decr_ftl)
|
393 |
|
|
,.rst (~rst_n)
|
394 |
|
|
,.clk (clk)
|
395 |
|
|
);
|
396 |
|
|
|
397 |
|
|
cmm_errman_cnt_en ftl_cntr (
|
398 |
|
|
.count (cnt_ftl)
|
399 |
|
|
,.index (ftl_num)
|
400 |
|
|
,.inc_dec_b (ftl_add_sub_b)
|
401 |
|
|
,.enable (err_ftl_en)
|
402 |
|
|
,.rst (~rst_n)
|
403 |
|
|
,.clk (clk)
|
404 |
|
|
);
|
405 |
|
|
|
406 |
|
|
|
407 |
|
|
|
408 |
|
|
// Completion-Abort/Unsupported-Request TLM error handling: parse, count, send_request through a priorotised arbiter
|
409 |
|
|
cmm_errman_cpl wtd_cplt (
|
410 |
|
|
.cpl_num (cplt_num)
|
411 |
|
|
,.inc_dec_b (cplt_add_sub_b)
|
412 |
|
|
,.cmm_err_tlp_posted (tlp_posted)
|
413 |
|
|
,.decr_cpl (decr_cplt)
|
414 |
|
|
,.rst (~rst_n)
|
415 |
|
|
,.clk (clk)
|
416 |
|
|
);
|
417 |
|
|
|
418 |
|
|
cmm_errman_cnt_en cplt_cntr ( // one counter for TLM
|
419 |
|
|
.count (cnt_cplt)
|
420 |
|
|
,.index (cplt_num)
|
421 |
|
|
,.inc_dec_b (cplt_add_sub_b)
|
422 |
|
|
,.enable (1'b1) // always enable Cpl response
|
423 |
|
|
,.rst (~rst_n)
|
424 |
|
|
,.clk (clk)
|
425 |
|
|
);
|
426 |
|
|
|
427 |
|
|
|
428 |
|
|
// Completion-Abort/Unsupported-Request USER error handling: parse, count, send_request through a priorotised arbiter
|
429 |
|
|
cmm_errman_cpl wtd_cplu (
|
430 |
|
|
.cpl_num (cplu_num)
|
431 |
|
|
,.inc_dec_b (cplu_add_sub_b)
|
432 |
|
|
,.cmm_err_tlp_posted (cfg_posted)
|
433 |
|
|
,.decr_cpl (decr_cplu)
|
434 |
|
|
,.rst (~rst_n)
|
435 |
|
|
,.clk (clk)
|
436 |
|
|
);
|
437 |
|
|
|
438 |
|
|
cmm_errman_cnt_en cplu_cntr ( // one counter for User
|
439 |
|
|
.count (cnt_cplu)
|
440 |
|
|
,.index (cplu_num)
|
441 |
|
|
,.inc_dec_b (cplu_add_sub_b)
|
442 |
|
|
,.enable (1'b1) // always enable Cpl response
|
443 |
|
|
,.rst (~rst_n)
|
444 |
|
|
,.clk (clk)
|
445 |
|
|
);
|
446 |
|
|
|
447 |
|
|
|
448 |
|
|
|
449 |
|
|
always @(posedge clk) begin
|
450 |
|
|
if (~rst_n) begin
|
451 |
|
|
send_cor <= #`Tcq 1'b0;
|
452 |
|
|
send_nfl <= #`Tcq 1'b0;
|
453 |
|
|
send_ftl <= #`Tcq 1'b0;
|
454 |
|
|
send_cplt <= #`Tcq 1'b0;
|
455 |
|
|
send_cplu <= #`Tcq 1'b0;
|
456 |
|
|
end
|
457 |
|
|
else begin
|
458 |
|
|
send_cor <= #`Tcq |cnt_cor;
|
459 |
|
|
send_nfl <= #`Tcq |cnt_nfl;
|
460 |
|
|
send_ftl <= #`Tcq |cnt_ftl;
|
461 |
|
|
send_cplt <= #`Tcq |cnt_cplt;
|
462 |
|
|
send_cplu <= #`Tcq |cnt_cplu;
|
463 |
|
|
end
|
464 |
|
|
end
|
465 |
|
|
|
466 |
|
|
|
467 |
|
|
|
468 |
|
|
// Store the header information into FIFO
|
469 |
|
|
always @(posedge clk) begin
|
470 |
|
|
if (~rst_n)
|
471 |
|
|
reg_cmt_wr_hdr <= #`Tcq 50'h0000_0000_0000;
|
472 |
|
|
else begin
|
473 |
|
|
// If UR
|
474 |
|
|
if (tlp_is_np_and_ur)
|
475 |
|
|
reg_cmt_wr_hdr <= #`Tcq {rx_err_tlp_ur_lock_n,UR, // Locked status, UR
|
476 |
|
|
rx_err_tlp_hdr[47:0]}; // Lower-Addr + Byte-Count + TC + Attr + Req-ID + Tag
|
477 |
|
|
else
|
478 |
|
|
reg_cmt_wr_hdr <= #`Tcq 0;
|
479 |
|
|
end
|
480 |
|
|
end
|
481 |
|
|
|
482 |
|
|
|
483 |
|
|
// Store the header information into FIFO
|
484 |
|
|
always @(posedge clk) begin
|
485 |
|
|
if (~rst_n)
|
486 |
|
|
reg_cfg_wr_hdr <= #`Tcq 50'h0000_0000_0000;
|
487 |
|
|
else begin
|
488 |
|
|
if (cfg_is_np_and_ur)
|
489 |
|
|
reg_cfg_wr_hdr <= #`Tcq {cfg_err_locked_n, UR, // Locked status, UR
|
490 |
|
|
cfg_err_tlp_cpl_header[47:0]}; // Lower-Addr + Byte-Count + TC + Attr + Req-ID + Tag
|
491 |
|
|
else if (cfg_is_np_and_cpl_abort)
|
492 |
|
|
reg_cfg_wr_hdr <= #`Tcq {cfg_err_locked_n, CA, // Locked status, CA
|
493 |
|
|
cfg_err_tlp_cpl_header[47:0]}; // Lower-Addr + Byte-Count + TC + Attr + Req-ID + Tag
|
494 |
|
|
else
|
495 |
|
|
reg_cfg_wr_hdr <= #`Tcq 0;
|
496 |
|
|
end
|
497 |
|
|
end
|
498 |
|
|
|
499 |
|
|
assign cmt_wr_hdr = reg_cmt_wr_hdr;
|
500 |
|
|
assign cfg_wr_hdr = reg_cfg_wr_hdr;
|
501 |
|
|
|
502 |
|
|
|
503 |
|
|
|
504 |
|
|
|
505 |
|
|
|
506 |
|
|
// Pipeline the completion request signals
|
507 |
|
|
always @(posedge clk)
|
508 |
|
|
if (~rst_n) begin
|
509 |
|
|
reg_incr_cplu <= #`Tcq 1'b0;
|
510 |
|
|
reg_incr_cplt <= #`Tcq 1'b0;
|
511 |
|
|
end
|
512 |
|
|
else begin
|
513 |
|
|
reg_incr_cplu <= #`Tcq cfg_posted;
|
514 |
|
|
reg_incr_cplt <= #`Tcq tlp_posted;
|
515 |
|
|
end
|
516 |
|
|
|
517 |
|
|
|
518 |
|
|
assign incr_cplu = reg_incr_cplu;
|
519 |
|
|
assign incr_cplt = reg_incr_cplt;
|
520 |
|
|
|
521 |
|
|
always @(posedge clk) begin
|
522 |
|
|
if (~rst_n) reg_cmt_wp <= #`Tcq 2'b00;
|
523 |
|
|
else if (incr_cplt) reg_cmt_wp <= #`Tcq cmt_wp + 2'b01;
|
524 |
|
|
end
|
525 |
|
|
|
526 |
|
|
always @(posedge clk) begin
|
527 |
|
|
if (~rst_n) reg_cfg_wp <= #`Tcq 3'b000;
|
528 |
|
|
else if (incr_cplu) reg_cfg_wp <= #`Tcq cfg_wp + 3'b001;
|
529 |
|
|
end
|
530 |
|
|
|
531 |
|
|
|
532 |
|
|
always @(posedge clk) begin
|
533 |
|
|
if (~rst_n) reg_cmt_rp <= #`Tcq 2'b00;
|
534 |
|
|
else if (cs_is_cplt & grant) reg_cmt_rp <= #`Tcq cmt_rp + 2'b01;
|
535 |
|
|
end
|
536 |
|
|
|
537 |
|
|
always @(posedge clk) begin
|
538 |
|
|
if (~rst_n) reg_cfg_rp <= #`Tcq 3'b000;
|
539 |
|
|
else if (cs_is_cplu & grant) reg_cfg_rp <= #`Tcq cfg_rp + 3'b001;
|
540 |
|
|
end
|
541 |
|
|
|
542 |
|
|
assign cmt_wp = reg_cmt_wp;
|
543 |
|
|
assign cfg_wp = reg_cfg_wp;
|
544 |
|
|
assign cmt_rp = reg_cmt_rp;
|
545 |
|
|
assign cfg_rp = reg_cfg_rp;
|
546 |
|
|
|
547 |
|
|
//******************************************************************//
|
548 |
|
|
// Instantiate two 4-deep, 50-bit wide buffers to store the header //
|
549 |
|
|
// information of the outstanding completion packets. One buffer //
|
550 |
|
|
// for the requests from the TLM (cmmt_* ports) and one for the //
|
551 |
|
|
// requests from the user (cfg_* ports). //
|
552 |
|
|
// The buffer is implemented with RAM16X1D primitives and the //
|
553 |
|
|
// read data output is registered. //
|
554 |
|
|
// The write and read pointers to the header buffer are separately //
|
555 |
|
|
// advanced by the FSM. Pointer wraps around if overflow. Both the //
|
556 |
|
|
// write and read pointers are not managed (e.g. if there are 16 //
|
557 |
|
|
// writes before a read occur, header information is lost). //
|
558 |
|
|
//******************************************************************//
|
559 |
|
|
|
560 |
|
|
// Header buffer for completion from TLM (TRN I/F) & USR (CFG I/F)
|
561 |
|
|
cmm_errman_ram4x26 cmt_hdr_buf (
|
562 |
|
|
.rddata (cmt_rd_hdr)
|
563 |
|
|
,.wrdata (cmt_wr_hdr)
|
564 |
|
|
,.wr_ptr (cmt_wp)
|
565 |
|
|
,.rd_ptr (cmt_rp)
|
566 |
|
|
,.we (incr_cplt)
|
567 |
|
|
,.rst (~rst_n)
|
568 |
|
|
,.clk (clk)
|
569 |
|
|
);
|
570 |
|
|
|
571 |
|
|
cmm_errman_ram8x26 cfg_hdr_buf (
|
572 |
|
|
.rddata (cfg_rd_hdr)
|
573 |
|
|
,.wrdata (cfg_wr_hdr)
|
574 |
|
|
,.wr_ptr (cfg_wp)
|
575 |
|
|
,.rd_ptr (cfg_rp)
|
576 |
|
|
,.we (incr_cplu)
|
577 |
|
|
,.rst (~rst_n)
|
578 |
|
|
,.clk (clk)
|
579 |
|
|
);
|
580 |
|
|
|
581 |
|
|
assign decr_cplu = cs_is_cplu && grant;
|
582 |
|
|
assign decr_cplt = cs_is_cplt && grant;
|
583 |
|
|
assign decr_cor = cs_is_cor && grant;
|
584 |
|
|
assign decr_nfl = cs_is_nfl && grant;
|
585 |
|
|
assign decr_ftl = cs_is_ftl && grant;
|
586 |
|
|
|
587 |
|
|
//assign tlp_is_np_and_ur = cmmt_err_tlp_ur & cmmt_err_tlp_p_cpl_n;
|
588 |
|
|
assign tlp_is_np_and_ur = ~rx_err_tlp_ur_n & rx_err_tlp_p_cpl_n;
|
589 |
|
|
// For a Non-Posted TLP that causes a UR, we should report a UR
|
590 |
|
|
assign tlp_posted = tlp_is_np_and_ur ? 1'b1 : 1'b0;
|
591 |
|
|
|
592 |
|
|
assign cfg_is_np_and_ur = ~cfg_err_ur_n & cfg_err_posted_n;
|
593 |
|
|
assign cfg_is_np_and_cpl_abort = ~cfg_err_cpl_abort_n & cfg_err_posted_n;
|
594 |
|
|
|
595 |
|
|
// cfg_posted has a 3 cycle delay from when cfg_err_ur_n or
|
596 |
|
|
// cfg_err_cpl_abort_n is asserted. Set throttle at 4, so fifo needs space
|
597 |
|
|
// for 3+3. Only 1 cpl can be added to fifo at a time.
|
598 |
|
|
|
599 |
|
|
assign cfg_posted = ((cfg_is_np_and_ur|cfg_is_np_and_cpl_abort) & ~cnt_cplu[2]) ? 1'b1 : 1'b0;
|
600 |
|
|
|
601 |
|
|
assign cfg_err_cpl_rdy_n = (cnt_cplu[2] | ~rst_n);
|
602 |
|
|
|
603 |
|
|
|
604 |
|
|
assign l0_set_user_master_data_parity = reg_masterdataparityerror;
|
605 |
|
|
assign l0_set_user_signaled_target_abort = reg_signaledtargetabort;
|
606 |
|
|
assign l0_set_user_received_target_abort = reg_receivedtargetabort;
|
607 |
|
|
assign l0_set_user_received_master_abort = reg_receivedmasterabort;
|
608 |
|
|
assign l0_set_user_detected_parity_error = reg_detectedparityerror;
|
609 |
|
|
|
610 |
|
|
assign l0_set_user_system_error = reg_signaledsystemerror;
|
611 |
|
|
|
612 |
|
|
assign l0_set_unsupported_request_other_error = reg_unsupportedreq;
|
613 |
|
|
assign l0_set_detected_fatal_error = reg_detectedfatal;
|
614 |
|
|
assign l0_set_detected_nonfatal_error = reg_detectednonfatal;
|
615 |
|
|
assign l0_set_detected_corr_error = reg_detectedcorrectable;
|
616 |
|
|
|
617 |
|
|
endmodule // pcie_blk_cf_err
|