1 |
2 |
dsmv |
|
2 |
|
|
//-----------------------------------------------------------------------------
|
3 |
|
|
//
|
4 |
|
|
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
|
5 |
|
|
//
|
6 |
|
|
// This file contains confidential and proprietary information
|
7 |
|
|
// of Xilinx, Inc. and is protected under U.S. and
|
8 |
|
|
// international copyright and other intellectual property
|
9 |
|
|
// laws.
|
10 |
|
|
//
|
11 |
|
|
// DISCLAIMER
|
12 |
|
|
// This disclaimer is not a license and does not grant any
|
13 |
|
|
// rights to the materials distributed herewith. Except as
|
14 |
|
|
// otherwise provided in a valid license issued to you by
|
15 |
|
|
// Xilinx, and to the maximum extent permitted by applicable
|
16 |
|
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
17 |
|
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
18 |
|
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
19 |
|
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
20 |
|
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
21 |
|
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
22 |
|
|
// including negligence, or under any other theory of
|
23 |
|
|
// liability) for any loss or damage of any kind or nature
|
24 |
|
|
// related to, arising under or in connection with these
|
25 |
|
|
// materials, including for any direct, or any indirect,
|
26 |
|
|
// special, incidental, or consequential loss or damage
|
27 |
|
|
// (including loss of data, profits, goodwill, or any type of
|
28 |
|
|
// loss or damage suffered as a result of any action brought
|
29 |
|
|
// by a third party) even if such damage or loss was
|
30 |
|
|
// reasonably foreseeable or Xilinx had been advised of the
|
31 |
|
|
// possibility of the same.
|
32 |
|
|
//
|
33 |
|
|
// CRITICAL APPLICATIONS
|
34 |
|
|
// Xilinx products are not designed or intended to be fail-
|
35 |
|
|
// safe, or for use in any application requiring fail-safe
|
36 |
|
|
// performance, such as life-support or safety devices or
|
37 |
|
|
// systems, Class III medical devices, nuclear facilities,
|
38 |
|
|
// applications related to the deployment of airbags, or any
|
39 |
|
|
// other applications that could lead to death, personal
|
40 |
|
|
// injury, or severe property or environmental damage
|
41 |
|
|
// (individually and collectively, "Critical
|
42 |
|
|
// Applications"). Customer assumes the sole risk and
|
43 |
|
|
// liability of any use of Xilinx products in Critical
|
44 |
|
|
// Applications, subject only to applicable laws and
|
45 |
|
|
// regulations governing limitations on product liability.
|
46 |
|
|
//
|
47 |
|
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
48 |
|
|
// PART OF THIS FILE AT ALL TIMES.
|
49 |
|
|
//
|
50 |
|
|
//-----------------------------------------------------------------------------
|
51 |
|
|
// Project : V5-Block Plus for PCI Express
|
52 |
|
|
// File : pcie_blk_cf_mgmt.v
|
53 |
|
|
//--------------------------------------------------------------------------------
|
54 |
|
|
//--------------------------------------------------------------------------------
|
55 |
|
|
//--
|
56 |
|
|
//-- Description: Management Interface. This module will poll the
|
57 |
|
|
//-- configuration registers to store in shadow registers, and it will also
|
58 |
|
|
//-- arbitrate for access to the management interface with the user.
|
59 |
|
|
//--
|
60 |
|
|
//--------------------------------------------------------------------------------
|
61 |
|
|
|
62 |
|
|
`timescale 1ns/1ns
|
63 |
|
|
|
64 |
|
|
`ifndef Tcq
|
65 |
|
|
`define Tcq 1
|
66 |
|
|
`endif
|
67 |
|
|
|
68 |
|
|
`define INSTANTIATE_LUTROM 1
|
69 |
|
|
|
70 |
|
|
module pcie_blk_cf_mgmt
|
71 |
|
|
(
|
72 |
|
|
// PCIe Block clock and reset
|
73 |
|
|
|
74 |
|
|
input wire clk,
|
75 |
|
|
input wire rst_n,
|
76 |
|
|
|
77 |
|
|
// PCIe CFG signals
|
78 |
|
|
input wire [12:0] completer_id,
|
79 |
|
|
|
80 |
|
|
// PCIe Block Management Interface
|
81 |
|
|
|
82 |
|
|
output reg [10:0] mgmt_addr = 11'h047,
|
83 |
|
|
output reg mgmt_wren = 0,
|
84 |
|
|
output reg mgmt_rden = 0,
|
85 |
|
|
output reg [31:0] mgmt_wdata = 0,
|
86 |
|
|
output reg [3:0] mgmt_bwren = 4'hF,
|
87 |
|
|
input wire [31:0] mgmt_rdata,
|
88 |
|
|
input wire [16:0] mgmt_pso,
|
89 |
|
|
|
90 |
|
|
// PCIe Soft Macro Cfg Interface
|
91 |
|
|
|
92 |
|
|
input wire [63:0] cfg_dsn,
|
93 |
|
|
output reg [31:0] cfg_do = 0,
|
94 |
|
|
output reg cfg_rd_wr_done_n = 1,
|
95 |
|
|
input wire [11:0] cfg_dwaddr,
|
96 |
|
|
input wire cfg_rd_en_n,
|
97 |
|
|
output reg [31:0] cfg_rx_bar0 = 0,
|
98 |
|
|
output reg [31:0] cfg_rx_bar1 = 0,
|
99 |
|
|
output reg [31:0] cfg_rx_bar2 = 0,
|
100 |
|
|
output reg [31:0] cfg_rx_bar3 = 0,
|
101 |
|
|
output reg [31:0] cfg_rx_bar4 = 0,
|
102 |
|
|
output reg [31:0] cfg_rx_bar5 = 0,
|
103 |
|
|
output reg [31:0] cfg_rx_xrom = 0,
|
104 |
|
|
output reg [15:0] cfg_status = 0,
|
105 |
|
|
output reg [15:0] cfg_command = 0,
|
106 |
|
|
output reg [15:0] cfg_dstatus = 0,
|
107 |
|
|
output reg [15:0] cfg_dcommand = 0,
|
108 |
|
|
output reg [15:0] cfg_lstatus = 0,
|
109 |
|
|
output reg [15:0] cfg_lcommand = 0,
|
110 |
|
|
output reg [31:0] cfg_pmcsr = 0,
|
111 |
|
|
output reg [31:0] cfg_dcap = 0,
|
112 |
|
|
output reg [15:0] cfg_msgctrl = 0,
|
113 |
|
|
output reg [31:0] cfg_msgladdr = 0,
|
114 |
|
|
output reg [31:0] cfg_msguaddr = 0,
|
115 |
|
|
output reg [15:0] cfg_msgdata = 0,
|
116 |
|
|
output wire [7:0] cfg_bus_number,
|
117 |
|
|
output wire [4:0] cfg_device_number,
|
118 |
|
|
output wire [2:0] cfg_function_number,
|
119 |
|
|
|
120 |
|
|
//// These signals go to mgmt block to implement a workaround
|
121 |
|
|
input wire [63:0] llk_rx_data_d,
|
122 |
|
|
input wire llk_rx_src_rdy_n,
|
123 |
|
|
input wire [6:0] l0_dll_error_vector,
|
124 |
|
|
input wire [1:0] l0_rx_mac_link_error,
|
125 |
|
|
input wire l0_stats_cfg_received,
|
126 |
|
|
input wire l0_stats_cfg_transmitted,
|
127 |
|
|
input wire l0_set_unsupported_request_other_error,
|
128 |
|
|
input wire l0_set_detected_corr_error
|
129 |
|
|
);
|
130 |
|
|
|
131 |
|
|
|
132 |
|
|
(* ram_style = "distributed" *)
|
133 |
|
|
reg [6:0] poll_dwaddr_rom [0:31];
|
134 |
|
|
reg [31:0] poll_dwrw_rom;
|
135 |
|
|
reg [4:0] poll_dwaddr_cntr = 0;
|
136 |
|
|
reg [4:0] poll_dwaddr_cntr_d1 = 0;
|
137 |
|
|
reg [4:0] poll_dwaddr_cntr_d2 = 0;
|
138 |
|
|
reg poll_en = 0;
|
139 |
|
|
reg poll_data_en_d = 0;
|
140 |
|
|
reg wait_stg1 = 0;
|
141 |
|
|
reg wait_stg2 = 0;
|
142 |
|
|
//reg poll_rd_wr_done_n = 1;
|
143 |
|
|
reg [31:0] mgmt_rdata_d1 = 0;
|
144 |
|
|
reg cfg_data_en_d = 0;
|
145 |
|
|
reg cfg_rd_en_n_d = 0;
|
146 |
|
|
reg lock_useraccess = 0;
|
147 |
|
|
wire poll_data_en;
|
148 |
|
|
reg [6:0] cfg_dwaddr_rom [0:31];
|
149 |
|
|
reg [3:0] zero_out_byte = 0;
|
150 |
|
|
reg shift_word = 0;
|
151 |
|
|
|
152 |
|
|
// define fixed Unsupported Request Error detected register bit in fabric
|
153 |
|
|
reg fabric_ur_error_detected = 0;
|
154 |
|
|
// define fixed Correctable Error detected register bit in fabric
|
155 |
|
|
reg fabric_co_error_detected = 0;
|
156 |
|
|
wire fabric_ur_error_detect;
|
157 |
|
|
wire fabric_co_error_detect;
|
158 |
|
|
reg detected_h68read = 0;
|
159 |
|
|
reg detected_h68read_d = 0;
|
160 |
|
|
wire detected_h68read2cycle;
|
161 |
|
|
wire falseur_cfg_access_wr;
|
162 |
|
|
reg falseur_cfg_access_wr_reg = 0;
|
163 |
|
|
reg [3:0] packet_read_cntr = 0;
|
164 |
|
|
reg packet_read_occurred = 0;
|
165 |
|
|
reg mgmt_pso_co_d = 0;
|
166 |
|
|
reg mgmt_pso_ur_d = 0;
|
167 |
|
|
reg mgmt_pso_co_fell_d = 0;
|
168 |
|
|
reg mgmt_pso_ur_fell_d = 0;
|
169 |
|
|
reg [3:0] l0_dll_error_vector_d = 0;
|
170 |
|
|
reg [1:0] l0_rx_mac_link_error_d = 0;
|
171 |
|
|
reg l0_set_detected_corr_error_d = 0;
|
172 |
|
|
|
173 |
|
|
reg detected_h48read = 0;
|
174 |
|
|
reg detected_h48read_d = 0;
|
175 |
|
|
reg detected_cfg_read1cycle = 0;
|
176 |
|
|
wire detected_h48read2cycle;
|
177 |
|
|
wire msi_ctrl_cfg_access_wr;
|
178 |
|
|
reg msi_ctrl_cfg_access_wr_reg = 0;
|
179 |
|
|
|
180 |
|
|
assign cfg_bus_number = completer_id[12:5];
|
181 |
|
|
assign cfg_device_number = completer_id[4:0];
|
182 |
|
|
assign cfg_function_number = 3'b000;
|
183 |
|
|
|
184 |
|
|
`ifndef INSTANTIATE_LUTROM
|
185 |
|
|
// A ROM to store the sequence of addresses to poll
|
186 |
|
|
initial begin
|
187 |
|
|
poll_dwaddr_rom[0] = 7'h47;
|
188 |
|
|
poll_dwaddr_rom[1] = 7'h48;
|
189 |
|
|
poll_dwaddr_rom[2] = 7'h01; //CSR
|
190 |
|
|
poll_dwaddr_rom[3] = 7'h04; //BAR0
|
191 |
|
|
poll_dwaddr_rom[4] = 7'h05; //BAR1
|
192 |
|
|
poll_dwaddr_rom[5] = 7'h06; //BAR2
|
193 |
|
|
poll_dwaddr_rom[6] = 7'h07; //BAR3
|
194 |
|
|
poll_dwaddr_rom[7] = 7'h08; //BAR4
|
195 |
|
|
poll_dwaddr_rom[8] = 7'h09; //BAR5
|
196 |
|
|
poll_dwaddr_rom[9] = 7'h0c; //XROM
|
197 |
|
|
poll_dwaddr_rom[10] = 7'h2a; //Dstat,Dctrl
|
198 |
|
|
poll_dwaddr_rom[11] = 7'h2c; //Lstat,Lctrl
|
199 |
|
|
poll_dwaddr_rom[12] = 7'h1e; //PMCSR
|
200 |
|
|
poll_dwaddr_rom[13] = 7'h29; //Dcap
|
201 |
|
|
poll_dwaddr_rom[14] = 7'h47; //DSN high (write)
|
202 |
|
|
poll_dwaddr_rom[15] = 7'h48; //DSN low (write)
|
203 |
|
|
////
|
204 |
|
|
poll_dwaddr_rom[16] = 7'h22; //MSI Control
|
205 |
|
|
poll_dwaddr_rom[17] = 7'h23; //MSI Lower Address
|
206 |
|
|
poll_dwaddr_rom[18] = 7'h24; //MSI Upper Address
|
207 |
|
|
poll_dwaddr_rom[19] = 7'h25; //MSI Data
|
208 |
|
|
poll_dwaddr_rom[20] = 7'h00; //
|
209 |
|
|
poll_dwaddr_rom[21] = 7'h00; //
|
210 |
|
|
poll_dwaddr_rom[22] = 7'h00; //
|
211 |
|
|
poll_dwaddr_rom[23] = 7'h00; //
|
212 |
|
|
poll_dwaddr_rom[24] = 7'h00; //
|
213 |
|
|
poll_dwaddr_rom[25] = 7'h00; //
|
214 |
|
|
poll_dwaddr_rom[26] = 7'h00; //
|
215 |
|
|
poll_dwaddr_rom[27] = 7'h00; //
|
216 |
|
|
poll_dwaddr_rom[28] = 7'h00; //
|
217 |
|
|
poll_dwaddr_rom[29] = 7'h00; //
|
218 |
|
|
poll_dwaddr_rom[30] = 7'h00; //
|
219 |
|
|
poll_dwaddr_rom[31] = 7'h00; //
|
220 |
|
|
end
|
221 |
|
|
|
222 |
|
|
// A ROM to store the sequence of read or write ops
|
223 |
|
|
initial begin
|
224 |
|
|
poll_dwrw_rom[0] = 1'b0;
|
225 |
|
|
poll_dwrw_rom[1] = 1'b0;
|
226 |
|
|
poll_dwrw_rom[2] = 1'b0;
|
227 |
|
|
poll_dwrw_rom[3] = 1'b0;
|
228 |
|
|
poll_dwrw_rom[4] = 1'b0;
|
229 |
|
|
poll_dwrw_rom[5] = 1'b0;
|
230 |
|
|
poll_dwrw_rom[6] = 1'b0;
|
231 |
|
|
poll_dwrw_rom[7] = 1'b0;
|
232 |
|
|
poll_dwrw_rom[8] = 1'b0;
|
233 |
|
|
poll_dwrw_rom[9] = 1'b0;
|
234 |
|
|
poll_dwrw_rom[10] = 1'b0;
|
235 |
|
|
poll_dwrw_rom[11] = 1'b0;
|
236 |
|
|
poll_dwrw_rom[12] = 1'b0;
|
237 |
|
|
poll_dwrw_rom[13] = 1'b0;
|
238 |
|
|
poll_dwrw_rom[14] = 1'b1;
|
239 |
|
|
poll_dwrw_rom[15] = 1'b1;
|
240 |
|
|
////
|
241 |
|
|
poll_dwrw_rom[16] = 1'b0;
|
242 |
|
|
poll_dwrw_rom[17] = 1'b0;
|
243 |
|
|
poll_dwrw_rom[18] = 1'b0;
|
244 |
|
|
poll_dwrw_rom[19] = 1'b0;
|
245 |
|
|
poll_dwrw_rom[20] = 1'b0;
|
246 |
|
|
poll_dwrw_rom[21] = 1'b0;
|
247 |
|
|
poll_dwrw_rom[22] = 1'b0;
|
248 |
|
|
poll_dwrw_rom[23] = 1'b0;
|
249 |
|
|
poll_dwrw_rom[24] = 1'b0;
|
250 |
|
|
poll_dwrw_rom[25] = 1'b0;
|
251 |
|
|
poll_dwrw_rom[26] = 1'b0;
|
252 |
|
|
poll_dwrw_rom[27] = 1'b0;
|
253 |
|
|
poll_dwrw_rom[28] = 1'b0;
|
254 |
|
|
poll_dwrw_rom[29] = 1'b0;
|
255 |
|
|
poll_dwrw_rom[30] = 1'b0;
|
256 |
|
|
poll_dwrw_rom[31] = 1'b0;
|
257 |
|
|
end
|
258 |
|
|
|
259 |
|
|
wire [10:0] poll_dwaddr = {4'b0,poll_dwaddr_rom[poll_dwaddr_cntr]};
|
260 |
|
|
wire poll_dwrw = poll_dwrw_rom[poll_dwaddr_cntr];
|
261 |
|
|
|
262 |
|
|
`else
|
263 |
|
|
|
264 |
|
|
wire [6:0] poll_dwaddrx;
|
265 |
|
|
wire poll_dwrw;
|
266 |
|
|
|
267 |
|
|
//// DWADDR LUT ROM ////
|
268 |
|
|
// fedc ba98 7654 3210 fedc ba98 7654 3210
|
269 |
|
|
LUT5 #(.INIT(32'b0000_0000_0000_0000__1100_0000_0000_0011)) lut_dwaddr_rom6( .O (poll_dwaddrx[6]), .I0(poll_dwaddr_cntr[0]), .I1(poll_dwaddr_cntr[1]), .I2(poll_dwaddr_cntr[2]), .I3(poll_dwaddr_cntr[3]), .I4(poll_dwaddr_cntr[4]));
|
270 |
|
|
LUT5 #(.INIT(32'b0000_0000_0000_1111__0010_1100_0000_0000)) lut_dwaddr_rom5( .O (poll_dwaddrx[5]), .I0(poll_dwaddr_cntr[0]), .I1(poll_dwaddr_cntr[1]), .I2(poll_dwaddr_cntr[2]), .I3(poll_dwaddr_cntr[3]), .I4(poll_dwaddr_cntr[4]));
|
271 |
|
|
LUT5 #(.INIT(32'b0000_0000_0000_0000__0001_0000_0000_0000)) lut_dwaddr_rom4( .O (poll_dwaddrx[4]), .I0(poll_dwaddr_cntr[0]), .I1(poll_dwaddr_cntr[1]), .I2(poll_dwaddr_cntr[2]), .I3(poll_dwaddr_cntr[3]), .I4(poll_dwaddr_cntr[4]));
|
272 |
|
|
LUT5 #(.INIT(32'b0000_0000_0000_0000__1011_1111_1000_0010)) lut_dwaddr_rom3( .O (poll_dwaddrx[3]), .I0(poll_dwaddr_cntr[0]), .I1(poll_dwaddr_cntr[1]), .I2(poll_dwaddr_cntr[2]), .I3(poll_dwaddr_cntr[3]), .I4(poll_dwaddr_cntr[4]));
|
273 |
|
|
LUT5 #(.INIT(32'b0000_0000_0000_1100__0101_1010_0111_1001)) lut_dwaddr_rom2( .O (poll_dwaddrx[2]), .I0(poll_dwaddr_cntr[0]), .I1(poll_dwaddr_cntr[1]), .I2(poll_dwaddr_cntr[2]), .I3(poll_dwaddr_cntr[3]), .I4(poll_dwaddr_cntr[4]));
|
274 |
|
|
LUT5 #(.INIT(32'b0000_0000_0000_0011__0101_0100_0110_0001)) lut_dwaddr_rom1( .O (poll_dwaddrx[1]), .I0(poll_dwaddr_cntr[0]), .I1(poll_dwaddr_cntr[1]), .I2(poll_dwaddr_cntr[2]), .I3(poll_dwaddr_cntr[3]), .I4(poll_dwaddr_cntr[4]));
|
275 |
|
|
LUT5 #(.INIT(32'b0000_0000_0000_1010__0110_0001_0101_0101)) lut_dwaddr_rom0( .O (poll_dwaddrx[0]), .I0(poll_dwaddr_cntr[0]), .I1(poll_dwaddr_cntr[1]), .I2(poll_dwaddr_cntr[2]), .I3(poll_dwaddr_cntr[3]), .I4(poll_dwaddr_cntr[4]));
|
276 |
|
|
|
277 |
|
|
wire [10:0] poll_dwaddr = {4'b0,poll_dwaddrx};
|
278 |
|
|
|
279 |
|
|
//// DWRW LUT ROM ////
|
280 |
|
|
// fedc ba98 7654 3210 fedc ba98 7654 3210
|
281 |
|
|
LUT5 #(.INIT(32'b0000_0000_0000_0000__1100_0000_0000_0000)) lut_dwrw_rom( .O (poll_dwrw), .I0(poll_dwaddr_cntr[0]), .I1(poll_dwaddr_cntr[1]), .I2(poll_dwaddr_cntr[2]), .I3(poll_dwaddr_cntr[3]), .I4(poll_dwaddr_cntr[4]));
|
282 |
|
|
|
283 |
|
|
|
284 |
|
|
`endif
|
285 |
|
|
|
286 |
|
|
|
287 |
|
|
wire cfg_dwaddr_remap = (cfg_dwaddr[6:5] == 2'b10);
|
288 |
|
|
wire [4:0] cfg_dwaddr_int = (cfg_dwaddr[4:0] ^ {5{cfg_dwaddr_remap}});
|
289 |
|
|
|
290 |
|
|
`ifndef INSTANTIATE_LUTROM
|
291 |
|
|
initial begin
|
292 |
|
|
cfg_dwaddr_rom[0] = 7'h00; //00
|
293 |
|
|
cfg_dwaddr_rom[1] = 7'h01; //04
|
294 |
|
|
cfg_dwaddr_rom[2] = 7'h02; //08
|
295 |
|
|
cfg_dwaddr_rom[3] = 7'h03; //0C
|
296 |
|
|
//
|
297 |
|
|
cfg_dwaddr_rom[4] = 7'h04; //10
|
298 |
|
|
cfg_dwaddr_rom[5] = 7'h05; //14
|
299 |
|
|
cfg_dwaddr_rom[6] = 7'h06; //18
|
300 |
|
|
cfg_dwaddr_rom[7] = 7'h07; //1C
|
301 |
|
|
//
|
302 |
|
|
cfg_dwaddr_rom[8] = 7'h08; //20
|
303 |
|
|
cfg_dwaddr_rom[9] = 7'h09; //24
|
304 |
|
|
cfg_dwaddr_rom[10] = 7'h0a; //28
|
305 |
|
|
cfg_dwaddr_rom[11] = 7'h0b; //2C
|
306 |
|
|
//
|
307 |
|
|
cfg_dwaddr_rom[12] = 7'h0c; //30
|
308 |
|
|
cfg_dwaddr_rom[13] = 7'h0d; //34
|
309 |
|
|
cfg_dwaddr_rom[14] = 7'h0d; //38 rsvd
|
310 |
|
|
cfg_dwaddr_rom[15] = 7'h0d; //3C
|
311 |
|
|
//
|
312 |
|
|
cfg_dwaddr_rom[16] = 7'h1d; //40
|
313 |
|
|
cfg_dwaddr_rom[17] = 7'h1e; //44
|
314 |
|
|
cfg_dwaddr_rom[18] = 7'h22; //48
|
315 |
|
|
cfg_dwaddr_rom[19] = 7'h23; //4C
|
316 |
|
|
//
|
317 |
|
|
cfg_dwaddr_rom[20] = 7'h24; //50
|
318 |
|
|
cfg_dwaddr_rom[21] = 7'h25; //54
|
319 |
|
|
cfg_dwaddr_rom[22] = 7'h26; //58 mask
|
320 |
|
|
cfg_dwaddr_rom[23] = 7'h27; //5C pend
|
321 |
|
|
//
|
322 |
|
|
cfg_dwaddr_rom[24] = 7'h28; //60
|
323 |
|
|
cfg_dwaddr_rom[25] = 7'h29; //64
|
324 |
|
|
cfg_dwaddr_rom[26] = 7'h2a; //68
|
325 |
|
|
cfg_dwaddr_rom[27] = 7'h2b; //6C
|
326 |
|
|
//
|
327 |
|
|
cfg_dwaddr_rom[28] = 7'h2c; //70
|
328 |
|
|
//these addresses are in backwards order to "stuff" the last address range into the LUTRAM
|
329 |
|
|
// if the upper bits of the cfgdwaddr are "10", then the lower bits that are used to address
|
330 |
|
|
// this LUTRAM are inverted, which convienently happens to be 31,30,29 for inputted addresses
|
331 |
|
|
// 0xh108, 0xh104, 0xh100
|
332 |
|
|
cfg_dwaddr_rom[29] = 7'h48; //108 (dwaddr=66)
|
333 |
|
|
cfg_dwaddr_rom[30] = 7'h47; //104 (dwaddr=65)
|
334 |
|
|
cfg_dwaddr_rom[31] = 7'h46; //100 (dwaddr=64)
|
335 |
|
|
end
|
336 |
|
|
|
337 |
|
|
wire [9:0] cfg_dwaddr_trans = {3'b0,cfg_dwaddr_rom[cfg_dwaddr_int]};
|
338 |
|
|
|
339 |
|
|
`else
|
340 |
|
|
|
341 |
|
|
wire [9:0] cfg_dwaddr_trans;
|
342 |
|
|
assign cfg_dwaddr_trans[9:7] = 3'b000;
|
343 |
|
|
|
344 |
|
|
// fedc ba98 7654 3210 fedc ba98 7654 3210
|
345 |
|
|
LUT5 #(.INIT(32'b1110_0000_0000_0000__0000_0000_0000_0000)) lut_cfgdw_rom6( .O (cfg_dwaddr_trans[6]), .I0(cfg_dwaddr_int[0]), .I1(cfg_dwaddr_int[1]), .I2(cfg_dwaddr_int[2]), .I3(cfg_dwaddr_int[3]), .I4(cfg_dwaddr_int[4]));
|
346 |
|
|
LUT5 #(.INIT(32'b0001_1111_1111_1100__0000_0000_0000_0000)) lut_cfgdw_rom5( .O (cfg_dwaddr_trans[5]), .I0(cfg_dwaddr_int[0]), .I1(cfg_dwaddr_int[1]), .I2(cfg_dwaddr_int[2]), .I3(cfg_dwaddr_int[3]), .I4(cfg_dwaddr_int[4]));
|
347 |
|
|
LUT5 #(.INIT(32'b0000_0000_0000_0011__0000_0000_0000_0000)) lut_cfgdw_rom4( .O (cfg_dwaddr_trans[4]), .I0(cfg_dwaddr_int[0]), .I1(cfg_dwaddr_int[1]), .I2(cfg_dwaddr_int[2]), .I3(cfg_dwaddr_int[3]), .I4(cfg_dwaddr_int[4]));
|
348 |
|
|
|
349 |
|
|
LUT5 #(.INIT(32'b0011_1111_0000_0011__1111_1111_0000_0000)) lut_cfgdw_rom3( .O (cfg_dwaddr_trans[3]), .I0(cfg_dwaddr_int[0]), .I1(cfg_dwaddr_int[1]), .I2(cfg_dwaddr_int[2]), .I3(cfg_dwaddr_int[3]), .I4(cfg_dwaddr_int[4]));
|
350 |
|
|
LUT5 #(.INIT(32'b1101_0000_1111_0011__1111_0000_1111_0000)) lut_cfgdw_rom2( .O (cfg_dwaddr_trans[2]), .I0(cfg_dwaddr_int[0]), .I1(cfg_dwaddr_int[1]), .I2(cfg_dwaddr_int[2]), .I3(cfg_dwaddr_int[3]), .I4(cfg_dwaddr_int[4]));
|
351 |
|
|
LUT5 #(.INIT(32'b1100_1100_1100_1110__0000_1100_1100_1100)) lut_cfgdw_rom1( .O (cfg_dwaddr_trans[1]), .I0(cfg_dwaddr_int[0]), .I1(cfg_dwaddr_int[1]), .I2(cfg_dwaddr_int[2]), .I3(cfg_dwaddr_int[3]), .I4(cfg_dwaddr_int[4]));
|
352 |
|
|
LUT5 #(.INIT(32'b0100_1010_1010_1001__1110_1010_1010_1010)) lut_cfgdw_rom0( .O (cfg_dwaddr_trans[0]), .I0(cfg_dwaddr_int[0]), .I1(cfg_dwaddr_int[1]), .I2(cfg_dwaddr_int[2]), .I3(cfg_dwaddr_int[3]), .I4(cfg_dwaddr_int[4]));
|
353 |
|
|
|
354 |
|
|
`endif
|
355 |
|
|
|
356 |
|
|
wire enable_mgmt_op = (!mgmt_rden && !wait_stg1 && !lock_useraccess);
|
357 |
|
|
reg [9:0] cfg_dwaddr_trans_reg = 0;
|
358 |
|
|
wire cappntr = (cfg_dwaddr[9:0] == 10'h00D);
|
359 |
|
|
wire intline = (cfg_dwaddr[9:0] == 10'h00F);
|
360 |
|
|
|
361 |
|
|
always @(posedge clk) begin
|
362 |
|
|
if (!rst_n) begin
|
363 |
|
|
cfg_rd_en_n_d <= #`Tcq 0;
|
364 |
|
|
cfg_dwaddr_trans_reg <= #`Tcq 0;
|
365 |
|
|
end else begin
|
366 |
|
|
cfg_rd_en_n_d <= #`Tcq cfg_rd_en_n || !cfg_rd_wr_done_n;
|
367 |
|
|
cfg_dwaddr_trans_reg <= #`Tcq cfg_dwaddr_trans;
|
368 |
|
|
end
|
369 |
|
|
end
|
370 |
|
|
|
371 |
|
|
//////////
|
372 |
|
|
// Generate MGMT interface transaction
|
373 |
|
|
always @(posedge clk) begin
|
374 |
|
|
if (!rst_n) begin
|
375 |
|
|
mgmt_addr <= #`Tcq 11'h047;
|
376 |
|
|
mgmt_wdata <= #`Tcq 0;
|
377 |
|
|
mgmt_rden <= #`Tcq 0;
|
378 |
|
|
mgmt_wren <= #`Tcq 0;
|
379 |
|
|
poll_en <= #`Tcq 0;
|
380 |
|
|
poll_dwaddr_cntr <= #`Tcq 0;
|
381 |
|
|
poll_dwaddr_cntr_d1 <= #`Tcq 0;
|
382 |
|
|
zero_out_byte <= #`Tcq 0;
|
383 |
|
|
shift_word <= #`Tcq 0;
|
384 |
|
|
end else if (enable_mgmt_op || falseur_cfg_access_wr || msi_ctrl_cfg_access_wr) begin
|
385 |
|
|
if (falseur_cfg_access_wr) begin
|
386 |
|
|
mgmt_addr <= #`Tcq 11'h02a;
|
387 |
|
|
mgmt_wdata <= #`Tcq {8'h00, 2'b00, mgmt_pso[6], 1'b0, fabric_ur_error_detected,
|
388 |
|
|
mgmt_pso[8], mgmt_pso[9], fabric_co_error_detected, 16'h0000};
|
389 |
|
|
mgmt_rden <= #`Tcq 0;
|
390 |
|
|
mgmt_wren <= #`Tcq 1;
|
391 |
|
|
mgmt_bwren <= #`Tcq 4'b0100;
|
392 |
|
|
poll_en <= #`Tcq 0;
|
393 |
|
|
poll_dwaddr_cntr <= #`Tcq poll_dwaddr_cntr;
|
394 |
|
|
poll_dwaddr_cntr_d1 <= #`Tcq poll_dwaddr_cntr_d1;
|
395 |
|
|
zero_out_byte <= #`Tcq 0;
|
396 |
|
|
shift_word <= #`Tcq 0;
|
397 |
|
|
end else if (msi_ctrl_cfg_access_wr) begin
|
398 |
|
|
mgmt_addr <= #`Tcq 11'h022;
|
399 |
|
|
mgmt_wdata <= #`Tcq 32'h00;
|
400 |
|
|
mgmt_rden <= #`Tcq 0;
|
401 |
|
|
mgmt_wren <= #`Tcq 1;
|
402 |
|
|
mgmt_bwren <= #`Tcq 4'b1000;
|
403 |
|
|
poll_en <= #`Tcq 0;
|
404 |
|
|
poll_dwaddr_cntr <= #`Tcq poll_dwaddr_cntr;
|
405 |
|
|
poll_dwaddr_cntr_d1 <= #`Tcq poll_dwaddr_cntr_d1;
|
406 |
|
|
zero_out_byte <= #`Tcq 0;
|
407 |
|
|
shift_word <= #`Tcq 0;
|
408 |
|
|
// user requests Configuration access
|
409 |
|
|
end else if (!cfg_rd_en_n && !cfg_rd_en_n_d) begin
|
410 |
|
|
mgmt_addr <= #`Tcq {1'b0,cfg_dwaddr_trans_reg[9:0]};
|
411 |
|
|
mgmt_rden <= #`Tcq 1;
|
412 |
|
|
mgmt_wren <= #`Tcq 0;
|
413 |
|
|
mgmt_bwren <= #`Tcq 4'hf;
|
414 |
|
|
poll_en <= #`Tcq 0;
|
415 |
|
|
poll_dwaddr_cntr <= #`Tcq poll_dwaddr_cntr;
|
416 |
|
|
poll_dwaddr_cntr_d1 <= #`Tcq poll_dwaddr_cntr_d1;
|
417 |
|
|
zero_out_byte <= #`Tcq {(cappntr||intline),(cappntr||intline),cappntr,1'b0};
|
418 |
|
|
shift_word <= #`Tcq intline;
|
419 |
|
|
// no User request, begin a new write operation
|
420 |
|
|
end else if (poll_dwrw) begin
|
421 |
|
|
mgmt_addr <= #`Tcq poll_dwaddr;
|
422 |
|
|
mgmt_wdata <= #`Tcq (!poll_dwaddr_cntr[0]) ? cfg_dsn[31:0]:
|
423 |
|
|
cfg_dsn[63:32];
|
424 |
|
|
mgmt_rden <= #`Tcq 0;
|
425 |
|
|
mgmt_wren <= #`Tcq 1;
|
426 |
|
|
mgmt_bwren <= #`Tcq 4'hf;
|
427 |
|
|
poll_en <= #`Tcq 0;
|
428 |
|
|
poll_dwaddr_cntr <= #`Tcq poll_dwaddr_cntr + 1;
|
429 |
|
|
poll_dwaddr_cntr_d1 <= #`Tcq poll_dwaddr_cntr;
|
430 |
|
|
zero_out_byte <= #`Tcq 0;
|
431 |
|
|
shift_word <= #`Tcq 0;
|
432 |
|
|
// no User request, begin a new polling operation
|
433 |
|
|
end else if (!poll_dwrw) begin
|
434 |
|
|
mgmt_addr <= #`Tcq poll_dwaddr;
|
435 |
|
|
mgmt_rden <= #`Tcq 1;
|
436 |
|
|
mgmt_wren <= #`Tcq 0;
|
437 |
|
|
mgmt_bwren <= #`Tcq 4'hf;
|
438 |
|
|
poll_en <= #`Tcq 1;
|
439 |
|
|
poll_dwaddr_cntr <= #`Tcq poll_dwaddr_cntr + 1;
|
440 |
|
|
poll_dwaddr_cntr_d1 <= #`Tcq poll_dwaddr_cntr;
|
441 |
|
|
zero_out_byte <= #`Tcq 0;
|
442 |
|
|
shift_word <= #`Tcq 0;
|
443 |
|
|
// in the middle of a current op, hold values (except turnoff rden)
|
444 |
|
|
end
|
445 |
|
|
end else begin
|
446 |
|
|
mgmt_addr <= #`Tcq mgmt_addr;
|
447 |
|
|
mgmt_rden <= #`Tcq 0;
|
448 |
|
|
mgmt_wren <= #`Tcq 0;
|
449 |
|
|
mgmt_bwren <= #`Tcq 4'hf;
|
450 |
|
|
poll_en <= #`Tcq poll_en;
|
451 |
|
|
poll_dwaddr_cntr <= #`Tcq poll_dwaddr_cntr;
|
452 |
|
|
poll_dwaddr_cntr_d1 <= #`Tcq poll_dwaddr_cntr_d1;
|
453 |
|
|
zero_out_byte <= #`Tcq zero_out_byte;
|
454 |
|
|
shift_word <= #`Tcq shift_word;
|
455 |
|
|
end
|
456 |
|
|
end
|
457 |
|
|
|
458 |
|
|
|
459 |
|
|
|
460 |
|
|
always @(posedge clk) begin
|
461 |
|
|
if (!rst_n) begin
|
462 |
|
|
lock_useraccess <= #`Tcq 0;
|
463 |
|
|
wait_stg1 <= #`Tcq 0;
|
464 |
|
|
wait_stg2 <= #`Tcq 0;
|
465 |
|
|
poll_data_en_d <= #`Tcq 0;
|
466 |
|
|
poll_dwaddr_cntr_d2 <= #`Tcq 0;
|
467 |
|
|
end else begin
|
468 |
|
|
// Lock out new transactions while waiting for user access to complete
|
469 |
|
|
if (!cfg_rd_wr_done_n)
|
470 |
|
|
lock_useraccess <= #`Tcq 0;
|
471 |
|
|
else if (!cfg_rd_en_n && !cfg_rd_en_n_d && !mgmt_rden && !wait_stg1 &&
|
472 |
|
|
!lock_useraccess)
|
473 |
|
|
lock_useraccess <= #`Tcq 1;
|
474 |
|
|
////
|
475 |
|
|
wait_stg1 <= #`Tcq mgmt_rden;
|
476 |
|
|
wait_stg2 <= #`Tcq wait_stg1;
|
477 |
|
|
poll_data_en_d <= #`Tcq poll_data_en;
|
478 |
|
|
poll_dwaddr_cntr_d2 <= #`Tcq poll_dwaddr_cntr_d1;
|
479 |
|
|
end
|
480 |
|
|
end
|
481 |
|
|
|
482 |
|
|
assign poll_data_en = wait_stg2 && poll_en;
|
483 |
|
|
assign cfg_data_en = wait_stg2 && !poll_en;
|
484 |
|
|
|
485 |
|
|
// Indicate whether user or polled access is complete, and capture data
|
486 |
|
|
always @(posedge clk) begin
|
487 |
|
|
if (!rst_n) begin
|
488 |
|
|
cfg_data_en_d <= #`Tcq 0;
|
489 |
|
|
mgmt_rdata_d1 <= #`Tcq 0;
|
490 |
|
|
cfg_do <= #`Tcq 0;
|
491 |
|
|
cfg_rd_wr_done_n <= #`Tcq 1;
|
492 |
|
|
end else begin
|
493 |
|
|
cfg_data_en_d <= #`Tcq cfg_data_en;
|
494 |
|
|
if (poll_data_en || cfg_data_en) begin
|
495 |
|
|
mgmt_rdata_d1 <= #`Tcq mgmt_rdata;
|
496 |
|
|
end
|
497 |
|
|
if (cfg_data_en_d) begin
|
498 |
|
|
case ( zero_out_byte[3])
|
499 |
|
|
1'b0: cfg_do[31:24] <= #`Tcq mgmt_rdata_d1[31:24];
|
500 |
|
|
1'b1: cfg_do[31:24] <= #`Tcq 8'b0;
|
501 |
|
|
endcase
|
502 |
|
|
case ( zero_out_byte[2])
|
503 |
|
|
1'b0: cfg_do[23:16] <= #`Tcq mgmt_rdata_d1[23:16];
|
504 |
|
|
1'b1: cfg_do[23:16] <= #`Tcq 8'b0;
|
505 |
|
|
endcase
|
506 |
|
|
case ({zero_out_byte[1], shift_word})
|
507 |
|
|
2'b00: cfg_do[15:8] <= #`Tcq mgmt_rdata_d1[15:8];
|
508 |
|
|
2'b01: cfg_do[15:8] <= #`Tcq mgmt_rdata_d1[23:16];
|
509 |
|
|
2'b10: cfg_do[15:8] <= #`Tcq 8'b0;
|
510 |
|
|
2'b11: cfg_do[15:8] <= #`Tcq 8'b0;
|
511 |
|
|
endcase
|
512 |
|
|
case ( shift_word)
|
513 |
|
|
1'b0: cfg_do[7:0] <= #`Tcq mgmt_rdata_d1[7:0];
|
514 |
|
|
1'b1: cfg_do[7:0] <= #`Tcq mgmt_rdata_d1[15:8];
|
515 |
|
|
endcase
|
516 |
|
|
end
|
517 |
|
|
cfg_rd_wr_done_n <= #`Tcq !cfg_data_en_d;
|
518 |
|
|
end
|
519 |
|
|
end
|
520 |
|
|
|
521 |
|
|
// For polled data, write captured data to shadow registers
|
522 |
|
|
always @(posedge clk) begin
|
523 |
|
|
if (!rst_n) begin
|
524 |
|
|
cfg_status <= #`Tcq 0;
|
525 |
|
|
cfg_command <= #`Tcq 0;
|
526 |
|
|
cfg_dstatus <= #`Tcq 0;
|
527 |
|
|
cfg_dcommand <= #`Tcq 0;
|
528 |
|
|
cfg_lstatus <= #`Tcq 0;
|
529 |
|
|
cfg_lcommand <= #`Tcq 0;
|
530 |
|
|
cfg_pmcsr <= #`Tcq 0;
|
531 |
|
|
cfg_dcap <= #`Tcq 0;
|
532 |
|
|
cfg_msgctrl <= #`Tcq 0;
|
533 |
|
|
cfg_msgladdr <= #`Tcq 0;
|
534 |
|
|
cfg_msguaddr <= #`Tcq 0;
|
535 |
|
|
cfg_msgdata <= #`Tcq 0;
|
536 |
|
|
cfg_rx_bar0 <= #`Tcq 0;
|
537 |
|
|
cfg_rx_bar1 <= #`Tcq 0;
|
538 |
|
|
cfg_rx_bar2 <= #`Tcq 0;
|
539 |
|
|
cfg_rx_bar3 <= #`Tcq 0;
|
540 |
|
|
cfg_rx_bar4 <= #`Tcq 0;
|
541 |
|
|
cfg_rx_bar5 <= #`Tcq 0;
|
542 |
|
|
cfg_rx_xrom <= #`Tcq 0;
|
543 |
|
|
end else if (poll_data_en_d) begin
|
544 |
|
|
case (poll_dwaddr_cntr_d2)
|
545 |
|
|
5'h2: begin //01
|
546 |
|
|
cfg_status <= #`Tcq mgmt_rdata_d1[31:16];
|
547 |
|
|
cfg_command <= #`Tcq mgmt_rdata_d1[15:0];
|
548 |
|
|
end
|
549 |
|
|
5'h3: //04
|
550 |
|
|
cfg_rx_bar0 <= #`Tcq mgmt_rdata_d1;
|
551 |
|
|
5'h4: //05
|
552 |
|
|
cfg_rx_bar1 <= #`Tcq mgmt_rdata_d1;
|
553 |
|
|
5'h5: //06
|
554 |
|
|
cfg_rx_bar2 <= #`Tcq mgmt_rdata_d1;
|
555 |
|
|
5'h6: //07
|
556 |
|
|
cfg_rx_bar3 <= #`Tcq mgmt_rdata_d1;
|
557 |
|
|
5'h7: //08
|
558 |
|
|
cfg_rx_bar4 <= #`Tcq mgmt_rdata_d1;
|
559 |
|
|
5'h8: //09
|
560 |
|
|
cfg_rx_bar5 <= #`Tcq mgmt_rdata_d1;
|
561 |
|
|
5'h9: //0c
|
562 |
|
|
cfg_rx_xrom <= #`Tcq mgmt_rdata_d1;
|
563 |
|
|
5'ha: begin //2a
|
564 |
|
|
cfg_dstatus <= #`Tcq mgmt_rdata_d1[31:16];
|
565 |
|
|
cfg_dcommand <= #`Tcq mgmt_rdata_d1[15:0];
|
566 |
|
|
end
|
567 |
|
|
5'hb: begin //2c
|
568 |
|
|
cfg_lstatus <= #`Tcq mgmt_rdata_d1[31:16];
|
569 |
|
|
cfg_lcommand <= #`Tcq mgmt_rdata_d1[15:0];
|
570 |
|
|
end
|
571 |
|
|
5'hc: //1e
|
572 |
|
|
cfg_pmcsr <= #`Tcq mgmt_rdata_d1;
|
573 |
|
|
5'hd: //29
|
574 |
|
|
cfg_dcap <= #`Tcq mgmt_rdata_d1;
|
575 |
|
|
5'h10: //22
|
576 |
|
|
cfg_msgctrl <= #`Tcq mgmt_rdata_d1[31:16];
|
577 |
|
|
5'h11: //23
|
578 |
|
|
cfg_msgladdr <= #`Tcq mgmt_rdata_d1;
|
579 |
|
|
5'h12: //24
|
580 |
|
|
cfg_msguaddr <= #`Tcq mgmt_rdata_d1;
|
581 |
|
|
5'h13: //25
|
582 |
|
|
cfg_msgdata <= #`Tcq mgmt_rdata_d1[15:0];
|
583 |
|
|
default: begin end
|
584 |
|
|
endcase
|
585 |
|
|
end
|
586 |
|
|
end
|
587 |
|
|
|
588 |
|
|
|
589 |
|
|
// ANFE workaround for Correctable and Unsupported Request detected
|
590 |
|
|
|
591 |
|
|
|
592 |
|
|
assign fabric_co_error_detect = (|l0_dll_error_vector_d[3:0]) | l0_rx_mac_link_error_d[1] | l0_set_detected_corr_error_d;
|
593 |
|
|
|
594 |
|
|
always @(posedge clk) begin
|
595 |
|
|
if (!rst_n) begin
|
596 |
|
|
mgmt_pso_co_d <= #`Tcq 1'b0;
|
597 |
|
|
mgmt_pso_ur_d <= #`Tcq 1'b0;
|
598 |
|
|
mgmt_pso_co_fell_d <= #`Tcq 1'b0;
|
599 |
|
|
mgmt_pso_ur_fell_d <= #`Tcq 1'b0;
|
600 |
|
|
l0_dll_error_vector_d <= #`Tcq 4'b0;
|
601 |
|
|
l0_rx_mac_link_error_d <= #`Tcq 2'b0;
|
602 |
|
|
l0_set_detected_corr_error_d <= #`Tcq 1'b0;
|
603 |
|
|
end else begin
|
604 |
|
|
mgmt_pso_co_d <= #`Tcq mgmt_pso[10];
|
605 |
|
|
mgmt_pso_ur_d <= #`Tcq mgmt_pso[7];
|
606 |
|
|
mgmt_pso_co_fell_d <= #`Tcq !mgmt_pso[10]&& mgmt_pso_co_d;
|
607 |
|
|
mgmt_pso_ur_fell_d <= #`Tcq !mgmt_pso[7] && mgmt_pso_ur_d;
|
608 |
|
|
l0_dll_error_vector_d <= #`Tcq l0_dll_error_vector[3:0];
|
609 |
|
|
l0_rx_mac_link_error_d <= #`Tcq l0_rx_mac_link_error[1:0];
|
610 |
|
|
l0_set_detected_corr_error_d <= #`Tcq l0_set_detected_corr_error;
|
611 |
|
|
end
|
612 |
|
|
end
|
613 |
|
|
|
614 |
|
|
always @(posedge clk) begin
|
615 |
|
|
if (!rst_n) begin
|
616 |
|
|
fabric_co_error_detected <= #`Tcq 1'b0;
|
617 |
|
|
end else if (mgmt_pso_co_fell_d) begin
|
618 |
|
|
fabric_co_error_detected <= #`Tcq 1'b0;
|
619 |
|
|
end else if (fabric_co_error_detect) begin
|
620 |
|
|
fabric_co_error_detected <= #`Tcq 1'b1;
|
621 |
|
|
end
|
622 |
|
|
end
|
623 |
|
|
|
624 |
|
|
assign fabric_ur_error_detect = l0_set_unsupported_request_other_error;
|
625 |
|
|
always @(posedge clk) begin
|
626 |
|
|
if (!rst_n) begin
|
627 |
|
|
fabric_ur_error_detected <= #`Tcq 1'b0;
|
628 |
|
|
end else if (mgmt_pso_ur_fell_d) begin
|
629 |
|
|
fabric_ur_error_detected <= #`Tcq 1'b0;
|
630 |
|
|
end else if (fabric_ur_error_detect) begin
|
631 |
|
|
fabric_ur_error_detected <= #`Tcq 1'b1;
|
632 |
|
|
end
|
633 |
|
|
end
|
634 |
|
|
|
635 |
|
|
// override the bits only when Root is reading the Device Control/Status
|
636 |
|
|
// Register, and both the internal Correctable and UR Error detected bits
|
637 |
|
|
// are 1
|
638 |
|
|
always @(posedge clk)
|
639 |
|
|
if (!rst_n)
|
640 |
|
|
detected_cfg_read1cycle <= #`Tcq 1'b0;
|
641 |
|
|
else if (llk_rx_data_d[63:32] == 32'h04000001)
|
642 |
|
|
detected_cfg_read1cycle <= #`Tcq 1'b1;
|
643 |
|
|
else if (!(detected_h68read2cycle | detected_h48read2cycle))
|
644 |
|
|
detected_cfg_read1cycle <= #`Tcq 1'b0;
|
645 |
|
|
|
646 |
|
|
assign detected_h68read2cycle = (llk_rx_data_d[47:32] == 16'h0068);
|
647 |
|
|
|
648 |
|
|
always @(posedge clk) begin
|
649 |
|
|
if (!rst_n) begin
|
650 |
|
|
detected_h68read <= #`Tcq 1'b0;
|
651 |
|
|
detected_h68read_d <= #`Tcq 1'b0;
|
652 |
|
|
end else begin
|
653 |
|
|
detected_h68read <= #`Tcq detected_cfg_read1cycle &&
|
654 |
|
|
detected_h68read2cycle;
|
655 |
|
|
detected_h68read_d <= #`Tcq detected_h68read;
|
656 |
|
|
end
|
657 |
|
|
end
|
658 |
|
|
|
659 |
|
|
assign falseur_cfg_access_wr = falseur_cfg_access_wr_reg;
|
660 |
|
|
|
661 |
|
|
always @(posedge clk) begin
|
662 |
|
|
if (!rst_n | l0_stats_cfg_transmitted) begin
|
663 |
|
|
falseur_cfg_access_wr_reg <= #`Tcq 1'b0;
|
664 |
|
|
end else if (!falseur_cfg_access_wr_reg) begin
|
665 |
|
|
falseur_cfg_access_wr_reg <= #`Tcq (detected_h68read_d && l0_stats_cfg_received &&
|
666 |
|
|
(mgmt_pso_co_d || mgmt_pso_ur_d));
|
667 |
|
|
end
|
668 |
|
|
end
|
669 |
|
|
|
670 |
|
|
//end of ANFE workaround
|
671 |
|
|
|
672 |
|
|
// override the PVM bit only when Root is reading the MSI control Register
|
673 |
|
|
|
674 |
|
|
assign detected_h48read2cycle = (llk_rx_data_d[47:32] == 16'h0048);
|
675 |
|
|
|
676 |
|
|
always @(posedge clk) begin
|
677 |
|
|
if (!rst_n) begin
|
678 |
|
|
detected_h48read <= #`Tcq 1'b0;
|
679 |
|
|
detected_h48read_d <= #`Tcq 1'b0;
|
680 |
|
|
end else begin
|
681 |
|
|
detected_h48read <= #`Tcq detected_cfg_read1cycle &&
|
682 |
|
|
detected_h48read2cycle;
|
683 |
|
|
detected_h48read_d <= #`Tcq detected_h48read;
|
684 |
|
|
end
|
685 |
|
|
end
|
686 |
|
|
|
687 |
|
|
assign msi_ctrl_cfg_access_wr = msi_ctrl_cfg_access_wr_reg;
|
688 |
|
|
|
689 |
|
|
always @(posedge clk) begin
|
690 |
|
|
if (!rst_n | l0_stats_cfg_transmitted) begin
|
691 |
|
|
msi_ctrl_cfg_access_wr_reg <= #`Tcq 1'b0;
|
692 |
|
|
end else if (!msi_ctrl_cfg_access_wr_reg) begin
|
693 |
|
|
msi_ctrl_cfg_access_wr_reg <= #`Tcq (detected_h48read_d && l0_stats_cfg_received);
|
694 |
|
|
end
|
695 |
|
|
end
|
696 |
|
|
|
697 |
|
|
endmodule // pcie_blk_cf_mgmt
|
698 |
|
|
|
699 |
|
|
|