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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [pcie_blk_cf_pwr.v] - Blame information for rev 2

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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project    : V5-Block Plus for PCI Express
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// File       : pcie_blk_cf_pwr.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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//--
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//-- Description: PCIe Block Power Management Interface
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//--
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//--             
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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`ifndef TCQ
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 `define TCQ 1
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`endif
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module pcie_blk_cf_pwr
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(
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       // Clock and reset
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       input              clk,
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       input              rst_n,
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       // User Interface Power Management Ports
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       input              cfg_turnoff_ok_n,
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       output reg         cfg_to_turnoff_n,
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       input              cfg_pm_wake_n,
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       // PCIe Block Power Management Ports
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       input              l0_pwr_turn_off_req,
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       output reg         l0_pme_req_in,
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       input              l0_pme_ack,
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       // Interface to arbiter
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       output reg         send_pmeack,
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       input              cs_is_pm,
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       input              grant
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);
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always @(posedge clk)
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begin
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  if (~rst_n) begin
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    cfg_to_turnoff_n    <= #`TCQ 1;
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    send_pmeack         <= #`TCQ 0;
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    l0_pme_req_in       <= #`TCQ 0;
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  end else begin
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    //PME Turn Off message rec'd; inform user
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    if (l0_pwr_turn_off_req)
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      cfg_to_turnoff_n    <= #`TCQ 0;
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    else if (~cfg_turnoff_ok_n)
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      cfg_to_turnoff_n    <= #`TCQ 1;
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    //User issues PME To ACK
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    if (~cfg_turnoff_ok_n && ~cfg_to_turnoff_n)
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      send_pmeack         <= #`TCQ 1;
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    else if (cs_is_pm && grant)
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      send_pmeack         <= #`TCQ 0;
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    //Send a PM PME message
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    if (~cfg_pm_wake_n)
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      l0_pme_req_in       <= #`TCQ 1;
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    else if (l0_pme_ack)
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      l0_pme_req_in       <= #`TCQ 0;
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  end
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end
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endmodule // pcie_blk_cf_pwr
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