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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : pcie_blk_ll.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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//--
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//-- Description: PCIe Block LocalLink Bridge
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module pcie_blk_ll #
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(
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parameter BAR0 = 32'hffff_0001, // base address cfg[ 95: 64]
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parameter BAR1 = 32'hffff_0000, // base address cfg[127: 96]
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parameter BAR2 = 32'hffff_0004, // base address cfg[159:128]
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parameter BAR3 = 32'hffff_ffff, // base address cfg[191:160]
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parameter BAR4 = 32'h0000_0000, // base address cfg[223:192]
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parameter BAR5 = 32'h0000_0000, // base address cfg[255:224]
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parameter XROM_BAR = 32'hffff_f001, // expansion rom bar cfg[351:320]
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parameter MPS = 3'b101, // Max Payload Size cfg[370:368]
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parameter LEGACY_EP = 1'b0, // Legacy PCI endpoint?
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parameter TRIM_ECRC = 1'b0, // Trim ECRC from rx TLPs cfg[508]
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parameter CPL_STREAMING_PRIORITIZE_P_NP = 0, // arb priority to P/NP during cpl strm
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parameter C_CALENDAR_LEN = 9,
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parameter C_CALENDAR_SUB_LEN = 12,
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parameter C_CALENDAR_SEQ = 72'h68_08_68_2C_68_08_68_0C_FF, //S Tc S T1 S Tc S T2 F
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parameter C_CALENDAR_SUB_SEQ = 96'h40_60_44_64_4C_6C_20_24_28_2C_30_34,
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parameter TX_DATACREDIT_FIX_EN = 1,
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parameter TX_DATACREDIT_FIX_1DWONLY= 1,
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parameter TX_DATACREDIT_FIX_MARGIN = 6,
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parameter TX_CPL_STALL_THRESHOLD = 6
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)
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(
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// Clock and reset
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input wire clk,
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input wire rst_n,
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// Transaction Link Up
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input trn_lnk_up_n,
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// PCIe Block Tx Ports
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output [63:0] llk_tx_data,
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output llk_tx_src_rdy_n,
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output llk_tx_src_dsc_n,
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output llk_tx_sof_n,
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output llk_tx_eof_n,
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output llk_tx_sop_n,
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output llk_tx_eop_n,
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output [1:0] llk_tx_enable_n,
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output [2:0] llk_tx_ch_tc,
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output [1:0] llk_tx_ch_fifo,
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input wire llk_tx_dst_rdy_n,
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input wire [9:0] llk_tx_chan_space,
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input wire [7:0] llk_tx_ch_posted_ready_n,
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input wire [7:0] llk_tx_ch_non_posted_ready_n,
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input wire [7:0] llk_tx_ch_completion_ready_n,
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// PCIe Block Rx Ports
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output llk_rx_dst_req_n,
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output llk_rx_dst_cont_req_n,
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output [2:0] llk_rx_ch_tc,
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output [1:0] llk_rx_ch_fifo,
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input wire [7:0] llk_tc_status,
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input wire [63:0] llk_rx_data,
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output wire [63:0] llk_rx_data_d, //needed by mgmt module
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input wire llk_rx_src_rdy_n,
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input wire llk_rx_src_last_req_n,
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input wire llk_rx_src_dsc_n,
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input wire llk_rx_sof_n,
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input wire llk_rx_eof_n,
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input wire [1:0] llk_rx_valid_n,
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input wire [7:0] llk_rx_ch_posted_available_n,
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input wire [7:0] llk_rx_ch_non_posted_available_n,
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input wire [7:0] llk_rx_ch_completion_available_n,
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input wire [15:0] llk_rx_preferred_type,
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// PCIe Block MGMT Credit Status
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output wire [6:0] mgmt_stats_credit_sel,
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input wire [11:0] mgmt_stats_credit,
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// LocalLink Tx Ports (User)
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input wire [63:0] trn_td,
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input wire [7:0] trn_trem_n,
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input wire trn_tsof_n,
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input trn_teof_n,
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input trn_tsrc_rdy_n,
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input trn_tsrc_dsc_n,
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input trn_terrfwd_n,
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output trn_tdst_rdy_n,
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output trn_tdst_dsc_n,
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output [3:0] trn_tbuf_av,
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output [7:0] trn_pfc_nph_cl,
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output [11:0] trn_pfc_npd_cl,
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output [7:0] trn_pfc_ph_cl,
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output [11:0] trn_pfc_pd_cl,
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output [7:0] trn_pfc_cplh_cl,
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output [11:0] trn_pfc_cpld_cl,
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// LocalLink TX Ports (Cfg/Mgmt)
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input [63:0] cfg_tx_td,
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input cfg_tx_rem_n,
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input cfg_tx_sof_n,
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input cfg_tx_eof_n,
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input cfg_tx_src_rdy_n,
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output cfg_tx_dst_rdy_n,
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// LocalLink Rx Ports
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output [63:0] trn_rd,
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output [7:0] trn_rrem_n,
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output trn_rsof_n,
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output trn_reof_n,
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output trn_rsrc_rdy_n,
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output trn_rsrc_dsc_n,
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output trn_rerrfwd_n,
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output [6:0] trn_rbar_hit_n,
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output [7:0] trn_rfc_nph_av,
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output [11:0] trn_rfc_npd_av,
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output [7:0] trn_rfc_ph_av,
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output [11:0] trn_rfc_pd_av,
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output [7:0] trn_rfc_cplh_av,
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output [11:0] trn_rfc_cpld_av,
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input wire trn_rnp_ok_n,
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input wire trn_rdst_rdy_n,
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input wire trn_rcpl_streaming_n,
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// Sideband signals to control operation
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input wire [31:0] cfg_rx_bar0,
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input wire [31:0] cfg_rx_bar1,
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input wire [31:0] cfg_rx_bar2,
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input wire [31:0] cfg_rx_bar3,
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input wire [31:0] cfg_rx_bar4,
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input wire [31:0] cfg_rx_bar5,
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input wire [31:0] cfg_rx_xrom,
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input wire [7:0] cfg_bus_number,
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input wire [4:0] cfg_device_number,
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input wire [2:0] cfg_function_number,
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input wire [15:0] cfg_dcommand,
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input wire [15:0] cfg_pmcsr,
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input wire io_space_enable,
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input wire mem_space_enable,
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input wire [2:0] max_payload_size,
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// Error signaling logic
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output wire rx_err_cpl_abort_n,
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output wire rx_err_cpl_ur_n,
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output wire rx_err_cpl_ep_n,
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output wire rx_err_ep_n,
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output wire [47:0] err_tlp_cpl_header,
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output wire err_tlp_p,
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output wire err_tlp_ur,
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output wire err_tlp_ur_lock,
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output wire err_tlp_uc,
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output wire err_tlp_malformed,
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output wire tx_err_wr_ep_n,
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input l0_stats_tlp_received,
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input l0_stats_cfg_transmitted
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);
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wire [7:0] tx_ch_credits_consumed;
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wire [11:0] tx_pd_credits_consumed;
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wire [11:0] tx_pd_credits_available;
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wire [11:0] tx_npd_credits_consumed;
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wire [11:0] tx_npd_credits_available;
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wire [11:0] tx_cd_credits_consumed;
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wire [11:0] tx_cd_credits_available;
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wire [7:0] rx_ch_credits_received;
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wire trn_pfc_cplh_cl_upd;
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pcie_blk_plus_ll_tx #
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( .TX_CPL_STALL_THRESHOLD ( TX_CPL_STALL_THRESHOLD ),
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.TX_DATACREDIT_FIX_EN ( TX_DATACREDIT_FIX_EN ),
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.TX_DATACREDIT_FIX_1DWONLY( TX_DATACREDIT_FIX_1DWONLY ),
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.TX_DATACREDIT_FIX_MARGIN ( TX_DATACREDIT_FIX_MARGIN ),
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.MPS ( MPS ),
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.LEGACY_EP ( LEGACY_EP )
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)
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tx_bridge
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(
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// Clock & Reset
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.clk( clk ), // I
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.rst_n( rst_n ), // I
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| 246 |
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// Transaction Link Up
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| 248 |
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.trn_lnk_up_n (trn_lnk_up_n), // I
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// PCIe Block Tx Ports
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.llk_tx_data( llk_tx_data ), // O[63:0]
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.llk_tx_src_rdy_n( llk_tx_src_rdy_n ), // O
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.llk_tx_src_dsc_n( llk_tx_src_dsc_n ), // O
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| 256 |
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.llk_tx_sof_n( llk_tx_sof_n ), // O
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| 257 |
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.llk_tx_eof_n( llk_tx_eof_n ), // O
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| 258 |
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.llk_tx_sop_n( llk_tx_sop_n ), // O
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| 259 |
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.llk_tx_eop_n( llk_tx_eop_n ), // O
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| 260 |
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.llk_tx_enable_n( llk_tx_enable_n ), // O[1:0]
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.llk_tx_ch_tc( llk_tx_ch_tc ), // O[2:0]
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.llk_tx_ch_fifo( llk_tx_ch_fifo ), // O[1:0]
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| 264 |
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.llk_tx_dst_rdy_n( llk_tx_dst_rdy_n ), // I
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| 265 |
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.llk_tx_chan_space( llk_tx_chan_space ), // I[9:0]
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| 266 |
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.llk_tx_ch_posted_ready_n( llk_tx_ch_posted_ready_n ), // I[7:0]
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| 267 |
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.llk_tx_ch_non_posted_ready_n( llk_tx_ch_non_posted_ready_n ), // I[7:0]
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| 268 |
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.llk_tx_ch_completion_ready_n( llk_tx_ch_completion_ready_n ), // I[7:0]
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| 269 |
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| 270 |
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// LocalLink Tx Ports
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| 271 |
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| 272 |
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.trn_td( trn_td ), // I[63:0]
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| 273 |
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.trn_trem_n( trn_trem_n ), // I[7:0]
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.trn_tsof_n( trn_tsof_n ), // I
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| 275 |
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.trn_teof_n( trn_teof_n ), // I
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| 276 |
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.trn_tsrc_rdy_n( trn_tsrc_rdy_n ), // I
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| 277 |
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.trn_tsrc_dsc_n( trn_tsrc_dsc_n ), // I
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| 278 |
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.trn_terrfwd_n( trn_terrfwd_n ), // I
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| 279 |
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| 280 |
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.trn_tdst_rdy_n( trn_tdst_rdy_n ), // O
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| 281 |
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.trn_tdst_dsc_n( trn_tdst_dsc_n ), // O
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.trn_tbuf_av( trn_tbuf_av ), // O[2:0]
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// Config Tx Ports
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| 286 |
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.cfg_tx_td( cfg_tx_td ), // I[63:0]
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| 287 |
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.cfg_tx_rem_n( cfg_tx_rem_n ), // I
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| 288 |
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.cfg_tx_sof_n( cfg_tx_sof_n ), // I
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| 289 |
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.cfg_tx_eof_n( cfg_tx_eof_n ), // I
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| 290 |
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.cfg_tx_src_rdy_n( cfg_tx_src_rdy_n ), // I
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| 291 |
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.cfg_tx_dst_rdy_n( cfg_tx_dst_rdy_n ), // O
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| 292 |
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| 293 |
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// Status Ports
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| 294 |
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|
.tx_err_wr_ep_n( tx_err_wr_ep_n ), // O
|
| 295 |
|
|
.tx_ch_credits_consumed ( tx_ch_credits_consumed ),
|
| 296 |
|
|
.tx_pd_credits_available ( tx_pd_credits_available ),
|
| 297 |
|
|
.tx_pd_credits_consumed ( tx_pd_credits_consumed ),
|
| 298 |
|
|
.tx_npd_credits_available ( tx_npd_credits_available ),
|
| 299 |
|
|
.tx_npd_credits_consumed ( tx_npd_credits_consumed ),
|
| 300 |
|
|
.tx_cd_credits_available ( tx_cd_credits_available ),
|
| 301 |
|
|
.tx_cd_credits_consumed ( tx_cd_credits_consumed ),
|
| 302 |
|
|
.clear_cpl_count ( clear_cpl_count ),
|
| 303 |
|
|
.pd_credit_limited ( pd_credit_limited ),
|
| 304 |
|
|
.npd_credit_limited ( npd_credit_limited ),
|
| 305 |
|
|
.cd_credit_limited ( cd_credit_limited ),
|
| 306 |
|
|
.trn_pfc_cplh_cl ( trn_pfc_cplh_cl),
|
| 307 |
|
|
.trn_pfc_cplh_cl_upd ( trn_pfc_cplh_cl_upd),
|
| 308 |
|
|
.l0_stats_cfg_transmitted ( l0_stats_cfg_transmitted )
|
| 309 |
|
|
);
|
| 310 |
|
|
|
| 311 |
|
|
pcie_blk_plus_ll_rx #
|
| 312 |
|
|
( .BAR0( BAR0 ),
|
| 313 |
|
|
.BAR1( BAR1 ),
|
| 314 |
|
|
.BAR2( BAR2 ),
|
| 315 |
|
|
.BAR3( BAR3 ),
|
| 316 |
|
|
.BAR4( BAR4 ),
|
| 317 |
|
|
.BAR5( BAR5 ),
|
| 318 |
|
|
.XROM_BAR( XROM_BAR ),
|
| 319 |
|
|
.MPS( MPS ),
|
| 320 |
|
|
.LEGACY_EP ( LEGACY_EP ),
|
| 321 |
|
|
.TRIM_ECRC ( TRIM_ECRC ),
|
| 322 |
|
|
.CPL_STREAMING_PRIORITIZE_P_NP(CPL_STREAMING_PRIORITIZE_P_NP)
|
| 323 |
|
|
)
|
| 324 |
|
|
rx_bridge
|
| 325 |
|
|
(
|
| 326 |
|
|
// Clock & Reset
|
| 327 |
|
|
|
| 328 |
|
|
.clk( clk ), // I
|
| 329 |
|
|
.rst_n( rst_n ), // I
|
| 330 |
|
|
|
| 331 |
|
|
// PCIe Block Rx Ports
|
| 332 |
|
|
|
| 333 |
|
|
.llk_rx_dst_req_n( llk_rx_dst_req_n ), // O
|
| 334 |
|
|
.llk_rx_ch_tc( llk_rx_ch_tc ), // O[2:0]
|
| 335 |
|
|
.llk_rx_ch_fifo( llk_rx_ch_fifo ), // O[1:0]
|
| 336 |
|
|
.llk_rx_dst_cont_req_n(llk_rx_dst_cont_req_n ), // O
|
| 337 |
|
|
.llk_tc_status( llk_tc_status ), // I[7:0]
|
| 338 |
|
|
.llk_rx_data ( llk_rx_data ), // I[63:0]
|
| 339 |
|
|
.llk_rx_data_d( llk_rx_data_d ), // O[63:0]
|
| 340 |
|
|
.llk_rx_src_rdy_n( llk_rx_src_rdy_n ), // I
|
| 341 |
|
|
.llk_rx_src_last_req_n( llk_rx_src_last_req_n ), // I
|
| 342 |
|
|
.llk_rx_src_dsc_n( llk_rx_src_dsc_n ), // I
|
| 343 |
|
|
.llk_rx_sof_n( llk_rx_sof_n ), // I
|
| 344 |
|
|
.llk_rx_eof_n( llk_rx_eof_n ), // I
|
| 345 |
|
|
.llk_rx_valid_n( llk_rx_valid_n ), // I[1:0]
|
| 346 |
|
|
.llk_rx_ch_posted_available_n( llk_rx_ch_posted_available_n ), // I[7:0]
|
| 347 |
|
|
.llk_rx_ch_non_posted_available_n( llk_rx_ch_non_posted_available_n ), // I[7:0]
|
| 348 |
|
|
.llk_rx_ch_completion_available_n( llk_rx_ch_completion_available_n ), // I[7:0]
|
| 349 |
|
|
.llk_rx_preferred_type( llk_rx_preferred_type ), // I[15:0]
|
| 350 |
|
|
|
| 351 |
|
|
// LocalLink Rx Ports
|
| 352 |
|
|
.trn_rd( trn_rd ), // O[63:0]
|
| 353 |
|
|
.trn_rrem_n( trn_rrem_n ), // O[7:0]
|
| 354 |
|
|
.trn_rsof_n( trn_rsof_n ), // O
|
| 355 |
|
|
.trn_reof_n( trn_reof_n ), // O
|
| 356 |
|
|
.trn_rsrc_rdy_n( trn_rsrc_rdy_n ), // O
|
| 357 |
|
|
.trn_rsrc_dsc_n( trn_rsrc_dsc_n ), // O
|
| 358 |
|
|
.trn_rerrfwd_n( trn_rerrfwd_n ), // O
|
| 359 |
|
|
.trn_rbar_hit_n( trn_rbar_hit_n ), // O[6:0]
|
| 360 |
|
|
.trn_lnk_up_n( trn_lnk_up_n ), // O
|
| 361 |
|
|
|
| 362 |
|
|
.trn_rnp_ok_n( trn_rnp_ok_n ), // I
|
| 363 |
|
|
.trn_rdst_rdy_n( trn_rdst_rdy_n ), // I
|
| 364 |
|
|
.trn_rcpl_streaming_n( trn_rcpl_streaming_n ), // I
|
| 365 |
|
|
|
| 366 |
|
|
// Sideband signals to control operation
|
| 367 |
|
|
.cfg_rx_bar0( cfg_rx_bar0 ), // I[31:0]
|
| 368 |
|
|
.cfg_rx_bar1( cfg_rx_bar1 ), // I[31:0]
|
| 369 |
|
|
.cfg_rx_bar2( cfg_rx_bar2 ), // I[31:0]
|
| 370 |
|
|
.cfg_rx_bar3( cfg_rx_bar3 ), // I[31:0]
|
| 371 |
|
|
.cfg_rx_bar4( cfg_rx_bar4 ), // I[31:0]
|
| 372 |
|
|
.cfg_rx_bar5( cfg_rx_bar5 ), // I[31:0]
|
| 373 |
|
|
.cfg_rx_xrom( cfg_rx_xrom ), // I[31:0]
|
| 374 |
|
|
.cfg_bus_number( cfg_bus_number ), // I[7:0]
|
| 375 |
|
|
.cfg_device_number( cfg_device_number ), // I[4:0]
|
| 376 |
|
|
.cfg_function_number( cfg_function_number ), // I[2:0]
|
| 377 |
|
|
.cfg_dcommand( cfg_dcommand ), // I[15:0]
|
| 378 |
|
|
.cfg_pmcsr( cfg_pmcsr ), // I[15:0]
|
| 379 |
|
|
.io_space_enable( io_space_enable ), // I
|
| 380 |
|
|
.mem_space_enable( mem_space_enable ), // I
|
| 381 |
|
|
.max_payload_size( max_payload_size ), // I[2:0]
|
| 382 |
|
|
|
| 383 |
|
|
// Error reporting
|
| 384 |
|
|
.rx_err_cpl_abort_n( rx_err_cpl_abort_n ), // O
|
| 385 |
|
|
.rx_err_cpl_ur_n( rx_err_cpl_ur_n ), // O
|
| 386 |
|
|
.rx_err_cpl_ep_n( rx_err_cpl_ep_n ), // O
|
| 387 |
|
|
.rx_err_ep_n( rx_err_ep_n ), // O
|
| 388 |
|
|
.err_tlp_cpl_header( err_tlp_cpl_header ), // O[47:0]
|
| 389 |
|
|
.err_tlp_p( err_tlp_p ), // O
|
| 390 |
|
|
.err_tlp_ur( err_tlp_ur ), // O
|
| 391 |
|
|
.err_tlp_ur_lock( err_tlp_ur_lock ), // O
|
| 392 |
|
|
.err_tlp_uc( err_tlp_uc ), // O
|
| 393 |
|
|
.err_tlp_malformed( err_tlp_malformed ), // O
|
| 394 |
|
|
.rx_ch_credits_received (rx_ch_credits_received),
|
| 395 |
|
|
.rx_ch_credits_received_inc (rx_ch_credits_received_inc),
|
| 396 |
|
|
.l0_stats_tlp_received (l0_stats_tlp_received)
|
| 397 |
|
|
);
|
| 398 |
|
|
|
| 399 |
|
|
// Rx Credit calculation logic
|
| 400 |
|
|
pcie_blk_ll_credit
|
| 401 |
|
|
#( .C_CALENDAR_LEN (C_CALENDAR_LEN),
|
| 402 |
|
|
.C_CALENDAR_SUB_LEN (C_CALENDAR_SUB_LEN),
|
| 403 |
|
|
.C_CALENDAR_SEQ (C_CALENDAR_SEQ),
|
| 404 |
|
|
.C_CALENDAR_SUB_SEQ (C_CALENDAR_SUB_SEQ),
|
| 405 |
|
|
.MPS (MPS),
|
| 406 |
|
|
.LEGACY_EP (LEGACY_EP)
|
| 407 |
|
|
)
|
| 408 |
|
|
ll_credit
|
| 409 |
|
|
(.clk (clk),
|
| 410 |
|
|
.rst_n (rst_n),
|
| 411 |
|
|
.mgmt_stats_credit_sel (mgmt_stats_credit_sel),
|
| 412 |
|
|
.mgmt_stats_credit (mgmt_stats_credit),
|
| 413 |
|
|
.trn_pfc_nph_cl( trn_pfc_nph_cl),
|
| 414 |
|
|
.trn_pfc_npd_cl( trn_pfc_npd_cl),
|
| 415 |
|
|
.trn_pfc_ph_cl( trn_pfc_ph_cl),
|
| 416 |
|
|
.trn_pfc_pd_cl( trn_pfc_pd_cl),
|
| 417 |
|
|
.trn_pfc_cplh_cl (trn_pfc_cplh_cl),
|
| 418 |
|
|
.trn_pfc_cplh_cl_upd (trn_pfc_cplh_cl_upd),
|
| 419 |
|
|
.trn_pfc_cpld_cl (trn_pfc_cpld_cl),
|
| 420 |
|
|
.trn_lnk_up_n (trn_lnk_up_n),
|
| 421 |
|
|
.trn_rfc_ph_av (trn_rfc_ph_av),
|
| 422 |
|
|
.trn_rfc_pd_av (trn_rfc_pd_av),
|
| 423 |
|
|
.trn_rfc_nph_av (trn_rfc_nph_av),
|
| 424 |
|
|
.trn_rfc_npd_av (trn_rfc_npd_av),
|
| 425 |
|
|
.trn_rfc_cplh_av (trn_rfc_cplh_av),
|
| 426 |
|
|
.trn_rfc_cpld_av (trn_rfc_cpld_av),
|
| 427 |
|
|
.trn_rcpl_streaming_n (trn_rcpl_streaming_n),
|
| 428 |
|
|
.rx_ch_credits_received (rx_ch_credits_received),
|
| 429 |
|
|
.rx_ch_credits_received_inc (rx_ch_credits_received_inc),
|
| 430 |
|
|
.tx_ch_credits_consumed (tx_ch_credits_consumed),
|
| 431 |
|
|
.tx_pd_credits_available (tx_pd_credits_available),
|
| 432 |
|
|
.tx_pd_credits_consumed (tx_pd_credits_consumed),
|
| 433 |
|
|
.tx_npd_credits_available (tx_npd_credits_available),
|
| 434 |
|
|
.tx_npd_credits_consumed (tx_npd_credits_consumed),
|
| 435 |
|
|
.tx_cd_credits_available (tx_cd_credits_available),
|
| 436 |
|
|
.tx_cd_credits_consumed (tx_cd_credits_consumed),
|
| 437 |
|
|
.clear_cpl_count (clear_cpl_count),
|
| 438 |
|
|
.pd_credit_limited (pd_credit_limited),
|
| 439 |
|
|
.npd_credit_limited (npd_credit_limited),
|
| 440 |
|
|
.cd_credit_limited (cd_credit_limited),
|
| 441 |
|
|
.l0_stats_cfg_transmitted (l0_stats_cfg_transmitted)
|
| 442 |
|
|
);
|
| 443 |
|
|
|
| 444 |
|
|
endmodule // pcie_blk_ll
|
