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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : pcie_blk_ll_credit.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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//--
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//-- Description: Rx Credit Calculation. This module will compute the credit
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//-- availability of the various queue types.
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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`ifndef Tcq
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`define Tcq 1
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`endif
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module pcie_blk_ll_credit
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//{{{ Module Port/Parameters
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#(
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parameter C_STREAMING = 0,
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parameter C_CALENDAR_STREAMING = 4,
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parameter C_CALENDAR_LEN = 9,
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parameter C_CALENDAR_SUB_LEN = 12,
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//RxStream=68, TxCpl=08, SUB_SEQ=FF
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parameter C_CALENDAR_SEQ = 72'h68_08_68_2C_68_08_68_0C_FF, //S Tc S T1 S Tc S T2 F
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//CPLLim: tPHl=20,tNPHl=24,tCHl=28,tPDl=2C,tNPDl=30,tCDl=34
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//RFC: rPHa=40,rPHr=60,rNPHa=44,rNPHr=64,rPDa=4C,rPDr=6C
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parameter C_CALENDAR_SUB_SEQ = 96'h40_60_44_64_4C_6C_20_24_28_2C_30_34,
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parameter MPS = 3'b101,
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parameter LEGACY_EP = 0,
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//These parameters are only used for SV assertions, and are set via
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//defparams via "board.v".
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parameter BFM_INIT_FC_PH = 0,
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parameter BFM_INIT_FC_PD = 0,
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parameter BFM_INIT_FC_NPH = 0,
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parameter BFM_INIT_FC_NPD = 0,
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parameter BFM_INIT_FC_CPLH = 0,
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parameter BFM_INIT_FC_CPLD = 0
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)
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(
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// PCIe Block clock and reset
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input wire clk,
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input wire rst_n,
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// PCIe Block Management Interface
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output reg [6:0] mgmt_stats_credit_sel,
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input wire [11:0] mgmt_stats_credit,
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// PCIe Soft Macro Trn Interface
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output reg [7:0] trn_pfc_ph_cl = 0,
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output reg [7:0] trn_pfc_nph_cl = 0,
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output reg [7:0] trn_pfc_cplh_cl = 0,
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output reg trn_pfc_cplh_cl_upd = 0,
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output reg [11:0] trn_pfc_pd_cl = 0,
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output reg [11:0] trn_pfc_npd_cl = 0,
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output reg [11:0] trn_pfc_cpld_cl = 0,
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input trn_lnk_up_n,
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output reg [7:0] trn_rfc_ph_av = 0,
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output reg [11:0] trn_rfc_pd_av = 0,
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output reg [7:0] trn_rfc_nph_av = 0,
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output wire [11:0] trn_rfc_npd_av,
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output wire [7:0] trn_rfc_cplh_av,
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output wire [11:0] trn_rfc_cpld_av,
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// I/O to Rx Arb, for Streaming Credit Data
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input wire trn_rcpl_streaming_n,
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output reg [7:0] rx_ch_credits_received = 0,
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output reg rx_ch_credits_received_inc = 0,
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// I/O for Tx Cpl Data
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output reg [7:0] tx_ch_credits_consumed = 0,
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// I/O for Tx PD
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output reg [11:0] tx_pd_credits_available = 0,
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output reg [11:0] tx_pd_credits_consumed = 0,
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output reg [11:0] tx_npd_credits_available = 0,
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output reg [11:0] tx_npd_credits_consumed = 0,
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output reg [11:0] tx_cd_credits_available = 0,
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output wire [11:0] tx_cd_credits_consumed,
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input wire clear_cpl_count,
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output reg pd_credit_limited = 1,
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output reg npd_credit_limited = 1,
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output reg cd_credit_limited = 1,
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input wire l0_stats_cfg_transmitted
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);
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//}}}
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//{{{ Functions, Regs, Wires, Parameters
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reg [11:0] reg_ph_alloc = 0;
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reg [11:0] reg_nph_alloc = 0;
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reg [11:0] reg_pd_alloc = 0;
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reg [11:0] reg_recvd = 0;
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reg [6:0] mgmt_stats_credit_sel_d = 0;
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wire service_stream;
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reg service_rxrcd_ch = 0;
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wire service_txcpl;
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reg service_txcon_pd = 0;
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reg service_txcon_npd = 0;
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reg service_txcon_cd = 0;
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reg service_txcon_ch = 0;
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reg service_txcon_pd_d = 0;
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reg service_txcon_npd_d = 0;
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reg service_txcon_cd_d = 0;
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reg service_txlim_ph = 0;
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reg service_txlim_nph = 0;
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reg service_txlim_ch = 0;
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reg service_txlim_pd = 0;
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reg service_txlim_npd = 0;
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reg service_txlim_cd = 0;
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reg service_txlim_ph_d = 0;
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reg service_txlim_nph_d = 0;
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reg service_txlim_ch_d = 0;
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reg service_txlim_pd_d = 0;
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reg service_txlim_npd_d = 0;
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reg service_txlim_cd_d = 0;
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reg service_rxall_ph = 0;
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reg service_rxrcd_ph = 0;
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reg service_rxall_nph = 0;
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reg service_rxrcd_nph = 0;
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reg service_rxall_pd = 0;
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reg service_rxrcd_pd = 0;
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reg service_rxall_ph_d = 0;
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reg service_rxall_nph_d = 0;
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reg service_rxall_pd_d = 0;
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reg service_rxrcd_ph_d = 0;
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reg service_rxrcd_nph_d = 0;
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reg service_rxrcd_pd_d = 0;
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reg service_rxrcd_ph_d2 = 0;
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reg service_rxrcd_nph_d2 = 0;
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reg service_rxrcd_pd_d2 = 0;
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reg trn_pfc_ph_cl_upd = 0;
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reg trn_pfc_nph_cl_upd = 0;
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reg trn_pfc_pd_cl_upd = 0;
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reg trn_pfc_npd_cl_upd = 0;
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reg trn_pfc_cpld_cl_upd = 0;
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reg pd_credit_limited_upd = 0;
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reg npd_credit_limited_upd = 0;
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reg cd_credit_limited_upd = 0;
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reg [11:0] tx_cd_credits_consumed_int = 0;
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reg [11:0] tx_cd_credits_consumed_all = 0;
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reg [11:0] tx_cd_credits_consumed_trn = 0;
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reg [11:0] tx_cd_credits_consumed_diff = 0;
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reg [11:0] l0_stats_cfg_transmitted_cnt = 0;
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reg [11:0] mgmt_stats_credit_d = 0;
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wire [7:0] cal_seq_out;
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wire [1:0] cal_tag_out;
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wire [6:0] cal_sub_seq_out;
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wire [6:0] cal_seq_init_out;
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wire [7:0] old_cal_seq_out;
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wire [1:0] old_cal_tag_out;
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wire [6:0] old_cal_sub_seq_out;
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reg [3:0] cal_addr = (C_CALENDAR_LEN - 1)%16;
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wire cal_enable;
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reg [4:0] initial_header_read_cntr = 0;
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reg initial_header_read = 1;
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integer i,j;
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assign trn_rfc_npd_av = 0;
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assign trn_rfc_cplh_av = 0;
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assign trn_rfc_cpld_av = 0;
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// ==============================
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// VC
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localparam VC0 = 2'b00;
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// ==============================
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// Channel
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localparam CREDIT_SEL_PH = 3'b000;
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localparam CREDIT_SEL_NPH = 3'b001;
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localparam CREDIT_SEL_CH = 3'b010;
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localparam CREDIT_SEL_PD = 3'b011;
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localparam CREDIT_SEL_NPD = 3'b100;
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localparam CREDIT_SEL_CD = 3'b101;
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`define CREDIT_SEL_PH 3'h0
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`define CREDIT_SEL_NPH 3'h1
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`define CREDIT_SEL_CH 3'h2
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`define CREDIT_SEL_PD 3'h3
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`define CREDIT_SEL_NPD 3'h4
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`define CREDIT_SEL_CD 3'h5
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// ==============================
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// Credit Type Information
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localparam CREDIT_TX_CONS = 2'b00;
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localparam CREDIT_TX_LIM = 2'b01;
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localparam CREDIT_RX_ALLO = 2'b10;
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localparam CREDIT_RX_RCVD = 2'b11;
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`define CREDIT_TX_CONS 3'h0
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`define CREDIT_TX_LIM 3'h1
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`define CREDIT_RX_ALLO 3'h2
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`define CREDIT_RX_RCVD 3'h3
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// ==============================
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function integer numsrl (input integer length);
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begin
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if (length%16 == 0) numsrl = length/16;
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else numsrl = (length[31:4]+1);
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end
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endfunction
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function integer parsecal (input integer index, input reg [127:0] CAL_SEQ,
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input integer CAL_LEN, input integer numsrl);
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integer g;
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begin
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for (g=0; g<numsrl*16; g=g+1)
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if (g>=CAL_LEN)
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parsecal[g] = 0;
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else
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parsecal[g] = CAL_SEQ[index + g*8];
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end
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endfunction
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function integer tagcal (input integer index, input reg [127:0] CAL_SEQ,
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input integer CAL_LEN, input integer numsrl);
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integer g;
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reg [5:0] S;
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begin
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for (g=0; g<numsrl*16; g=g+1) begin
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S[5] = CAL_SEQ[g*8+7];
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S[4] = CAL_SEQ[g*8+6];
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S[3] = CAL_SEQ[g*8+5];
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S[2] = CAL_SEQ[g*8+4];
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S[1] = CAL_SEQ[g*8+3];
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S[0] = CAL_SEQ[g*8+2];
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if (g>=CAL_LEN)
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tagcal[g] = 0;
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else if ((S[5:0] == { `CREDIT_TX_CONS , `CREDIT_SEL_PD }) ||
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(S[5:0] == { `CREDIT_TX_LIM , `CREDIT_SEL_PD }))
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tagcal[g] = 1; //PD = 11
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else if ((S[5:0] == { `CREDIT_TX_CONS , `CREDIT_SEL_NPD }) ||
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(S[5:0] == { `CREDIT_TX_LIM , `CREDIT_SEL_NPD }))
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tagcal[g] = index; //NPD = 10
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else if ((S[5:0] == { `CREDIT_TX_CONS , `CREDIT_SEL_CD }) ||
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(S[5:0] == { `CREDIT_TX_LIM , `CREDIT_SEL_CD }))
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tagcal[g] = !index; //CD = 01
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else
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tagcal[g] = 0; //everything else = 00
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end
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end
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endfunction
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//}}}
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//{{{ Instantiate SRLs for Calendar
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parameter number_srls = numsrl(C_CALENDAR_LEN);
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parameter number_srls_sub = numsrl(C_CALENDAR_SUB_LEN);
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parameter [number_srls*16-1:0] CALTAGINIT1 = tagcal(1, C_CALENDAR_SEQ,C_CALENDAR_LEN,number_srls);
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parameter [number_srls*16-1:0] CALTAGINIT0 = tagcal(0, C_CALENDAR_SEQ,C_CALENDAR_LEN,number_srls);
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parameter [number_srls*16-1:0] CALINIT7 = parsecal(7, C_CALENDAR_SEQ,C_CALENDAR_LEN,number_srls);
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parameter [number_srls*16-1:0] CALINIT6 = parsecal(6, C_CALENDAR_SEQ,C_CALENDAR_LEN,number_srls);
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parameter [number_srls*16-1:0] CALINIT5 = parsecal(5, C_CALENDAR_SEQ,C_CALENDAR_LEN,number_srls);
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parameter [number_srls*16-1:0] CALINIT4 = parsecal(4, C_CALENDAR_SEQ,C_CALENDAR_LEN,number_srls);
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parameter [number_srls*16-1:0] CALINIT3 = parsecal(3, C_CALENDAR_SEQ,C_CALENDAR_LEN,number_srls);
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parameter [number_srls*16-1:0] CALINIT2 = parsecal(2, C_CALENDAR_SEQ,C_CALENDAR_LEN,number_srls);
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|
|
parameter [number_srls_sub*16-1:0] CALSUBINIT6 = parsecal(6, C_CALENDAR_SUB_SEQ,C_CALENDAR_SUB_LEN,number_srls_sub);
|
303 |
|
|
parameter [number_srls_sub*16-1:0] CALSUBINIT5 = parsecal(5, C_CALENDAR_SUB_SEQ,C_CALENDAR_SUB_LEN,number_srls_sub);
|
304 |
|
|
parameter [number_srls_sub*16-1:0] CALSUBINIT4 = parsecal(4, C_CALENDAR_SUB_SEQ,C_CALENDAR_SUB_LEN,number_srls_sub);
|
305 |
|
|
parameter [number_srls_sub*16-1:0] CALSUBINIT3 = parsecal(3, C_CALENDAR_SUB_SEQ,C_CALENDAR_SUB_LEN,number_srls_sub);
|
306 |
|
|
parameter [number_srls_sub*16-1:0] CALSUBINIT2 = parsecal(2, C_CALENDAR_SUB_SEQ,C_CALENDAR_SUB_LEN,number_srls_sub);
|
307 |
|
|
|
308 |
|
|
parameter CAL_SUB_ADDR = (C_CALENDAR_SUB_LEN - 1)%16;
|
309 |
|
|
|
310 |
|
|
always @(posedge clk) begin
|
311 |
|
|
if (~rst_n) begin
|
312 |
|
|
cal_addr <= #`Tcq (C_CALENDAR_LEN - 1)%16;
|
313 |
|
|
end else if (!cal_enable) begin
|
314 |
|
|
cal_addr <= #`Tcq cal_addr - 1;
|
315 |
|
|
end
|
316 |
|
|
end
|
317 |
|
|
|
318 |
|
|
always @(posedge clk) begin
|
319 |
|
|
if (~rst_n) begin
|
320 |
|
|
initial_header_read <= #`Tcq 1;
|
321 |
|
|
initial_header_read_cntr <= #`Tcq 'h0;
|
322 |
|
|
end else begin
|
323 |
|
|
if (initial_header_read_cntr < 'd16) begin
|
324 |
|
|
initial_header_read_cntr <= #`Tcq initial_header_read_cntr + 1;
|
325 |
|
|
initial_header_read <= #`Tcq 1;
|
326 |
|
|
end else begin
|
327 |
|
|
initial_header_read <= #`Tcq 0;
|
328 |
|
|
end
|
329 |
|
|
end
|
330 |
|
|
end
|
331 |
|
|
|
332 |
|
|
assign cal_enable = !((!pd_credit_limited && (cal_tag_out[1:0]==2'b11)) ||
|
333 |
|
|
(!npd_credit_limited && (cal_tag_out[1:0]==2'b10) && LEGACY_EP) ||
|
334 |
|
|
(!cd_credit_limited && (cal_tag_out[1:0]==2'b01)));
|
335 |
|
|
|
336 |
|
|
assign cal_seq_out[1:0] = 2'b00;
|
337 |
|
|
assign cal_sub_seq_out[1:0] = 2'b00;
|
338 |
|
|
|
339 |
|
|
|
340 |
|
|
assign old_cal_seq_out[1:0] = 2'b00;
|
341 |
|
|
assign old_cal_sub_seq_out[1:0] = 2'b00;
|
342 |
|
|
|
343 |
|
|
|
344 |
|
|
// old SRL, left for comparison
|
345 |
|
|
//synthesis translate_off
|
346 |
|
|
genvar j_srl;
|
347 |
|
|
generate for (j_srl=0; j_srl<number_srls; j_srl=j_srl+1) begin: old_srl_gen
|
348 |
|
|
SRL16E #(.INIT(CALTAGINIT1[15:0])) srl_cal_tag1
|
349 |
|
|
(.D(old_cal_tag_out[1]),.Q(old_cal_tag_out[1]),.CLK(clk),.CE(cal_enable),
|
350 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]));
|
351 |
|
|
SRL16E #(.INIT(CALTAGINIT0[15:0])) srl_cal_tag0
|
352 |
|
|
(.D(old_cal_tag_out[0]),.Q(old_cal_tag_out[0]),.CLK(clk),.CE(cal_enable),
|
353 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]));
|
354 |
|
|
SRL16E #(.INIT(CALINIT7[15:0])) srl_cal7
|
355 |
|
|
(.D(old_cal_seq_out[7]),.Q(old_cal_seq_out[7]),.CLK(clk),.CE(cal_enable),
|
356 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]));
|
357 |
|
|
SRL16E #(.INIT(CALINIT6[15:0])) srl_cal6
|
358 |
|
|
(.D(old_cal_seq_out[6]),.Q(old_cal_seq_out[6]),.CLK(clk),.CE(cal_enable),
|
359 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]));
|
360 |
|
|
SRL16E #(.INIT(CALINIT5[15:0])) srl_cal5
|
361 |
|
|
(.D(old_cal_seq_out[5]),.Q(old_cal_seq_out[5]),.CLK(clk),.CE(cal_enable),
|
362 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]));
|
363 |
|
|
SRL16E #(.INIT(CALINIT4[15:0])) srl_cal4
|
364 |
|
|
(.D(old_cal_seq_out[4]),.Q(old_cal_seq_out[4]),.CLK(clk),.CE(cal_enable),
|
365 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]));
|
366 |
|
|
SRL16E #(.INIT(CALINIT3[15:0])) srl_cal3
|
367 |
|
|
(.D(old_cal_seq_out[3]),.Q(old_cal_seq_out[3]),.CLK(clk),.CE(cal_enable),
|
368 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]));
|
369 |
|
|
SRL16E #(.INIT(CALINIT2[15:0])) srl_cal2
|
370 |
|
|
(.D(old_cal_seq_out[2]),.Q(old_cal_seq_out[2]),.CLK(clk),.CE(cal_enable),
|
371 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]));
|
372 |
|
|
end
|
373 |
|
|
endgenerate
|
374 |
|
|
//synthesis translate_on
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
genvar i_srl;
|
378 |
|
|
generate for (i_srl=0; i_srl<number_srls; i_srl=i_srl+1) begin: srl_gen
|
379 |
|
|
my_SRL16E #(.INIT(CALTAGINIT1[15:0])) srl_cal_tag1
|
380 |
|
|
(.D(cal_tag_out[1]),.Q(cal_tag_out[1]),.CLK(clk),.CE(cal_enable & rst_n),
|
381 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]),
|
382 |
|
|
.RST_N(rst_n));
|
383 |
|
|
my_SRL16E #(.INIT(CALTAGINIT0[15:0])) srl_cal_tag0
|
384 |
|
|
(.D(cal_tag_out[0]),.Q(cal_tag_out[0]),.CLK(clk),.CE(cal_enable & rst_n),
|
385 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]),
|
386 |
|
|
.RST_N(rst_n));
|
387 |
|
|
my_SRL16E #(.INIT(CALINIT7[15:0])) srl_cal7
|
388 |
|
|
(.D(cal_seq_out[7]),.Q(cal_seq_out[7]),.CLK(clk),.CE(cal_enable & rst_n),
|
389 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]),
|
390 |
|
|
.RST_N(rst_n));
|
391 |
|
|
my_SRL16E #(.INIT(CALINIT6[15:0])) srl_cal6
|
392 |
|
|
(.D(cal_seq_out[6]),.Q(cal_seq_out[6]),.CLK(clk),.CE(cal_enable & rst_n),
|
393 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]),
|
394 |
|
|
.RST_N(rst_n));
|
395 |
|
|
my_SRL16E #(.INIT(CALINIT5[15:0])) srl_cal5
|
396 |
|
|
(.D(cal_seq_out[5]),.Q(cal_seq_out[5]),.CLK(clk),.CE(cal_enable & rst_n),
|
397 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]),
|
398 |
|
|
.RST_N(rst_n));
|
399 |
|
|
my_SRL16E #(.INIT(CALINIT4[15:0])) srl_cal4
|
400 |
|
|
(.D(cal_seq_out[4]),.Q(cal_seq_out[4]),.CLK(clk),.CE(cal_enable & rst_n),
|
401 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]),
|
402 |
|
|
.RST_N(rst_n));
|
403 |
|
|
my_SRL16E #(.INIT(CALINIT3[15:0])) srl_cal3
|
404 |
|
|
(.D(cal_seq_out[3]),.Q(cal_seq_out[3]),.CLK(clk),.CE(cal_enable & rst_n),
|
405 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]),
|
406 |
|
|
.RST_N(rst_n));
|
407 |
|
|
my_SRL16E #(.INIT(CALINIT2[15:0])) srl_cal2
|
408 |
|
|
(.D(cal_seq_out[2]),.Q(cal_seq_out[2]),.CLK(clk),.CE(cal_enable & rst_n),
|
409 |
|
|
.A3(cal_addr[3]),.A2(cal_addr[2]),.A1(cal_addr[1]),.A0(cal_addr[0]),
|
410 |
|
|
.RST_N(rst_n));
|
411 |
|
|
end
|
412 |
|
|
endgenerate
|
413 |
|
|
|
414 |
|
|
|
415 |
|
|
/*
|
416 |
|
|
0000_0000_0000_0000 6
|
417 |
|
|
|
418 |
|
|
1111_1101_1111_1011 5
|
419 |
|
|
0000_1110_0001_1100 4
|
420 |
|
|
|
421 |
|
|
0011_0000_0110_0000 3
|
422 |
|
|
0101_0110_1010_1101 2
|
423 |
|
|
OOOO_OOOO_OOOO_OOOO 1
|
424 |
|
|
OOOO_OOOO_OOOO_OOOO 0
|
425 |
|
|
|
426 |
|
|
2222 3312 2223 3122
|
427 |
|
|
048c 0440 48c0 4404
|
428 |
|
|
|
429 |
|
|
1234 5671 2345 6712
|
430 |
|
|
|
431 |
|
|
20 PHli
|
432 |
|
|
24 NPHli
|
433 |
|
|
28 CHli
|
434 |
|
|
2c PDli
|
435 |
|
|
30 PHli
|
436 |
|
|
34 CDli
|
437 |
|
|
14 ConCD
|
438 |
|
|
|
439 |
|
|
*/
|
440 |
|
|
|
441 |
|
|
assign cal_seq_init_out[6] = 0;
|
442 |
|
|
// assign cal_seq_init_out[5] = 1;
|
443 |
|
|
|
444 |
|
|
my_SRL16E #(.INIT(16'b1111_1101_1111_1011)) srl_init_cal5
|
445 |
|
|
(.D(cal_seq_init_out[5]),.Q(cal_seq_init_out[5]),.CLK(clk),.CE(1'b1),
|
446 |
|
|
.A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1), .RST_N(rst_n));
|
447 |
|
|
|
448 |
|
|
my_SRL16E #(.INIT(16'b0000_1110_0001_1100)) srl_init_cal4
|
449 |
|
|
(.D(cal_seq_init_out[4]),.Q(cal_seq_init_out[4]),.CLK(clk),.CE(1'b1),
|
450 |
|
|
.A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1), .RST_N(rst_n));
|
451 |
|
|
|
452 |
|
|
my_SRL16E #(.INIT(16'b0011_0000_0110_0000)) srl_init_cal3
|
453 |
|
|
(.D(cal_seq_init_out[3]),.Q(cal_seq_init_out[3]),.CLK(clk),.CE(1'b1),
|
454 |
|
|
.A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1), .RST_N(rst_n));
|
455 |
|
|
|
456 |
|
|
my_SRL16E #(.INIT(16'b0101_0110_1010_1101)) srl_init_cal2
|
457 |
|
|
(.D(cal_seq_init_out[2]),.Q(cal_seq_init_out[2]),.CLK(clk),.CE(1'b1),
|
458 |
|
|
.A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1), .RST_N(rst_n));
|
459 |
|
|
|
460 |
|
|
assign cal_seq_init_out[1] = 0;
|
461 |
|
|
assign cal_seq_init_out[0] = 0;
|
462 |
|
|
|
463 |
|
|
|
464 |
|
|
|
465 |
|
|
// old SRL, left for comparison
|
466 |
|
|
//synthesis translate_off
|
467 |
|
|
genvar j_ssrl;
|
468 |
|
|
generate for (j_ssrl=0; j_ssrl<number_srls_sub; j_ssrl=j_ssrl+1) begin: old_sub_srl_gen
|
469 |
|
|
|
470 |
|
|
SRL16E #(.INIT(CALSUBINIT6[15:0])) srl_sub_cal6
|
471 |
|
|
(.D(old_cal_sub_seq_out[6]),.Q(old_cal_sub_seq_out[6]),.CLK(clk),.CE(cal_seq_out[7]),
|
472 |
|
|
.A3(CAL_SUB_ADDR[3]),.A2(CAL_SUB_ADDR[2]),.A1(CAL_SUB_ADDR[1]),.A0(CAL_SUB_ADDR[0]));
|
473 |
|
|
SRL16E #(.INIT(CALSUBINIT5[15:0])) srl_sub_cal5
|
474 |
|
|
(.D(old_cal_sub_seq_out[5]),.Q(old_cal_sub_seq_out[5]),.CLK(clk),.CE(cal_seq_out[7]),
|
475 |
|
|
.A3(CAL_SUB_ADDR[3]),.A2(CAL_SUB_ADDR[2]),.A1(CAL_SUB_ADDR[1]),.A0(CAL_SUB_ADDR[0]));
|
476 |
|
|
SRL16E #(.INIT(CALSUBINIT4[15:0])) srl_sub_cal4
|
477 |
|
|
(.D(old_cal_sub_seq_out[4]),.Q(old_cal_sub_seq_out[4]),.CLK(clk),.CE(cal_seq_out[7]),
|
478 |
|
|
.A3(CAL_SUB_ADDR[3]),.A2(CAL_SUB_ADDR[2]),.A1(CAL_SUB_ADDR[1]),.A0(CAL_SUB_ADDR[0]));
|
479 |
|
|
SRL16E #(.INIT(CALSUBINIT3[15:0])) srl_sub_cal3
|
480 |
|
|
(.D(old_cal_sub_seq_out[3]),.Q(old_cal_sub_seq_out[3]),.CLK(clk),.CE(cal_seq_out[7]),
|
481 |
|
|
.A3(CAL_SUB_ADDR[3]),.A2(CAL_SUB_ADDR[2]),.A1(CAL_SUB_ADDR[1]),.A0(CAL_SUB_ADDR[0]));
|
482 |
|
|
SRL16E #(.INIT(CALSUBINIT2[15:0])) srl_sub_cal2
|
483 |
|
|
(.D(old_cal_sub_seq_out[2]),.Q(old_cal_sub_seq_out[2]),.CLK(clk),.CE(cal_seq_out[7]),
|
484 |
|
|
.A3(CAL_SUB_ADDR[3]),.A2(CAL_SUB_ADDR[2]),.A1(CAL_SUB_ADDR[1]),.A0(CAL_SUB_ADDR[0]));
|
485 |
|
|
end
|
486 |
|
|
endgenerate
|
487 |
|
|
//synthesis translate_on
|
488 |
|
|
|
489 |
|
|
|
490 |
|
|
|
491 |
|
|
genvar i_ssrl;
|
492 |
|
|
generate for (i_ssrl=0; i_ssrl<number_srls_sub; i_ssrl=i_ssrl+1) begin: sub_srl_gen
|
493 |
|
|
my_SRL16E #(.INIT(CALSUBINIT6[15:0])) srl_sub_cal6
|
494 |
|
|
(.D(cal_sub_seq_out[6]),.Q(cal_sub_seq_out[6]),.CLK(clk),.CE(cal_seq_out[7] & rst_n),
|
495 |
|
|
.A3(CAL_SUB_ADDR[3]),.A2(CAL_SUB_ADDR[2]),.A1(CAL_SUB_ADDR[1]),.A0(CAL_SUB_ADDR[0]), .RST_N(rst_n));
|
496 |
|
|
my_SRL16E #(.INIT(CALSUBINIT5[15:0])) srl_sub_cal5
|
497 |
|
|
(.D(cal_sub_seq_out[5]),.Q(cal_sub_seq_out[5]),.CLK(clk),.CE(cal_seq_out[7] & rst_n),
|
498 |
|
|
.A3(CAL_SUB_ADDR[3]),.A2(CAL_SUB_ADDR[2]),.A1(CAL_SUB_ADDR[1]),.A0(CAL_SUB_ADDR[0]), .RST_N(rst_n));
|
499 |
|
|
my_SRL16E #(.INIT(CALSUBINIT4[15:0])) srl_sub_cal4
|
500 |
|
|
(.D(cal_sub_seq_out[4]),.Q(cal_sub_seq_out[4]),.CLK(clk),.CE(cal_seq_out[7] & rst_n),
|
501 |
|
|
.A3(CAL_SUB_ADDR[3]),.A2(CAL_SUB_ADDR[2]),.A1(CAL_SUB_ADDR[1]),.A0(CAL_SUB_ADDR[0]), .RST_N(rst_n));
|
502 |
|
|
my_SRL16E #(.INIT(CALSUBINIT3[15:0])) srl_sub_cal3
|
503 |
|
|
(.D(cal_sub_seq_out[3]),.Q(cal_sub_seq_out[3]),.CLK(clk),.CE(cal_seq_out[7] & rst_n),
|
504 |
|
|
.A3(CAL_SUB_ADDR[3]),.A2(CAL_SUB_ADDR[2]),.A1(CAL_SUB_ADDR[1]),.A0(CAL_SUB_ADDR[0]), .RST_N(rst_n));
|
505 |
|
|
my_SRL16E #(.INIT(CALSUBINIT2[15:0])) srl_sub_cal2
|
506 |
|
|
(.D(cal_sub_seq_out[2]),.Q(cal_sub_seq_out[2]),.CLK(clk),.CE(cal_seq_out[7] & rst_n),
|
507 |
|
|
.A3(CAL_SUB_ADDR[3]),.A2(CAL_SUB_ADDR[2]),.A1(CAL_SUB_ADDR[1]),.A0(CAL_SUB_ADDR[0]), .RST_N(rst_n));
|
508 |
|
|
end
|
509 |
|
|
endgenerate
|
510 |
|
|
|
511 |
|
|
|
512 |
|
|
|
513 |
|
|
//}}}
|
514 |
|
|
//{{{ Parse Calendar & Trigger for Service of Streaming or Tx Cpl Credit Data
|
515 |
|
|
always @(posedge clk) begin
|
516 |
|
|
if (~rst_n || trn_lnk_up_n) begin
|
517 |
|
|
mgmt_stats_credit_sel <= #`Tcq 'h0;
|
518 |
|
|
mgmt_stats_credit_sel_d <= #`Tcq 'h0;
|
519 |
|
|
service_rxall_ph <= #`Tcq 1'b0;
|
520 |
|
|
service_rxall_nph <= #`Tcq 1'b0;
|
521 |
|
|
service_rxall_pd <= #`Tcq 1'b0;
|
522 |
|
|
service_rxrcd_ph <= #`Tcq 1'b0;
|
523 |
|
|
service_rxrcd_nph <= #`Tcq 1'b0;
|
524 |
|
|
service_rxrcd_ch <= #`Tcq 1'b0;
|
525 |
|
|
service_rxrcd_pd <= #`Tcq 1'b0;
|
526 |
|
|
service_txcon_ch <= #`Tcq 1'b0;
|
527 |
|
|
service_txcon_pd <= #`Tcq 1'b0;
|
528 |
|
|
service_txcon_npd <= #`Tcq 1'b0;
|
529 |
|
|
service_txcon_cd <= #`Tcq 1'b0;
|
530 |
|
|
service_txlim_ph <= #`Tcq 1'b0;
|
531 |
|
|
service_txlim_nph <= #`Tcq 1'b0;
|
532 |
|
|
service_txlim_ch <= #`Tcq 1'b0;
|
533 |
|
|
service_txlim_pd <= #`Tcq 1'b0;
|
534 |
|
|
service_txlim_npd <= #`Tcq 1'b0;
|
535 |
|
|
service_txlim_cd <= #`Tcq 1'b0;
|
536 |
|
|
end else begin
|
537 |
|
|
// mgmt_stats_credit_sel <= #`Tcq {(cal_seq_out[7] || initial_header_read )? cal_sub_seq_out[6:2]:cal_seq_out[6:2], VC0};
|
538 |
|
|
|
539 |
|
|
mgmt_stats_credit_sel <= #`Tcq {initial_header_read ? cal_seq_init_out[6:2] : cal_seq_out[7] ? cal_sub_seq_out[6:2] : cal_seq_out[6:2], VC0};
|
540 |
|
|
|
541 |
|
|
mgmt_stats_credit_sel_d <= #`Tcq mgmt_stats_credit_sel;
|
542 |
|
|
service_rxall_ph <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_RX_ALLO,CREDIT_SEL_PH}; //0x40
|
543 |
|
|
service_rxall_nph <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_RX_ALLO,CREDIT_SEL_NPH};//0x44
|
544 |
|
|
service_rxall_pd <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_RX_ALLO,CREDIT_SEL_PD}; //0x4C
|
545 |
|
|
service_rxrcd_ph <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_RX_RCVD,CREDIT_SEL_PH}; //0x60
|
546 |
|
|
service_rxrcd_nph <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_RX_RCVD,CREDIT_SEL_NPH};//0x64
|
547 |
|
|
service_rxrcd_ch <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_RX_RCVD,CREDIT_SEL_CH}; //0x68 (streaming)
|
548 |
|
|
service_rxrcd_pd <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_RX_RCVD,CREDIT_SEL_PD}; //0x6C
|
549 |
|
|
service_txcon_ch <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_TX_CONS,CREDIT_SEL_CH}; //0x08 (tx cpl fix)
|
550 |
|
|
service_txcon_pd <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_TX_CONS,CREDIT_SEL_PD}; //0x0C (tx PDcredit fix2)
|
551 |
|
|
service_txcon_npd <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_TX_CONS,CREDIT_SEL_NPD};//0x10 (tx NPDcredit fix2)
|
552 |
|
|
service_txcon_cd <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_TX_CONS,CREDIT_SEL_CD}; //0x14 (tx CDcredit fix2)
|
553 |
|
|
service_txlim_ph <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_TX_LIM, CREDIT_SEL_PH}; //0x20
|
554 |
|
|
service_txlim_nph <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_TX_LIM, CREDIT_SEL_NPH};//0x24
|
555 |
|
|
service_txlim_ch <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_TX_LIM, CREDIT_SEL_CH}; //0x28
|
556 |
|
|
service_txlim_pd <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_TX_LIM, CREDIT_SEL_PD}; //0x2C (tx PDcredit fix1)
|
557 |
|
|
service_txlim_npd <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_TX_LIM, CREDIT_SEL_NPD};//0x30 (tx NPDcredit fix1)
|
558 |
|
|
service_txlim_cd <= #`Tcq mgmt_stats_credit_sel_d[6:2] == {CREDIT_TX_LIM, CREDIT_SEL_CD}; //0x34 (tx CDcredit fix1)
|
559 |
|
|
end
|
560 |
|
|
end
|
561 |
|
|
|
562 |
|
|
assign service_stream = service_rxrcd_ch;
|
563 |
|
|
assign service_txcpl = service_txcon_ch;
|
564 |
|
|
//}}}
|
565 |
|
|
//{{{ Capture Credit Data for Streaming Mode
|
566 |
|
|
always @(posedge clk) begin
|
567 |
|
|
if (~rst_n) begin
|
568 |
|
|
rx_ch_credits_received <= #`Tcq 0;
|
569 |
|
|
rx_ch_credits_received_inc <= #`Tcq 0;
|
570 |
|
|
// requested CplH-rcvd when service_stream=1
|
571 |
|
|
// wait 2 cycles for data
|
572 |
|
|
end else if (service_stream) begin
|
573 |
|
|
rx_ch_credits_received <= #`Tcq mgmt_stats_credit[7:0];
|
574 |
|
|
rx_ch_credits_received_inc <= #`Tcq (mgmt_stats_credit[7:0] != rx_ch_credits_received);
|
575 |
|
|
end else begin
|
576 |
|
|
rx_ch_credits_received_inc <= #`Tcq 0;
|
577 |
|
|
end
|
578 |
|
|
end
|
579 |
|
|
//}}}
|
580 |
|
|
//{{{ Capture Credit Data for Tx Cpl Issue
|
581 |
|
|
always @(posedge clk) begin
|
582 |
|
|
if (~rst_n) begin
|
583 |
|
|
tx_ch_credits_consumed <= #`Tcq 0;
|
584 |
|
|
end else if (service_txcpl) begin
|
585 |
|
|
tx_ch_credits_consumed <= #`Tcq mgmt_stats_credit[7:0];
|
586 |
|
|
end
|
587 |
|
|
end
|
588 |
|
|
//}}}
|
589 |
|
|
//{{{ Capture Credit Data for Tx Blocking Data Credit Issue
|
590 |
|
|
always @(posedge clk) begin
|
591 |
|
|
if (~rst_n) begin
|
592 |
|
|
service_txcon_pd_d <= #`Tcq 0;
|
593 |
|
|
service_txcon_npd_d <= #`Tcq 0;
|
594 |
|
|
service_txcon_cd_d <= #`Tcq 0;
|
595 |
|
|
tx_pd_credits_consumed <= #`Tcq 0;
|
596 |
|
|
tx_pd_credits_available <= #`Tcq 0;
|
597 |
|
|
tx_npd_credits_consumed <= #`Tcq 0;
|
598 |
|
|
tx_npd_credits_available <= #`Tcq 0;
|
599 |
|
|
tx_cd_credits_consumed_all <= #`Tcq 0;
|
600 |
|
|
tx_cd_credits_consumed_trn <= #`Tcq 0;
|
601 |
|
|
tx_cd_credits_consumed_int <= #`Tcq 0;
|
602 |
|
|
tx_cd_credits_consumed_diff <= #`Tcq 'h0;
|
603 |
|
|
tx_cd_credits_available <= #`Tcq 0;
|
604 |
|
|
l0_stats_cfg_transmitted_cnt <= #`Tcq 'h0;
|
605 |
|
|
end else begin
|
606 |
|
|
service_txcon_pd_d <= #`Tcq service_txcon_pd;
|
607 |
|
|
service_txcon_npd_d <= #`Tcq service_txcon_npd;
|
608 |
|
|
service_txcon_cd_d <= #`Tcq service_txcon_cd;
|
609 |
|
|
if (service_txcon_pd_d) begin
|
610 |
|
|
tx_pd_credits_consumed <= #`Tcq mgmt_stats_credit_d[11:0];
|
611 |
|
|
tx_pd_credits_available <= #`Tcq trn_pfc_pd_cl - mgmt_stats_credit_d[11:0];
|
612 |
|
|
end
|
613 |
|
|
if (LEGACY_EP && service_txcon_npd_d) begin
|
614 |
|
|
tx_npd_credits_consumed <= #`Tcq mgmt_stats_credit_d[11:0];
|
615 |
|
|
tx_npd_credits_available <= #`Tcq trn_pfc_npd_cl - mgmt_stats_credit_d[11:0];
|
616 |
|
|
end
|
617 |
|
|
if (service_txcon_cd_d) begin
|
618 |
|
|
tx_cd_credits_consumed_int <= #`Tcq mgmt_stats_credit_d[11:0];
|
619 |
|
|
tx_cd_credits_consumed_diff<= #`Tcq mgmt_stats_credit_d[11:0] - tx_cd_credits_consumed_int;
|
620 |
|
|
tx_cd_credits_available <= #`Tcq trn_pfc_cpld_cl - mgmt_stats_credit_d[11:0];
|
621 |
|
|
end else begin
|
622 |
|
|
tx_cd_credits_consumed_diff<= #`Tcq 'h0;
|
623 |
|
|
end
|
624 |
|
|
tx_cd_credits_consumed_all <= #`Tcq tx_cd_credits_consumed_all + tx_cd_credits_consumed_diff;
|
625 |
|
|
tx_cd_credits_consumed_trn <= #`Tcq tx_cd_credits_consumed_all - l0_stats_cfg_transmitted_cnt;
|
626 |
|
|
if (clear_cpl_count)
|
627 |
|
|
l0_stats_cfg_transmitted_cnt <= #`Tcq 0;
|
628 |
|
|
else
|
629 |
|
|
l0_stats_cfg_transmitted_cnt <= #`Tcq l0_stats_cfg_transmitted_cnt + l0_stats_cfg_transmitted;
|
630 |
|
|
end
|
631 |
|
|
end
|
632 |
|
|
|
633 |
|
|
assign tx_cd_credits_consumed = tx_cd_credits_consumed_all;
|
634 |
|
|
|
635 |
|
|
//}}}
|
636 |
|
|
//{{{ Capture Credit Data for RFC
|
637 |
|
|
always @(posedge clk) begin
|
638 |
|
|
if (~rst_n) begin
|
639 |
|
|
service_rxall_ph_d <= #`Tcq 0;
|
640 |
|
|
service_rxall_nph_d <= #`Tcq 0;
|
641 |
|
|
service_rxall_pd_d <= #`Tcq 0;
|
642 |
|
|
service_rxrcd_ph_d <= #`Tcq 0;
|
643 |
|
|
service_rxrcd_nph_d <= #`Tcq 0;
|
644 |
|
|
service_rxrcd_pd_d <= #`Tcq 0;
|
645 |
|
|
service_rxrcd_ph_d2 <= #`Tcq 0;
|
646 |
|
|
service_rxrcd_nph_d2<= #`Tcq 0;
|
647 |
|
|
service_rxrcd_pd_d2 <= #`Tcq 0;
|
648 |
|
|
reg_ph_alloc <= #`Tcq 0;
|
649 |
|
|
reg_nph_alloc <= #`Tcq 0;
|
650 |
|
|
reg_pd_alloc <= #`Tcq 0;
|
651 |
|
|
reg_recvd <= #`Tcq 0;
|
652 |
|
|
trn_rfc_ph_av <= #`Tcq 0;
|
653 |
|
|
trn_rfc_nph_av <= #`Tcq 0;
|
654 |
|
|
trn_rfc_pd_av <= #`Tcq 0;
|
655 |
|
|
end else begin
|
656 |
|
|
service_rxall_ph_d <= #`Tcq service_rxall_ph;
|
657 |
|
|
service_rxall_nph_d <= #`Tcq service_rxall_nph;
|
658 |
|
|
service_rxall_pd_d <= #`Tcq service_rxall_pd;
|
659 |
|
|
service_rxrcd_ph_d <= #`Tcq service_rxrcd_ph;
|
660 |
|
|
service_rxrcd_nph_d <= #`Tcq service_rxrcd_nph;
|
661 |
|
|
service_rxrcd_pd_d <= #`Tcq service_rxrcd_pd;
|
662 |
|
|
service_rxrcd_ph_d2 <= #`Tcq service_rxrcd_ph_d;
|
663 |
|
|
service_rxrcd_nph_d2<= #`Tcq service_rxrcd_nph_d;
|
664 |
|
|
service_rxrcd_pd_d2 <= #`Tcq service_rxrcd_pd_d;
|
665 |
|
|
if (service_rxall_ph_d)
|
666 |
|
|
reg_ph_alloc <= #`Tcq mgmt_stats_credit_d;
|
667 |
|
|
if (service_rxall_nph_d)
|
668 |
|
|
reg_nph_alloc <= #`Tcq mgmt_stats_credit_d;
|
669 |
|
|
if (service_rxall_pd_d)
|
670 |
|
|
reg_pd_alloc <= #`Tcq mgmt_stats_credit_d;
|
671 |
|
|
if (service_rxrcd_ph_d || service_rxrcd_nph_d || service_rxrcd_pd_d)
|
672 |
|
|
reg_recvd <= #`Tcq mgmt_stats_credit_d;
|
673 |
|
|
if (service_rxrcd_ph_d2)
|
674 |
|
|
trn_rfc_ph_av <= #`Tcq reg_ph_alloc - reg_recvd;
|
675 |
|
|
if (service_rxrcd_nph_d2)
|
676 |
|
|
trn_rfc_nph_av <= #`Tcq reg_nph_alloc - reg_recvd;
|
677 |
|
|
if (service_rxrcd_pd_d2)
|
678 |
|
|
trn_rfc_pd_av <= #`Tcq reg_pd_alloc - reg_recvd;
|
679 |
|
|
end
|
680 |
|
|
end
|
681 |
|
|
|
682 |
|
|
//}}}
|
683 |
|
|
|
684 |
|
|
always @(posedge clk) begin
|
685 |
|
|
if (~rst_n) begin
|
686 |
|
|
mgmt_stats_credit_d <= #`Tcq 'h0;
|
687 |
|
|
service_txlim_ph_d <= #`Tcq 1'b0;
|
688 |
|
|
service_txlim_nph_d <= #`Tcq 1'b0;
|
689 |
|
|
service_txlim_ch_d <= #`Tcq 1'b0;
|
690 |
|
|
service_txlim_pd_d <= #`Tcq 1'b0;
|
691 |
|
|
service_txlim_npd_d <= #`Tcq 1'b0;
|
692 |
|
|
service_txlim_cd_d <= #`Tcq 1'b0;
|
693 |
|
|
trn_pfc_ph_cl <= #`Tcq 'h0;
|
694 |
|
|
trn_pfc_nph_cl <= #`Tcq 'h0;
|
695 |
|
|
trn_pfc_cplh_cl <= #`Tcq 'h0;
|
696 |
|
|
trn_pfc_pd_cl <= #`Tcq 'h0;
|
697 |
|
|
trn_pfc_npd_cl <= #`Tcq 'h0;
|
698 |
|
|
trn_pfc_cpld_cl <= #`Tcq 'h0;
|
699 |
|
|
trn_pfc_ph_cl_upd <= #`Tcq 1'b0;
|
700 |
|
|
trn_pfc_nph_cl_upd <= #`Tcq 1'b0;
|
701 |
|
|
trn_pfc_cplh_cl_upd <= #`Tcq 1'b0;
|
702 |
|
|
trn_pfc_pd_cl_upd <= #`Tcq 1'b0;
|
703 |
|
|
trn_pfc_npd_cl_upd <= #`Tcq 1'b0;
|
704 |
|
|
trn_pfc_cpld_cl_upd <= #`Tcq 1'b0;
|
705 |
|
|
end else begin
|
706 |
|
|
mgmt_stats_credit_d <= #`Tcq mgmt_stats_credit;
|
707 |
|
|
service_txlim_ph_d <= #`Tcq service_txlim_ph;
|
708 |
|
|
service_txlim_nph_d <= #`Tcq service_txlim_nph;
|
709 |
|
|
service_txlim_ch_d <= #`Tcq service_txlim_ch;
|
710 |
|
|
service_txlim_pd_d <= #`Tcq service_txlim_pd;
|
711 |
|
|
service_txlim_npd_d <= #`Tcq service_txlim_npd;
|
712 |
|
|
service_txlim_cd_d <= #`Tcq service_txlim_cd;
|
713 |
|
|
if (service_txlim_ph_d) begin
|
714 |
|
|
trn_pfc_ph_cl <= #`Tcq mgmt_stats_credit_d[7:0];
|
715 |
|
|
trn_pfc_ph_cl_upd <= #`Tcq 1'b1;
|
716 |
|
|
end
|
717 |
|
|
if (service_txlim_nph_d) begin
|
718 |
|
|
trn_pfc_nph_cl <= #`Tcq mgmt_stats_credit_d[7:0];
|
719 |
|
|
trn_pfc_nph_cl_upd <= #`Tcq 1'b1;
|
720 |
|
|
end
|
721 |
|
|
if (service_txlim_ch_d) begin
|
722 |
|
|
trn_pfc_cplh_cl <= #`Tcq mgmt_stats_credit_d[7:0];
|
723 |
|
|
trn_pfc_cplh_cl_upd <= #`Tcq 1'b1;
|
724 |
|
|
end
|
725 |
|
|
if (service_txlim_pd_d) begin
|
726 |
|
|
trn_pfc_pd_cl <= #`Tcq (mgmt_stats_credit_d[11:0] == 0) ? 12'hfff :
|
727 |
|
|
mgmt_stats_credit_d[11:0];
|
728 |
|
|
trn_pfc_pd_cl_upd <= #`Tcq 1'b1;
|
729 |
|
|
end
|
730 |
|
|
if (service_txlim_npd_d) begin
|
731 |
|
|
trn_pfc_npd_cl <= #`Tcq (mgmt_stats_credit_d[11:0] == 0) ? 12'hfff :
|
732 |
|
|
mgmt_stats_credit_d[11:0];
|
733 |
|
|
trn_pfc_npd_cl_upd <= #`Tcq 1'b1;
|
734 |
|
|
end
|
735 |
|
|
if (service_txlim_cd_d) begin
|
736 |
|
|
trn_pfc_cpld_cl <= #`Tcq mgmt_stats_credit_d[11:0];
|
737 |
|
|
trn_pfc_cpld_cl_upd <= #`Tcq 1'b1;
|
738 |
|
|
end
|
739 |
|
|
end
|
740 |
|
|
end
|
741 |
|
|
|
742 |
|
|
|
743 |
|
|
always @(posedge clk) begin
|
744 |
|
|
if (~rst_n) begin
|
745 |
|
|
pd_credit_limited <= #`Tcq 1'b1; //assume restricted until find out otherwise
|
746 |
|
|
npd_credit_limited <= #`Tcq 1'b1; //assume restricted until find out otherwise
|
747 |
|
|
cd_credit_limited <= #`Tcq 1'b1; //assume restricted until find out otherwise
|
748 |
|
|
pd_credit_limited_upd <= #`Tcq 1'b0;
|
749 |
|
|
npd_credit_limited_upd <= #`Tcq 1'b0;
|
750 |
|
|
cd_credit_limited_upd <= #`Tcq 1'b0;
|
751 |
|
|
end else begin
|
752 |
|
|
if (!pd_credit_limited_upd && trn_pfc_ph_cl_upd && trn_pfc_pd_cl_upd) begin
|
753 |
|
|
pd_credit_limited <= #`Tcq trn_pfc_pd_cl < (trn_pfc_ph_cl*8*(2**MPS));
|
754 |
|
|
pd_credit_limited_upd <= #`Tcq 1'b1;
|
755 |
|
|
end
|
756 |
|
|
if (!npd_credit_limited_upd && trn_pfc_nph_cl_upd && trn_pfc_npd_cl_upd) begin
|
757 |
|
|
npd_credit_limited <= #`Tcq (trn_pfc_npd_cl < trn_pfc_nph_cl) && LEGACY_EP;
|
758 |
|
|
npd_credit_limited_upd <= #`Tcq 1'b1;
|
759 |
|
|
end
|
760 |
|
|
if (!cd_credit_limited_upd && trn_pfc_cplh_cl_upd && trn_pfc_cpld_cl_upd) begin
|
761 |
|
|
cd_credit_limited <= #`Tcq trn_pfc_cpld_cl < (trn_pfc_cplh_cl*8*(2**MPS));
|
762 |
|
|
cd_credit_limited_upd <= #`Tcq 1'b1;
|
763 |
|
|
end
|
764 |
|
|
end
|
765 |
|
|
end
|
766 |
|
|
|
767 |
|
|
//{{{ Assertions
|
768 |
|
|
`ifdef SV
|
769 |
|
|
//synthesis translate_off
|
770 |
|
|
ASSERT_DETECT_POSTED_LIMITED: assert property (@(posedge clk)
|
771 |
|
|
rst_n[*256] |-> (BFM_INIT_FC_PH<BFM_INIT_FC_PD*8*(MPS+1)) ? pd_credit_limited : ~pd_credit_limited
|
772 |
|
|
) else $fatal;
|
773 |
|
|
ASSERT_DETECT_NONPOSTED_LIMITED: assert property (@(posedge clk)
|
774 |
|
|
rst_n[*256] |-> ((BFM_INIT_FC_NPH<BFM_INIT_FC_NPD)&&LEGACY_EP) ? npd_credit_limited : ~npd_credit_limited
|
775 |
|
|
) else $fatal;
|
776 |
|
|
ASSERT_DETECT_COMPLETION_LIMITED: assert property (@(posedge clk)
|
777 |
|
|
rst_n[*256] |-> (BFM_INIT_FC_CPLH<BFM_INIT_FC_CPLD*8*(MPS+1)) ? cd_credit_limited : ~cd_credit_limited
|
778 |
|
|
) else $fatal;
|
779 |
|
|
ASSERT_POSTED_LIMITED_POLL1: assert property (@(posedge clk)
|
780 |
|
|
rst_n[*256] ##1 pd_credit_limited |-> ##[1:16] (mgmt_stats_credit_sel == 7'h2C)
|
781 |
|
|
) else $fatal;
|
782 |
|
|
ASSERT_POSTED_LIMITED_POLL2: assert property (@(posedge clk)
|
783 |
|
|
rst_n[*256] ##1 pd_credit_limited |-> ##[1:16] (mgmt_stats_credit_sel == 7'h0C)
|
784 |
|
|
) else $fatal;
|
785 |
|
|
ASSERT_POSTED_NOT_LIMITED_POLL: assert property (@(posedge clk)
|
786 |
|
|
rst_n[*256] ##1 ((cal_seq_out[6:0]==7'h2C) || (cal_seq_out[6:0]==7'h0C))|-> pd_credit_limited
|
787 |
|
|
) else $fatal;
|
788 |
|
|
ASSERT_NONPOSTED_LIMITED_POLL1: assert property (@(posedge clk)
|
789 |
|
|
rst_n[*256] ##1 npd_credit_limited |-> ##[1:16] (mgmt_stats_credit_sel == 7'h30)
|
790 |
|
|
) else $fatal;
|
791 |
|
|
ASSERT_NONPOSTED_LIMITED_POLL2: assert property (@(posedge clk)
|
792 |
|
|
rst_n[*256] ##1 npd_credit_limited |-> ##[1:16] (mgmt_stats_credit_sel == 7'h10)
|
793 |
|
|
) else $fatal;
|
794 |
|
|
ASSERT_NONPOSTED_NOT_LIMITED_POLL:assert property (@(posedge clk)
|
795 |
|
|
rst_n[*256] ##1 ((cal_seq_out[6:0]==7'h30) || (cal_seq_out[6:0]==7'h10))|-> npd_credit_limited
|
796 |
|
|
) else $fatal;
|
797 |
|
|
ASSERT_COMPLETION_LIMITED_POLL1: assert property (@(posedge clk)
|
798 |
|
|
rst_n[*256] ##1 cd_credit_limited |-> ##[1:16] (mgmt_stats_credit_sel == 7'h34)
|
799 |
|
|
) else $fatal;
|
800 |
|
|
ASSERT_COMPLETION_LIMITED_POLL2: assert property (@(posedge clk)
|
801 |
|
|
rst_n[*256] ##1 cd_credit_limited |-> ##[1:16] (mgmt_stats_credit_sel == 7'h14)
|
802 |
|
|
) else $fatal;
|
803 |
|
|
ASSERT_COMPLETION_NOT_LIMITED_POLL:assert property (@(posedge clk)
|
804 |
|
|
rst_n[*256] ##1 ((cal_seq_out[6:0]==7'h34) || (cal_seq_out[6:0]==7'h14))|-> cd_credit_limited
|
805 |
|
|
) else $fatal;
|
806 |
|
|
ASSERT_NEVER_POLL_ZEROS: assert property (@(posedge clk) //assume we never poll 00
|
807 |
|
|
rst_n |-> ##1 (mgmt_stats_credit_sel != 7'h00)
|
808 |
|
|
) else $fatal;
|
809 |
|
|
ASSERT_NEVER_POLL_X_S: assert property (@(posedge clk)
|
810 |
|
|
rst_n |-> ((^mgmt_stats_credit_sel) == 1'b0) || ((^mgmt_stats_credit_sel) == 1'b1)
|
811 |
|
|
) else $fatal;
|
812 |
|
|
|
813 |
|
|
ASSERT_MATCH_CAL_TAG : assert property (@(posedge clk)
|
814 |
|
|
rst_n |-> ##1 (old_cal_tag_out == cal_tag_out)) else $fatal;
|
815 |
|
|
|
816 |
|
|
ASSERT_MATCH_CAL_SEQ : assert property (@(posedge clk)
|
817 |
|
|
rst_n |-> ##1 (old_cal_seq_out == cal_seq_out)) else $fatal;
|
818 |
|
|
|
819 |
|
|
ASSERT_MATCH_CAL_SUB_SEQ : assert property (@(posedge clk)
|
820 |
|
|
rst_n |-> ##1 (old_cal_sub_seq_out == cal_sub_seq_out)) else $fatal;
|
821 |
|
|
|
822 |
|
|
|
823 |
|
|
|
824 |
|
|
|
825 |
|
|
//synthesis translate_on
|
826 |
|
|
`endif
|
827 |
|
|
//}}}
|
828 |
|
|
|
829 |
|
|
endmodule // pcie_blk_ll_credit
|
830 |
|
|
|
831 |
|
|
|
832 |
|
|
module my_SRL16E #(
|
833 |
|
|
parameter INIT = 16'h0000
|
834 |
|
|
)(
|
835 |
|
|
output Q,
|
836 |
|
|
input A0,
|
837 |
|
|
input A1,
|
838 |
|
|
input A2,
|
839 |
|
|
input A3,
|
840 |
|
|
input CE,
|
841 |
|
|
input CLK,
|
842 |
|
|
input RST_N,
|
843 |
|
|
input D
|
844 |
|
|
);
|
845 |
|
|
|
846 |
|
|
reg [15:0] data = INIT;
|
847 |
|
|
|
848 |
|
|
assign Q = data[{A3, A2, A1, A0}];
|
849 |
|
|
|
850 |
|
|
always @(posedge CLK)
|
851 |
|
|
begin
|
852 |
|
|
if (RST_N == 1'b0)
|
853 |
|
|
{data[15:0]} <= #1 INIT;
|
854 |
|
|
else
|
855 |
|
|
if (CE == 1'b1) begin
|
856 |
|
|
{data[15:0]} <= #1 {data[14:0], D};
|
857 |
|
|
end
|
858 |
|
|
|
859 |
|
|
end
|
860 |
|
|
|
861 |
|
|
|
862 |
|
|
endmodule
|
863 |
|
|
|
864 |
|
|
|