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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : pcie_blk_ll_tx_arb.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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/*****************************************************************************
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* Description : PCIe Block Plus Tx Arbiter - multiplexes input to the
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* PCIE Block between the user input and bridge-generated traffic (such
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* as interrupts and config TLPs)
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****************************************************************************/
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`timescale 1ns/1ns
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`ifndef TCQ
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`define TCQ 1
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`endif
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module pcie_blk_ll_tx_arb
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(
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// Clock and reset
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input clk,
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input rst_n,
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// Transaction Link Up
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// input trn_lnk_up_n, // Might need this for discontinue
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// Tx Bridge Ports
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output reg [63:0] tx_td,
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output reg tx_sof_n,
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output reg tx_eof_n,
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output [7:0] tx_rem_n,
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output reg tx_src_dsc_n = 1'b1,
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output reg tx_src_rdy_n = 1'b1,
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input tx_dst_rdy_n,
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// User (TRN) Tx Ports
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input [63:0] trn_td,
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input [7:0] trn_trem_n,
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input trn_tsof_n,
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input trn_teof_n,
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input trn_tsrc_rdy_n,
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input trn_tsrc_dsc_n,
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output reg trn_tdst_rdy_n = 1'b1,
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output trn_tdst_dsc_n,
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// Config Tx Ports
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input [63:0] cfg_tx_td,
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input cfg_tx_rem_n,
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input cfg_tx_sof_n,
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input cfg_tx_eof_n,
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input cfg_tx_src_rdy_n,
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output reg cfg_tx_dst_rdy_n = 1'b1
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);
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reg cfg_in_pkt = 1'b0;
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reg usr_in_pkt = 1'b0;
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wire cfg_start;
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wire cfg_done;
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wire usr_start;
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wire usr_done;
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wire usr_in_pkt_inc; // Inclusive of SOF cycle
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reg [63:0] buf_td;
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reg buf_sof_n;
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reg buf_eof_n;
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reg buf_dsc_n = 1'b1;
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reg buf_rem_n;
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reg buf_vld = 1'b0;
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wire buf_divert;
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wire buf_rd;
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wire buf_filling;
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reg tx_rem_n_bit;
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// Assign static output to undriven signals
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assign trn_tdst_dsc_n = 1'b1; // FIXME do we need to do something with this?
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// Generate enables (dst_rdy)
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// NOTE this will insert a cycle switching cfg->usr; it is unavoidable
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// if we want to allow back-to-back TLPs from the CFG input
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always @(posedge clk) begin
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if (!rst_n) begin
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trn_tdst_rdy_n <= #`TCQ 1'b1;
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cfg_tx_dst_rdy_n <= #`TCQ 1'b1;
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end else begin
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if (cfg_in_pkt || ((!usr_in_pkt_inc || usr_done) &&
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!cfg_tx_src_rdy_n)) begin
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cfg_tx_dst_rdy_n <= #`TCQ ((buf_vld && !buf_rd) || buf_filling);
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trn_tdst_rdy_n <= #`TCQ 1'b1;
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end else begin
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cfg_tx_dst_rdy_n <= #`TCQ 1'b1;
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trn_tdst_rdy_n <= #`TCQ ((buf_vld && !buf_rd) || buf_filling);
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end
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end
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end
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assign usr_start = !trn_tdst_rdy_n && !trn_tsrc_rdy_n && !trn_tsof_n;
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assign usr_done = !trn_tdst_rdy_n && !trn_tsrc_rdy_n &&
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(!trn_teof_n || !trn_tsrc_dsc_n);
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assign usr_in_pkt_inc = usr_in_pkt ||
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(!trn_tdst_rdy_n && !trn_tsrc_rdy_n && !trn_tsof_n);
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assign cfg_start = !cfg_tx_dst_rdy_n && !cfg_tx_src_rdy_n && !cfg_tx_sof_n;
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assign cfg_done = !cfg_tx_dst_rdy_n && !cfg_tx_src_rdy_n && !cfg_tx_eof_n;
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// Create usr_in_pkt and cfg_in_pkt
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always @(posedge clk) begin
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if (!rst_n) begin
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usr_in_pkt <= #`TCQ 1'b0;
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cfg_in_pkt <= #`TCQ 1'b0;
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end else begin
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if (usr_start) begin
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usr_in_pkt <= #`TCQ 1'b1;
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end else if (usr_done) begin
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usr_in_pkt <= #`TCQ 1'b0;
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end
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if (cfg_start) begin
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cfg_in_pkt <= #`TCQ 1'b1;
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end else if (cfg_done) begin
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cfg_in_pkt <= #`TCQ 1'b0;
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end
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end
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end
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// Input shunt buffer - absorb one cycle of data to decouple
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// trn_tdst_rdy_n from other signals (and therefore make it a
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// registered output)
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always @(posedge clk) begin
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if (!rst_n) begin
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buf_vld <= #`TCQ 1'b0;
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end else begin
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if (!trn_tdst_rdy_n && !trn_tsrc_rdy_n && buf_divert) begin
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buf_td <= #`TCQ trn_td;
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buf_sof_n <= #`TCQ trn_tsof_n;
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buf_eof_n <= #`TCQ trn_teof_n && trn_tsrc_dsc_n;
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buf_dsc_n <= #`TCQ trn_tsrc_dsc_n;
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buf_rem_n <= #`TCQ trn_trem_n[0];
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// Prevent user-data outside of a packet (data after EOF and before
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// SOF) from being accepted by the core by masking with usr_in_pkt_inc
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buf_vld <= #`TCQ usr_in_pkt_inc;
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end else if (!cfg_tx_dst_rdy_n && !cfg_tx_src_rdy_n && buf_divert) begin
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buf_td <= #`TCQ cfg_tx_td;
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buf_sof_n <= #`TCQ cfg_tx_sof_n;
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buf_eof_n <= #`TCQ cfg_tx_eof_n;
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buf_dsc_n <= #`TCQ 1'b1;
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buf_rem_n <= #`TCQ cfg_tx_rem_n;
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buf_vld <= #`TCQ 1'b1;
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end else if (buf_rd) begin
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buf_vld <= #`TCQ 1'b0;
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end
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end
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end
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// Control when the shunt buffer is written and read
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// Writes go to the shunt buffer when the first pipeline stage is full
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// and not emptying
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assign buf_divert = !tx_src_rdy_n && tx_dst_rdy_n;
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// The shunt buffer gets read when the pipeline is first shifted after
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// the shunt buffer is filled
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assign buf_rd = buf_vld && !tx_src_rdy_n && !tx_dst_rdy_n;
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// Asserted if the shunt buffer is filling
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assign buf_filling = buf_divert &&
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((!cfg_tx_src_rdy_n && !cfg_tx_dst_rdy_n) ||
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(!trn_tsrc_rdy_n && !trn_tdst_rdy_n));
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// Output buffer
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always @(posedge clk) begin
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if (!rst_n) begin
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tx_src_rdy_n <= #`TCQ 1'b1;
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end else begin
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// Multiplex the three inputs into the output data
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casex ({buf_rd,
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(!cfg_tx_src_rdy_n && !cfg_tx_dst_rdy_n && !buf_divert),
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(!trn_tsrc_rdy_n && !trn_tdst_rdy_n && !buf_divert)})
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3'b1xx: begin
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// Buf_rd always has priority. If one of the other sources has
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// a successful transaction but we're reading from the buffer,
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// that incoming transaction goes into the buffer, not the output
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tx_td <= #`TCQ buf_td;
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tx_sof_n <= #`TCQ buf_sof_n;
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tx_eof_n <= #`TCQ buf_eof_n;
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tx_src_dsc_n <= #`TCQ buf_dsc_n;
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tx_rem_n_bit <= #`TCQ buf_rem_n;
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end
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3'b010: begin
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// Select from config input
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tx_td <= #`TCQ cfg_tx_td;
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tx_sof_n <= #`TCQ cfg_tx_sof_n;
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tx_eof_n <= #`TCQ cfg_tx_eof_n;
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tx_src_dsc_n <= #`TCQ 1'b1;
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tx_rem_n_bit <= #`TCQ cfg_tx_rem_n;
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end
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3'b001: begin
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// Select from user input
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tx_td <= #`TCQ trn_td;
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tx_sof_n <= #`TCQ trn_tsof_n;
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tx_eof_n <= #`TCQ trn_teof_n && trn_tsrc_dsc_n;
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tx_src_dsc_n <= #`TCQ trn_tsrc_dsc_n;
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tx_rem_n_bit <= #`TCQ trn_trem_n;
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end
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3'b000: ; // This case is OK - don't have to move data every cycle
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default: begin
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// Anything other than the above cases is BAD
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// synthesis translate_off
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$display("ERROR: pcie_blk_ll_tx_arb hit an illegal mux input combination");
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$finish;
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// synthesis translate_on
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end
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endcase
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// Generate the output-valid signal
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// Prevent user-data outside of a packet (data after EOF and before
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// SOF) from being accepted by the core by masking with usr_in_pkt_inc
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if (buf_rd || (!cfg_tx_src_rdy_n && !cfg_tx_dst_rdy_n) ||
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(!trn_tsrc_rdy_n && !trn_tdst_rdy_n && usr_in_pkt_inc)) begin
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tx_src_rdy_n <= #`TCQ 1'b0;
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end else if (!tx_dst_rdy_n) begin
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tx_src_rdy_n <= #`TCQ 1'b1;
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end
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end
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end
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// REM is an 8-bit signal into the existing bridge code (although
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// only 1 bit is actually used) so we synthesize the rest of it here
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assign tx_rem_n = {4'b0000, {4{tx_rem_n_bit}}};
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endmodule // pcie_blk_ll_tx_arb
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