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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : pcie_blk_plus_ll_rx.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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//--
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//-- Description: PCIe Block Plus Rx LocalLink Bridge
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//--
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//--
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//--
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//------------------------------------------------------------------------------
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`timescale 1ns/1ns
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`ifndef TCQ
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`define TCQ 1
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`endif
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`ifndef TCQ
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`define TCQ 1
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`endif
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module pcie_blk_plus_ll_rx #
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(
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parameter BAR0 = 32'hffff_0001, // base address cfg[ 95: 64]
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parameter BAR1 = 32'hffff_0000, // base address cfg[127: 96]
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parameter BAR2 = 32'hffff_0004, // base address cfg[159:128]
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parameter BAR3 = 32'hffff_ffff, // base address cfg[191:160]
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parameter BAR4 = 32'h0000_0000, // base address cfg[223:192]
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parameter BAR5 = 32'h0000_0000, // base address cfg[255:224]
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parameter XROM_BAR = 32'hffff_f001, // expansion rom bar cfg[351:320]
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parameter MPS = 3'b101, // Max Payload Size cfg[370:368]
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parameter LEGACY_EP = 1'b0, // Legacy PCI endpoint?
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parameter TRIM_ECRC = 1'b0, // Trim ECRC from rx TLPs cfg[508]
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parameter CPL_STREAMING_PRIORITIZE_P_NP = 0 // arb priority to P/NP during cpl strm
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)
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(
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// Clock and reset
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input wire clk,
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input wire rst_n,
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// PCIe Block Rx Ports
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output wire llk_rx_dst_req_n,
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output wire llk_rx_dst_cont_req_n,
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output wire [2:0] llk_rx_ch_tc,
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output wire [1:0] llk_rx_ch_fifo,
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input wire [7:0] llk_tc_status,
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input wire [63:0] llk_rx_data,
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output reg [63:0] llk_rx_data_d = 64'hffffffff, //needed by mgmt module
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input wire llk_rx_src_rdy_n,
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input wire llk_rx_src_last_req_n,
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input wire llk_rx_src_dsc_n,
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input wire llk_rx_sof_n,
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input wire llk_rx_eof_n,
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input wire [1:0] llk_rx_valid_n,
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input wire [7:0] llk_rx_ch_posted_available_n,
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input wire [7:0] llk_rx_ch_non_posted_available_n,
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input wire [7:0] llk_rx_ch_completion_available_n,
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input wire [15:0] llk_rx_preferred_type,
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// LocalLink Rx Ports
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output [63:0] trn_rd,
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output [7:0] trn_rrem_n,
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output trn_rsof_n,
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output trn_reof_n,
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output trn_rsrc_rdy_n,
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output reg trn_rsrc_dsc_n = 1'b1, // FIXME
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output trn_rerrfwd_n,
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output [6:0] trn_rbar_hit_n,
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input wire trn_lnk_up_n,
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input wire trn_rnp_ok_n,
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input wire trn_rdst_rdy_n,
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input wire trn_rcpl_streaming_n,
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// Sideband signals to control operation
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input wire [31:0] cfg_rx_bar0,
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input wire [31:0] cfg_rx_bar1,
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input wire [31:0] cfg_rx_bar2,
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input wire [31:0] cfg_rx_bar3,
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input wire [31:0] cfg_rx_bar4,
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input wire [31:0] cfg_rx_bar5,
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input wire [31:0] cfg_rx_xrom,
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input wire [7:0] cfg_bus_number,
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input wire [4:0] cfg_device_number,
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input wire [2:0] cfg_function_number,
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input wire [15:0] cfg_dcommand,
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input wire [15:0] cfg_pmcsr,
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input wire io_space_enable,
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input wire mem_space_enable,
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input wire [2:0] max_payload_size,
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// Error signaling logic
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output wire rx_err_cpl_abort_n,
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output wire rx_err_cpl_ur_n,
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output wire rx_err_cpl_ep_n,
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output wire rx_err_ep_n,
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output wire [47:0] err_tlp_cpl_header,
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output wire err_tlp_p,
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output wire err_tlp_ur,
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output wire err_tlp_ur_lock,
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output wire err_tlp_uc,
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output wire err_tlp_malformed,
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input wire l0_stats_tlp_received,
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input wire [7:0] rx_ch_credits_received,
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input wire rx_ch_credits_received_inc
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);
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localparam MPS_DECODE = (MPS == 3'b101) ? 4096 :
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(MPS == 3'b100) ? 2048 :
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(MPS == 3'b011) ? 1024 :
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(MPS == 3'b010) ? 512 :
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(MPS == 3'b001) ? 256 :
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(MPS == 3'b000) ? 128 :
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-1; // Dummy bad value
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// Data from data_snk to FIFO
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wire [63:0] snk_d;
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wire snk_sof;
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wire snk_eof;
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wire snk_preeof;
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wire snk_src_rdy;
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wire snk_rem;
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wire snk_src_dsc;
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wire [6:0] snk_bar;
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wire snk_rid;
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wire snk_bar_src_rdy;
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wire snk_np;
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wire snk_cpl;
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wire snk_cfg;
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wire snk_locked;
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wire snk_vend_msg;
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// BAR checking between data_snk and cmm_decoder
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wire [63:0] check_raddr;
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wire check_mem32;
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wire check_mem64;
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wire check_rio;
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wire check_rdev;
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wire check_rbus;
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wire check_rfun;
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wire check_rhit;
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wire [6:0] check_rhit_bar;
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wire check_rhit_bar_lat3;
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// Interface between FIFO and request logic
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wire fifo_np_ok;
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wire fifo_pcpl_ok;
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wire fifo_np_req;
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wire fifo_pcpl_req;
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// Processing of data between data_snk and FIFO
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reg snk_np_reg;
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reg [3:0] snk_barenc;
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reg snk_bar_ok;
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reg abort_np;
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reg abort_pcpl;
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// User outputs (these signals are inverted before being output)
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wire trn_rsrc_rdy;
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wire [7:0] trn_rrem;
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wire trn_rsof;
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wire trn_reof;
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wire trn_rerrfwd;
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wire [6:0] trn_rbar_hit;
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reg llk_rx_sof_n_d = 1;
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reg llk_rx_eof_n_d = 1;
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reg [1:0] llk_rx_valid_n_d = 0;
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reg llk_rx_src_rdy_n_d = 1;
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reg llk_rx_src_dsc_n_d = 1;
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wire rx_err_cpl_abort;
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wire rx_err_cpl_ur;
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wire rx_err_cpl_ep;
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wire rx_err_ep;
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assign rx_err_cpl_abort_n = !rx_err_cpl_abort;
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assign rx_err_cpl_ur_n = !rx_err_cpl_ur;
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assign rx_err_cpl_ep_n = !rx_err_cpl_ep;
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assign rx_err_ep_n = !rx_err_ep;
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// Drive unsupported outputs to a known value
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//assign llk_rx_dst_cont_req_n = 1;
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// BAR Checking and packet filtering logic (from TLM)
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tlm_rx_data_snk
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#(.DW (64), // Data width
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.FCW (6), // Packet credit width - not used
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.BARW (7), // BAR-hit width
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.DOWNSTREAM_PORT (0), // Endpoint, not downstream port
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.MPS (MPS_DECODE),// Core (capability) MPS
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.TYPE1_UR (1) // Issue UR on Type1 config TLP
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) snk_inst (
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.clk_i (clk),
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.reset_i (!rst_n),
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//--------------------------------------------------------
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// Datapath signals
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//--------------------------------------------------------
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// To FIFO
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.d_o (snk_d), // Data
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.sof_o (snk_sof), // ll sof
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.eof_o (snk_eof), // ll eof
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.preeof_o (snk_preeof), // ll eof 1 cycle early
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.src_rdy_o (snk_src_rdy), // ll src_rdy
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.rem_o (snk_rem), // ll rem (in words)
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.dsc_o (snk_src_dsc), // ll dsc
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.cfg_o (snk_cfg), // Config packet, @bar
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.locked_o (snk_locked), // Locked msg or cpl, @bar
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.np_o (snk_np), // Non-posted packet, @bar
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.cpl_o (snk_cpl), // Completion packet, @bar
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.bar_o (snk_bar), // Bar hit, @bar
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.rid_o (snk_rid), // RID hit, @bar
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.vend_msg_o (snk_vend_msg), // Vendor-defined MSG, @bar
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.bar_src_rdy_o (snk_bar_src_rdy), // ll src_rdy
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// To Flow controller
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.fc_use_p_o (), // posted update.. implies 1 hdr
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.fc_use_np_o (), // nonposted update.. ''
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.fc_use_cpl_o (), // compl update.. ''
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.fc_use_data_o (), // number of data credits used
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279 |
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.fc_unuse_o (), // ll src_rdy.. implies 1 header
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280 |
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281 |
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// From LLM
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.d_i (llk_rx_data_d), // Data
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.sof_i (!llk_rx_sof_n_d), // ll sof
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.eof_i (!llk_rx_eof_n_d), // ll eof
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.rem_i (!llk_rx_valid_n_d[0]), // ll rem in binary bytes
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.src_rdy_i (!llk_rx_src_rdy_n_d), // ll src_rdy
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.src_dsc_i (!llk_rx_src_dsc_n_d), // ll dsc
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289 |
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//--------------------------------------------------------
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// Sideband signals
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//--------------------------------------------------------
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292 |
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// InitFC communication to LLM
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294 |
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.vc_hit_o (), // TLP received on VC0
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295 |
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296 |
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// Power management signals for CMM
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297 |
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.pm_as_nak_l1_o (), // Pkt detected, implies src_rdy
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298 |
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.pm_turn_off_o (), // Pkt detected, implies src_rdy
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.pm_set_slot_pwr_o (), // Pkt detected, implies src_rdy
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.pm_set_slot_pwr_data_o (), // value of field
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301 |
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.pm_suspend_req_i (1'b0), // Go into pm.. drop packets - NOTE: should be
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302 |
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// handled internally by Block
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303 |
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// Completion event information for CMM
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.err_tlp_cpl_header_o (err_tlp_cpl_header), // Header fields
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.err_tlp_p_o (err_tlp_p), // Pkt is posted
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.err_tlp_ur_o (err_tlp_ur), // Unsupported req, implies src_rdy
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.err_tlp_ur_lock_o (err_tlp_ur_lock),// Unsupported req dur to lock, implies src_rdy
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.err_tlp_uc_o (err_tlp_uc), // Unsupported cpl, implies src_rdy
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.err_tlp_malformed_o (err_tlp_malformed), // Pkt is badly constructed,
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// implies src_rdy
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// status register in the CMM
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313 |
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.stat_tlp_cpl_abort_o (rx_err_cpl_abort), // cpl stat is abort
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314 |
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.stat_tlp_cpl_ur_o (rx_err_cpl_ur), // cpl stat is ur
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315 |
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.stat_tlp_cpl_ep_o (rx_err_cpl_ep), // cpl inc pkt poison
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316 |
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.stat_tlp_ep_o (rx_err_ep), // incoming pkt poison
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317 |
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318 |
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// Outgoing information to check CMM for bar hit
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319 |
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.check_raddr_o (check_raddr), // is address mapped?
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320 |
|
|
.check_mem32_o (check_mem32),
|
321 |
|
|
.check_mem64_o (check_mem64),
|
322 |
|
|
.check_rio_o (check_rio), // implies src_rdy
|
323 |
|
|
.check_rdev_o (check_rdev), // implies src_rdy
|
324 |
|
|
.check_rbus_o (check_rbus), // implies src_rdy
|
325 |
|
|
.check_rfun_o (check_rfun), // implies src_rdy
|
326 |
|
|
// Incoming information from CMM on bar hit status
|
327 |
|
|
.check_rhit_i (check_rhit), // match found
|
328 |
|
|
.check_rhit_bar_i (check_rhit_bar),// address of match
|
329 |
|
|
// Static control from CMM
|
330 |
|
|
.max_payload_i (max_payload_size),// Enc val for max paysize allowed
|
331 |
|
|
.rhit_bar_lat3_i (check_rhit_bar_lat3), // BAR-hit latency 3 clocks?
|
332 |
|
|
.legacy_mode_i (LEGACY_EP), // For interp of the spec
|
333 |
|
|
.legacy_cfg_access_i(1'b0), // User implements legacy config? Not
|
334 |
|
|
// supported in this release
|
335 |
|
|
.ext_cfg_access_i (1'b0), // User implements ext. config? Not
|
336 |
|
|
// supported in this release
|
337 |
|
|
.hotplug_msg_enable_i(1'b0), // Pass obsolete hot-plug to user? Never.
|
338 |
|
|
.td_ecrc_trim_i (TRIM_ECRC) // Strip digest for user?
|
339 |
|
|
);
|
340 |
|
|
|
341 |
|
|
// Populate the bits of the cfg bus which are required by cmm_decoder;
|
342 |
|
|
// set everything else to X so if it's used but we didn't notice, the
|
343 |
|
|
// X will propagate
|
344 |
|
|
wire [671:0] cfg_temp = {{320{1'bx}}, XROM_BAR, {64{1'bx}}, BAR5,
|
345 |
|
|
BAR4, BAR3, BAR2, BAR1, BAR0, {64{1'bx}}};
|
346 |
|
|
|
347 |
|
|
// Instantiate BAR decoder logic from the CMM32
|
348 |
|
|
cmm_decoder bar_decoder
|
349 |
|
|
(
|
350 |
|
|
.raddr (check_raddr),
|
351 |
|
|
.rmem32 (check_mem32),
|
352 |
|
|
.rmem64 (check_mem64),
|
353 |
|
|
.rio (check_rio),
|
354 |
|
|
.rcheck_bus_id (check_rbus),
|
355 |
|
|
.rcheck_dev_id (check_rdev),
|
356 |
|
|
.rcheck_fun_id (check_rfun),
|
357 |
|
|
.rhit (check_rhit),
|
358 |
|
|
.bar_hit (check_rhit_bar),
|
359 |
|
|
.cmmt_rbar_hit_lat2_n (check_rhit_bar_lat3), // lat=2 if low, =3 if high
|
360 |
|
|
.command ({14'hXXXX, mem_space_enable, io_space_enable}),
|
361 |
|
|
.bar0_reg (cfg_rx_bar0),
|
362 |
|
|
.bar1_reg (cfg_rx_bar1),
|
363 |
|
|
.bar2_reg (cfg_rx_bar2),
|
364 |
|
|
.bar3_reg (cfg_rx_bar3),
|
365 |
|
|
.bar4_reg (cfg_rx_bar4),
|
366 |
|
|
.bar5_reg (cfg_rx_bar5),
|
367 |
|
|
.xrom_reg (cfg_rx_xrom),
|
368 |
|
|
.pme_pmcsr (cfg_pmcsr),
|
369 |
|
|
.bus_num (cfg_bus_number),
|
370 |
|
|
.device_num (cfg_device_number),
|
371 |
|
|
.function_num (cfg_function_number),
|
372 |
|
|
.phantom_functions_supported (2'b01), //Block core supports 1 phantom bit
|
373 |
|
|
.phantom_functions_enabled (cfg_dcommand[9]),
|
374 |
|
|
.cfg (cfg_temp),
|
375 |
|
|
.rst (!rst_n),
|
376 |
|
|
.clk (clk)
|
377 |
|
|
);
|
378 |
|
|
|
379 |
|
|
// Determine if the current TLP from the data_snk is valid for output
|
380 |
|
|
// to user logic. TLPs are valid _unless_ one of the following is true:
|
381 |
|
|
//
|
382 |
|
|
// 1) TLP is a request and did not hit any BAR
|
383 |
|
|
// 2) TLP should have been processed by config logic
|
384 |
|
|
// 3) TLP is a locked transaction and this isn't a Legacy Endpoint
|
385 |
|
|
// 4) TLP is a completion but doesn't match our RID
|
386 |
|
|
//
|
387 |
|
|
// Additionally, the BAR value is encoded to fit in 4 bits so that it
|
388 |
|
|
// can be stored in a single BRAM in parallel with data.
|
389 |
|
|
always @(posedge clk) begin
|
390 |
|
|
if (snk_bar_src_rdy) begin
|
391 |
|
|
case (snk_bar)
|
392 |
|
|
// 32-bit BARs
|
393 |
|
|
7'b0000001: snk_barenc <= #`TCQ 4'b0000;
|
394 |
|
|
7'b0000010: snk_barenc <= #`TCQ 4'b0001;
|
395 |
|
|
7'b0000100: snk_barenc <= #`TCQ 4'b0010;
|
396 |
|
|
7'b0001000: snk_barenc <= #`TCQ 4'b0011;
|
397 |
|
|
7'b0010000: snk_barenc <= #`TCQ 4'b0100;
|
398 |
|
|
7'b0100000: snk_barenc <= #`TCQ 4'b0101;
|
399 |
|
|
7'b1000000: snk_barenc <= #`TCQ 4'b0110;
|
400 |
|
|
// 64-bit BARs
|
401 |
|
|
7'b0000011: snk_barenc <= #`TCQ 4'b0111;
|
402 |
|
|
7'b0000110: snk_barenc <= #`TCQ 4'b1000;
|
403 |
|
|
7'b0001100: snk_barenc <= #`TCQ 4'b1001;
|
404 |
|
|
7'b0011000: snk_barenc <= #`TCQ 4'b1010;
|
405 |
|
|
7'b0110000: snk_barenc <= #`TCQ 4'b1011;
|
406 |
|
|
// No BAR hit
|
407 |
|
|
default: snk_barenc <= #`TCQ 4'b1100;
|
408 |
|
|
endcase
|
409 |
|
|
snk_np_reg <= #`TCQ snk_np;
|
410 |
|
|
snk_bar_ok <= #`TCQ (snk_vend_msg ? 1'b1 :
|
411 |
|
|
(snk_cpl ? snk_rid : |snk_bar))
|
412 |
|
|
&& !snk_cfg && !(snk_locked && !LEGACY_EP);
|
413 |
|
|
end
|
414 |
|
|
end
|
415 |
|
|
|
416 |
|
|
// Detect TLPs that are never fully written to the FIFO and cause the
|
417 |
|
|
// FIFO fullness counter to be decremented appropriately
|
418 |
|
|
always @(posedge clk) begin
|
419 |
|
|
if (!rst_n) begin
|
420 |
|
|
abort_np <= #`TCQ 1'b0;
|
421 |
|
|
abort_pcpl <= #`TCQ 1'b0;
|
422 |
|
|
end else begin
|
423 |
|
|
abort_np <= #`TCQ snk_src_rdy && snk_src_dsc && snk_np_reg;
|
424 |
|
|
abort_pcpl <= #`TCQ snk_src_rdy && snk_src_dsc && !snk_np_reg;
|
425 |
|
|
end
|
426 |
|
|
end
|
427 |
|
|
|
428 |
|
|
always @(posedge clk) begin
|
429 |
|
|
if (!rst_n) begin
|
430 |
|
|
llk_rx_sof_n_d <= #`TCQ 1;
|
431 |
|
|
llk_rx_eof_n_d <= #`TCQ 1;
|
432 |
|
|
llk_rx_valid_n_d <= #`TCQ 0;
|
433 |
|
|
llk_rx_src_rdy_n_d <= #`TCQ 1;
|
434 |
|
|
llk_rx_src_dsc_n_d <= #`TCQ 1;
|
435 |
|
|
end else begin
|
436 |
|
|
llk_rx_sof_n_d <= #`TCQ llk_rx_sof_n;
|
437 |
|
|
llk_rx_eof_n_d <= #`TCQ llk_rx_eof_n;
|
438 |
|
|
llk_rx_valid_n_d <= #`TCQ llk_rx_valid_n;
|
439 |
|
|
llk_rx_src_rdy_n_d <= #`TCQ llk_rx_src_rdy_n;
|
440 |
|
|
llk_rx_src_dsc_n_d <= #`TCQ llk_rx_src_dsc_n;
|
441 |
|
|
end
|
442 |
|
|
end
|
443 |
|
|
|
444 |
|
|
always @(posedge clk) begin
|
445 |
|
|
llk_rx_data_d <= #`TCQ llk_rx_data;
|
446 |
|
|
end
|
447 |
|
|
|
448 |
|
|
// FIFO to store data and BAR values
|
449 |
|
|
// Accepts data from data_snk, passes data to TRN (user) interface,
|
450 |
|
|
// and communicates fullness to arbiter so it can request as many TLPs
|
451 |
|
|
// as possible to keep FIFO full.
|
452 |
|
|
//pcie_blk_ll_dualfifo fifo_inst (
|
453 |
|
|
pcie_blk_ll_oqbqfifo fifo_inst (
|
454 |
|
|
.clk (clk),
|
455 |
|
|
.rst_n (rst_n),
|
456 |
|
|
.trn_rsrc_rdy (trn_rsrc_rdy),
|
457 |
|
|
.trn_rd (trn_rd),
|
458 |
|
|
.trn_rrem (trn_rrem),
|
459 |
|
|
.trn_rsof (trn_rsof),
|
460 |
|
|
.trn_reof (trn_reof),
|
461 |
|
|
.trn_rerrfwd (trn_rerrfwd),
|
462 |
|
|
.trn_rbar_hit (trn_rbar_hit),
|
463 |
|
|
.fifo_np_ok (fifo_np_ok),
|
464 |
|
|
.fifo_pcpl_ok (fifo_pcpl_ok),
|
465 |
|
|
.trn_rdst_rdy (!trn_rdst_rdy_n),
|
466 |
|
|
.trn_rnp_ok (!trn_rnp_ok_n),
|
467 |
|
|
.fifo_wren (snk_src_rdy),
|
468 |
|
|
.fifo_data (snk_d),
|
469 |
|
|
.fifo_rem (snk_rem),
|
470 |
|
|
.fifo_sof (snk_sof && snk_bar_ok),
|
471 |
|
|
.fifo_preeof (snk_preeof),
|
472 |
|
|
.fifo_eof (snk_eof),
|
473 |
|
|
.fifo_dsc (snk_src_dsc),
|
474 |
|
|
.fifo_np (snk_np_reg),
|
475 |
|
|
.fifo_barenc (snk_barenc),
|
476 |
|
|
.fifo_np_req (fifo_np_req),
|
477 |
|
|
.fifo_pcpl_req (fifo_pcpl_req),
|
478 |
|
|
.fifo_np_abort (abort_np),
|
479 |
|
|
.fifo_pcpl_abort (abort_pcpl)
|
480 |
|
|
);
|
481 |
|
|
// Invert outputs for user logic
|
482 |
|
|
assign trn_rsrc_rdy_n = !trn_rsrc_rdy;
|
483 |
|
|
assign trn_rrem_n = ~trn_rrem;
|
484 |
|
|
assign trn_rsof_n = !trn_rsof;
|
485 |
|
|
assign trn_reof_n = !trn_reof;
|
486 |
|
|
assign trn_rerrfwd_n = !trn_rerrfwd;
|
487 |
|
|
assign trn_rbar_hit_n = ~trn_rbar_hit;
|
488 |
|
|
// FIXME add trn_tsrc_dsc_n
|
489 |
|
|
|
490 |
|
|
// Instantiate the arbiter, which determines which of the Block's FIFOs
|
491 |
|
|
// to read from next.
|
492 |
|
|
pcie_blk_ll_arb #(.CPL_STREAMING_PRIORITIZE_P_NP(CPL_STREAMING_PRIORITIZE_P_NP))
|
493 |
|
|
arb_inst (
|
494 |
|
|
.clk (clk),
|
495 |
|
|
.rst_n (rst_n),
|
496 |
|
|
.llk_rx_dst_req_n (llk_rx_dst_req_n),
|
497 |
|
|
.llk_rx_dst_cont_req_n (llk_rx_dst_cont_req_n),
|
498 |
|
|
.llk_rx_ch_tc (llk_rx_ch_tc),
|
499 |
|
|
.llk_rx_ch_fifo (llk_rx_ch_fifo),
|
500 |
|
|
.fifo_np_req (fifo_np_req),
|
501 |
|
|
.fifo_pcpl_req (fifo_pcpl_req),
|
502 |
|
|
.fifo_np_ok (fifo_np_ok),
|
503 |
|
|
.fifo_pcpl_ok (fifo_pcpl_ok),
|
504 |
|
|
.trn_rnp_ok_n (trn_rnp_ok_n),
|
505 |
|
|
.llk_rx_src_last_req_n (llk_rx_src_last_req_n),
|
506 |
|
|
.llk_rx_ch_posted_available_n (llk_rx_ch_posted_available_n),
|
507 |
|
|
.llk_rx_ch_non_posted_available_n (llk_rx_ch_non_posted_available_n),
|
508 |
|
|
.llk_rx_ch_completion_available_n (llk_rx_ch_completion_available_n),
|
509 |
|
|
.llk_rx_preferred_type (llk_rx_preferred_type),
|
510 |
|
|
.trn_rcpl_streaming_n (trn_rcpl_streaming_n),
|
511 |
|
|
.cpl_tlp_cntr (rx_ch_credits_received),
|
512 |
|
|
.cpl_tlp_cntr_inc (rx_ch_credits_received_inc)
|
513 |
|
|
);
|
514 |
|
|
|
515 |
|
|
//ASSERTIONS
|
516 |
|
|
//synthesis translate_off
|
517 |
|
|
always @(posedge clk) begin
|
518 |
|
|
if (!llk_rx_sof_n && !llk_rx_eof_n)
|
519 |
|
|
$display("FAIL: Simultaneous assertion of Llk Rx SOF/EOF ");
|
520 |
|
|
end
|
521 |
|
|
//synthesis translate_on
|
522 |
|
|
|
523 |
|
|
`ifdef SV
|
524 |
|
|
//synthesis translate_off
|
525 |
|
|
ASSERT_STALL_NP2: assert property (@(posedge clk)
|
526 |
|
|
fifo_inst.bq_full || fifo_inst.oq_full |-> !(!llk_rx_sof_n && !llk_rx_src_rdy_n &&
|
527 |
|
|
((llk_rx_data[63:56]==8'h00) ||
|
528 |
|
|
(llk_rx_data[63:56]==8'h20) ||
|
529 |
|
|
(llk_rx_data[63:56]==8'h01) ||
|
530 |
|
|
(llk_rx_data[63:56]==8'h21)
|
531 |
|
|
))
|
532 |
|
|
) else $fatal;
|
533 |
|
|
ASSERT_STALL_PCPL2: assert property (@(posedge clk)
|
534 |
|
|
fifo_inst.oq_full |-> !(!llk_rx_sof_n && !llk_rx_src_rdy_n)
|
535 |
|
|
) else $fatal;
|
536 |
|
|
//synthesis translate_on
|
537 |
|
|
`endif
|
538 |
|
|
|
539 |
|
|
|
540 |
|
|
endmodule // pcie_blk_plus_ll_rx
|
541 |
|
|
|