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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [pcie_blk_plus_ll_rx.v] - Blame information for rev 2

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2
//-----------------------------------------------------------------------------
3
//
4
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
5
//
6
// This file contains confidential and proprietary information
7
// of Xilinx, Inc. and is protected under U.S. and
8
// international copyright and other intellectual property
9
// laws.
10
//
11
// DISCLAIMER
12
// This disclaimer is not a license and does not grant any
13
// rights to the materials distributed herewith. Except as
14
// otherwise provided in a valid license issued to you by
15
// Xilinx, and to the maximum extent permitted by applicable
16
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
17
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
18
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
19
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
20
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
21
// (2) Xilinx shall not be liable (whether in contract or tort,
22
// including negligence, or under any other theory of
23
// liability) for any loss or damage of any kind or nature
24
// related to, arising under or in connection with these
25
// materials, including for any direct, or any indirect,
26
// special, incidental, or consequential loss or damage
27
// (including loss of data, profits, goodwill, or any type of
28
// loss or damage suffered as a result of any action brought
29
// by a third party) even if such damage or loss was
30
// reasonably foreseeable or Xilinx had been advised of the
31
// possibility of the same.
32
//
33
// CRITICAL APPLICATIONS
34
// Xilinx products are not designed or intended to be fail-
35
// safe, or for use in any application requiring fail-safe
36
// performance, such as life-support or safety devices or
37
// systems, Class III medical devices, nuclear facilities,
38
// applications related to the deployment of airbags, or any
39
// other applications that could lead to death, personal
40
// injury, or severe property or environmental damage
41
// (individually and collectively, "Critical
42
// Applications"). Customer assumes the sole risk and
43
// liability of any use of Xilinx products in Critical
44
// Applications, subject only to applicable laws and
45
// regulations governing limitations on product liability.
46
//
47
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
48
// PART OF THIS FILE AT ALL TIMES.
49
//
50
//-----------------------------------------------------------------------------
51
// Project    : V5-Block Plus for PCI Express
52
// File       : pcie_blk_plus_ll_rx.v
53
//--------------------------------------------------------------------------------
54
//--------------------------------------------------------------------------------
55
//--
56
//-- Description: PCIe Block Plus Rx LocalLink Bridge
57
//--
58
//--             
59
//--
60
//------------------------------------------------------------------------------
61
 
62
`timescale 1ns/1ns
63
`ifndef TCQ
64
 `define TCQ 1
65
`endif
66
 
67
`ifndef TCQ
68
  `define TCQ 1
69
`endif
70
 
71
module pcie_blk_plus_ll_rx #
72
(
73
   parameter   BAR0 = 32'hffff_0001,               // base address                                   cfg[ 95: 64]
74
   parameter   BAR1 = 32'hffff_0000,               // base address                                   cfg[127: 96]
75
   parameter   BAR2 = 32'hffff_0004,               // base address                                   cfg[159:128]
76
   parameter   BAR3 = 32'hffff_ffff,               // base address                                   cfg[191:160]
77
   parameter   BAR4 = 32'h0000_0000,               // base address                                   cfg[223:192]
78
   parameter   BAR5 = 32'h0000_0000,               // base address                                   cfg[255:224]
79
   parameter   XROM_BAR = 32'hffff_f001,           // expansion rom bar                              cfg[351:320]
80
   parameter   MPS = 3'b101,                       // Max Payload Size                               cfg[370:368]
81
   parameter   LEGACY_EP = 1'b0,                   // Legacy PCI endpoint?
82
   parameter   TRIM_ECRC = 1'b0,                   // Trim ECRC from rx TLPs                         cfg[508]
83
   parameter   CPL_STREAMING_PRIORITIZE_P_NP = 0   // arb priority to P/NP during cpl strm
84
)
85
(
86
  // Clock and reset
87
 
88
  input wire         clk,
89
  input wire         rst_n,
90
 
91
  // PCIe Block Rx Ports
92
 
93
  output wire        llk_rx_dst_req_n,
94
  output wire        llk_rx_dst_cont_req_n,
95
  output wire [2:0]  llk_rx_ch_tc,
96
  output wire [1:0]  llk_rx_ch_fifo,
97
 
98
  input  wire [7:0]  llk_tc_status,
99
  input  wire [63:0] llk_rx_data,
100
  output reg  [63:0] llk_rx_data_d = 64'hffffffff, //needed by mgmt module
101
  input  wire        llk_rx_src_rdy_n,
102
  input  wire        llk_rx_src_last_req_n,
103
  input  wire        llk_rx_src_dsc_n,
104
  input  wire        llk_rx_sof_n,
105
  input  wire        llk_rx_eof_n,
106
  input  wire [1:0]  llk_rx_valid_n,
107
  input  wire [7:0]  llk_rx_ch_posted_available_n,
108
  input  wire [7:0]  llk_rx_ch_non_posted_available_n,
109
  input  wire [7:0]  llk_rx_ch_completion_available_n,
110
  input  wire [15:0] llk_rx_preferred_type,
111
 
112
  // LocalLink Rx Ports
113
 
114
  output      [63:0] trn_rd,
115
  output      [7:0]  trn_rrem_n,
116
  output             trn_rsof_n,
117
  output             trn_reof_n,
118
  output             trn_rsrc_rdy_n,
119
  output reg         trn_rsrc_dsc_n = 1'b1, // FIXME
120
  output             trn_rerrfwd_n,
121
  output      [6:0]  trn_rbar_hit_n,
122
  input  wire        trn_lnk_up_n,
123
 
124
  input  wire        trn_rnp_ok_n,
125
  input  wire        trn_rdst_rdy_n,
126
  input  wire        trn_rcpl_streaming_n,
127
 
128
  // Sideband signals to control operation
129
  input  wire [31:0] cfg_rx_bar0,
130
  input  wire [31:0] cfg_rx_bar1,
131
  input  wire [31:0] cfg_rx_bar2,
132
  input  wire [31:0] cfg_rx_bar3,
133
  input  wire [31:0] cfg_rx_bar4,
134
  input  wire [31:0] cfg_rx_bar5,
135
  input  wire [31:0] cfg_rx_xrom,
136
  input  wire [7:0]  cfg_bus_number,
137
  input  wire [4:0]  cfg_device_number,
138
  input  wire [2:0]  cfg_function_number,
139
  input  wire [15:0] cfg_dcommand,
140
  input  wire [15:0] cfg_pmcsr,
141
  input  wire        io_space_enable,
142
  input  wire        mem_space_enable,
143
  input  wire [2:0]  max_payload_size,
144
 
145
  // Error signaling logic
146
  output wire        rx_err_cpl_abort_n,
147
  output wire        rx_err_cpl_ur_n,
148
  output wire        rx_err_cpl_ep_n,
149
  output wire        rx_err_ep_n,
150
  output wire [47:0] err_tlp_cpl_header,
151
  output wire        err_tlp_p,
152
  output wire        err_tlp_ur,
153
  output wire        err_tlp_ur_lock,
154
  output wire        err_tlp_uc,
155
  output wire        err_tlp_malformed,
156
  input  wire        l0_stats_tlp_received,
157
 
158
  input  wire  [7:0] rx_ch_credits_received,
159
  input  wire        rx_ch_credits_received_inc
160
);
161
 
162
  localparam MPS_DECODE = (MPS == 3'b101) ? 4096 :
163
                          (MPS == 3'b100) ? 2048 :
164
                          (MPS == 3'b011) ? 1024 :
165
                          (MPS == 3'b010) ?  512 :
166
                          (MPS == 3'b001) ?  256 :
167
                          (MPS == 3'b000) ?  128 :
168
                                             -1; // Dummy bad value
169
 
170
  // Data from data_snk to FIFO
171
  wire [63:0]     snk_d;
172
  wire            snk_sof;
173
  wire            snk_eof;
174
  wire            snk_preeof;
175
  wire            snk_src_rdy;
176
  wire            snk_rem;
177
  wire            snk_src_dsc;
178
  wire [6:0]      snk_bar;
179
  wire            snk_rid;
180
  wire            snk_bar_src_rdy;
181
  wire            snk_np;
182
  wire            snk_cpl;
183
  wire            snk_cfg;
184
  wire            snk_locked;
185
  wire            snk_vend_msg;
186
 
187
  // BAR checking between data_snk and cmm_decoder
188
  wire [63:0]     check_raddr;
189
  wire            check_mem32;
190
  wire            check_mem64;
191
  wire            check_rio;
192
  wire            check_rdev;
193
  wire            check_rbus;
194
  wire            check_rfun;
195
  wire            check_rhit;
196
  wire [6:0]      check_rhit_bar;
197
  wire            check_rhit_bar_lat3;
198
 
199
  // Interface between FIFO and request logic
200
  wire            fifo_np_ok;
201
  wire            fifo_pcpl_ok;
202
  wire            fifo_np_req;
203
  wire            fifo_pcpl_req;
204
 
205
  // Processing of data between data_snk and FIFO
206
  reg             snk_np_reg;
207
  reg  [3:0]      snk_barenc;
208
  reg             snk_bar_ok;
209
  reg             abort_np;
210
  reg             abort_pcpl;
211
 
212
  // User outputs (these signals are inverted before being output)
213
  wire            trn_rsrc_rdy;
214
  wire [7:0]      trn_rrem;
215
  wire            trn_rsof;
216
  wire            trn_reof;
217
  wire            trn_rerrfwd;
218
  wire [6:0]      trn_rbar_hit;
219
 
220
 
221
  reg             llk_rx_sof_n_d     = 1;
222
  reg             llk_rx_eof_n_d     = 1;
223
  reg  [1:0]      llk_rx_valid_n_d   = 0;
224
  reg             llk_rx_src_rdy_n_d = 1;
225
  reg             llk_rx_src_dsc_n_d = 1;
226
 
227
  wire            rx_err_cpl_abort;
228
  wire            rx_err_cpl_ur;
229
  wire            rx_err_cpl_ep;
230
  wire            rx_err_ep;
231
 
232
  assign          rx_err_cpl_abort_n = !rx_err_cpl_abort;
233
  assign          rx_err_cpl_ur_n    = !rx_err_cpl_ur;
234
  assign          rx_err_cpl_ep_n    = !rx_err_cpl_ep;
235
  assign          rx_err_ep_n        = !rx_err_ep;
236
 
237
  // Drive unsupported outputs to a known value
238
  //assign llk_rx_dst_cont_req_n = 1;
239
 
240
  // BAR Checking and packet filtering logic (from TLM)
241
  tlm_rx_data_snk
242
  #(.DW              (64), // Data width
243
    .FCW             (6),  // Packet credit width - not used
244
    .BARW            (7),  // BAR-hit width
245
    .DOWNSTREAM_PORT (0),  // Endpoint, not downstream port
246
    .MPS             (MPS_DECODE),// Core (capability) MPS
247
    .TYPE1_UR        (1)   // Issue UR on Type1 config TLP
248
   ) snk_inst (
249
    .clk_i               (clk),
250
    .reset_i             (!rst_n),
251
 
252
    //--------------------------------------------------------
253
    // Datapath signals
254
    //--------------------------------------------------------
255
 
256
    // To FIFO
257
    .d_o                (snk_d),               // Data
258
    .sof_o              (snk_sof),             // ll sof
259
    .eof_o              (snk_eof),             // ll eof
260
    .preeof_o           (snk_preeof),          // ll eof 1 cycle early
261
    .src_rdy_o          (snk_src_rdy),         // ll src_rdy
262
    .rem_o              (snk_rem),             // ll rem (in words)
263
    .dsc_o              (snk_src_dsc),         // ll dsc
264
 
265
    .cfg_o              (snk_cfg),             // Config packet, @bar
266
    .locked_o           (snk_locked),          // Locked msg or cpl, @bar
267
    .np_o               (snk_np),              // Non-posted packet, @bar
268
    .cpl_o              (snk_cpl),             // Completion packet, @bar
269
    .bar_o              (snk_bar),             // Bar hit, @bar
270
    .rid_o              (snk_rid),             // RID hit, @bar
271
    .vend_msg_o         (snk_vend_msg),        // Vendor-defined MSG, @bar
272
    .bar_src_rdy_o      (snk_bar_src_rdy),     // ll src_rdy
273
 
274
    // To Flow controller
275
    .fc_use_p_o         (), // posted update.. implies 1 hdr
276
    .fc_use_np_o        (), // nonposted update.. ''
277
    .fc_use_cpl_o       (), // compl update..     ''
278
    .fc_use_data_o      (), // number of data credits used
279
    .fc_unuse_o         (), // ll src_rdy.. implies 1 header
280
 
281
    // From LLM
282
    .d_i                (llk_rx_data_d),        // Data
283
    .sof_i              (!llk_rx_sof_n_d),      // ll sof
284
    .eof_i              (!llk_rx_eof_n_d),      // ll eof
285
    .rem_i              (!llk_rx_valid_n_d[0]), // ll rem in binary bytes
286
    .src_rdy_i          (!llk_rx_src_rdy_n_d),  // ll src_rdy
287
    .src_dsc_i          (!llk_rx_src_dsc_n_d),  // ll dsc
288
 
289
    //--------------------------------------------------------
290
    // Sideband signals
291
    //--------------------------------------------------------
292
 
293
    // InitFC communication to LLM
294
    .vc_hit_o           (),     // TLP received on VC0
295
 
296
    // Power management signals for CMM
297
    .pm_as_nak_l1_o     (),     // Pkt detected, implies src_rdy
298
    .pm_turn_off_o      (),     // Pkt detected, implies src_rdy
299
    .pm_set_slot_pwr_o  (),     // Pkt detected, implies src_rdy
300
    .pm_set_slot_pwr_data_o (), // value of field
301
    .pm_suspend_req_i   (1'b0), // Go into pm.. drop packets - NOTE: should be
302
                                // handled internally by Block
303
 
304
    // Completion event information for CMM
305
    .err_tlp_cpl_header_o (err_tlp_cpl_header), // Header fields
306
    .err_tlp_p_o        (err_tlp_p),     // Pkt is posted
307
    .err_tlp_ur_o       (err_tlp_ur),    // Unsupported req, implies src_rdy
308
    .err_tlp_ur_lock_o  (err_tlp_ur_lock),// Unsupported req dur to lock, implies src_rdy
309
    .err_tlp_uc_o       (err_tlp_uc),    // Unsupported cpl, implies src_rdy
310
    .err_tlp_malformed_o (err_tlp_malformed),   // Pkt is badly constructed,
311
                                                //   implies src_rdy
312
    // status register in the CMM
313
    .stat_tlp_cpl_abort_o (rx_err_cpl_abort),   // cpl stat is abort
314
    .stat_tlp_cpl_ur_o  (rx_err_cpl_ur),  // cpl stat is ur
315
    .stat_tlp_cpl_ep_o  (rx_err_cpl_ep),  // cpl inc pkt poison
316
    .stat_tlp_ep_o      (rx_err_ep),      // incoming pkt poison
317
 
318
    // Outgoing information to check CMM for bar hit
319
    .check_raddr_o      (check_raddr),     // is address mapped?
320
    .check_mem32_o      (check_mem32),
321
    .check_mem64_o      (check_mem64),
322
    .check_rio_o        (check_rio),       // implies src_rdy
323
    .check_rdev_o       (check_rdev),      // implies src_rdy
324
    .check_rbus_o       (check_rbus),      // implies src_rdy
325
    .check_rfun_o       (check_rfun),      // implies src_rdy
326
    // Incoming information from CMM on bar hit status
327
    .check_rhit_i       (check_rhit),    // match found
328
    .check_rhit_bar_i   (check_rhit_bar),// address of match
329
    // Static control from CMM
330
    .max_payload_i      (max_payload_size),// Enc val for max paysize allowed
331
    .rhit_bar_lat3_i    (check_rhit_bar_lat3), // BAR-hit latency 3 clocks?
332
    .legacy_mode_i      (LEGACY_EP), // For interp of the spec
333
    .legacy_cfg_access_i(1'b0),      // User implements legacy config? Not
334
                                     // supported in this release
335
    .ext_cfg_access_i   (1'b0),      // User implements ext. config? Not
336
                                     // supported in this release
337
    .hotplug_msg_enable_i(1'b0),     // Pass obsolete hot-plug to user? Never.
338
    .td_ecrc_trim_i     (TRIM_ECRC)  // Strip digest for user?
339
  );
340
 
341
  // Populate the bits of the cfg bus which are required by cmm_decoder;
342
  //   set everything else to X so if it's used but we didn't notice, the
343
  //   X will propagate
344
  wire [671:0] cfg_temp = {{320{1'bx}}, XROM_BAR, {64{1'bx}}, BAR5,
345
                          BAR4, BAR3, BAR2, BAR1, BAR0, {64{1'bx}}};
346
 
347
  // Instantiate BAR decoder logic from the CMM32
348
  cmm_decoder bar_decoder
349
  (
350
   .raddr              (check_raddr),
351
   .rmem32             (check_mem32),
352
   .rmem64             (check_mem64),
353
   .rio                (check_rio),
354
   .rcheck_bus_id      (check_rbus),
355
   .rcheck_dev_id      (check_rdev),
356
   .rcheck_fun_id      (check_rfun),
357
   .rhit               (check_rhit),
358
   .bar_hit            (check_rhit_bar),
359
   .cmmt_rbar_hit_lat2_n (check_rhit_bar_lat3), // lat=2 if low, =3 if high
360
   .command            ({14'hXXXX, mem_space_enable, io_space_enable}),
361
   .bar0_reg           (cfg_rx_bar0),
362
   .bar1_reg           (cfg_rx_bar1),
363
   .bar2_reg           (cfg_rx_bar2),
364
   .bar3_reg           (cfg_rx_bar3),
365
   .bar4_reg           (cfg_rx_bar4),
366
   .bar5_reg           (cfg_rx_bar5),
367
   .xrom_reg           (cfg_rx_xrom),
368
   .pme_pmcsr          (cfg_pmcsr),
369
   .bus_num            (cfg_bus_number),
370
   .device_num         (cfg_device_number),
371
   .function_num       (cfg_function_number),
372
   .phantom_functions_supported (2'b01), //Block core supports 1 phantom bit
373
   .phantom_functions_enabled   (cfg_dcommand[9]),
374
   .cfg                (cfg_temp),
375
   .rst                (!rst_n),
376
   .clk                (clk)
377
  );
378
 
379
  // Determine if the current TLP from the data_snk is valid for output
380
  // to user logic. TLPs are valid _unless_ one of the following is true:
381
  //
382
  // 1)  TLP is a request and did not hit any BAR
383
  // 2)  TLP should have been processed by config logic
384
  // 3)  TLP is a locked transaction and this isn't a Legacy Endpoint
385
  // 4)  TLP is a completion but doesn't match our RID
386
  //
387
  // Additionally, the BAR value is encoded to fit in 4 bits so that it
388
  // can be stored in a single BRAM in parallel with data.
389
  always @(posedge clk) begin
390
    if (snk_bar_src_rdy) begin
391
      case (snk_bar)
392
        // 32-bit BARs
393
        7'b0000001:  snk_barenc <= #`TCQ 4'b0000;
394
        7'b0000010:  snk_barenc <= #`TCQ 4'b0001;
395
        7'b0000100:  snk_barenc <= #`TCQ 4'b0010;
396
        7'b0001000:  snk_barenc <= #`TCQ 4'b0011;
397
        7'b0010000:  snk_barenc <= #`TCQ 4'b0100;
398
        7'b0100000:  snk_barenc <= #`TCQ 4'b0101;
399
        7'b1000000:  snk_barenc <= #`TCQ 4'b0110;
400
        // 64-bit BARs
401
        7'b0000011:  snk_barenc <= #`TCQ 4'b0111;
402
        7'b0000110:  snk_barenc <= #`TCQ 4'b1000;
403
        7'b0001100:  snk_barenc <= #`TCQ 4'b1001;
404
        7'b0011000:  snk_barenc <= #`TCQ 4'b1010;
405
        7'b0110000:  snk_barenc <= #`TCQ 4'b1011;
406
        // No BAR hit
407
        default:     snk_barenc <= #`TCQ 4'b1100;
408
      endcase
409
      snk_np_reg   <= #`TCQ snk_np;
410
      snk_bar_ok   <= #`TCQ (snk_vend_msg ? 1'b1 :
411
                                            (snk_cpl ? snk_rid : |snk_bar))
412
                            && !snk_cfg && !(snk_locked && !LEGACY_EP);
413
    end
414
  end
415
 
416
  // Detect TLPs that are never fully written to the FIFO and cause the
417
  // FIFO fullness counter to be decremented appropriately
418
  always @(posedge clk) begin
419
    if (!rst_n) begin
420
      abort_np    <= #`TCQ 1'b0;
421
      abort_pcpl  <= #`TCQ 1'b0;
422
    end else begin
423
      abort_np    <= #`TCQ snk_src_rdy && snk_src_dsc && snk_np_reg;
424
      abort_pcpl  <= #`TCQ snk_src_rdy && snk_src_dsc && !snk_np_reg;
425
    end
426
  end
427
 
428
  always @(posedge clk) begin
429
    if (!rst_n) begin
430
      llk_rx_sof_n_d     <= #`TCQ 1;
431
      llk_rx_eof_n_d     <= #`TCQ 1;
432
      llk_rx_valid_n_d   <= #`TCQ 0;
433
      llk_rx_src_rdy_n_d <= #`TCQ 1;
434
      llk_rx_src_dsc_n_d <= #`TCQ 1;
435
    end else begin
436
      llk_rx_sof_n_d     <= #`TCQ llk_rx_sof_n;
437
      llk_rx_eof_n_d     <= #`TCQ llk_rx_eof_n;
438
      llk_rx_valid_n_d   <= #`TCQ llk_rx_valid_n;
439
      llk_rx_src_rdy_n_d <= #`TCQ llk_rx_src_rdy_n;
440
      llk_rx_src_dsc_n_d <= #`TCQ llk_rx_src_dsc_n;
441
    end
442
  end
443
 
444
  always @(posedge clk) begin
445
    llk_rx_data_d      <= #`TCQ llk_rx_data;
446
  end
447
 
448
  // FIFO to store data and BAR values
449
  // Accepts data from data_snk, passes data to TRN (user) interface,
450
  // and communicates fullness to arbiter so it can request as many TLPs
451
  // as possible to keep FIFO full.
452
  //pcie_blk_ll_dualfifo fifo_inst (
453
  pcie_blk_ll_oqbqfifo fifo_inst (
454
    .clk             (clk),
455
    .rst_n           (rst_n),
456
    .trn_rsrc_rdy    (trn_rsrc_rdy),
457
    .trn_rd          (trn_rd),
458
    .trn_rrem        (trn_rrem),
459
    .trn_rsof        (trn_rsof),
460
    .trn_reof        (trn_reof),
461
    .trn_rerrfwd     (trn_rerrfwd),
462
    .trn_rbar_hit    (trn_rbar_hit),
463
    .fifo_np_ok      (fifo_np_ok),
464
    .fifo_pcpl_ok    (fifo_pcpl_ok),
465
    .trn_rdst_rdy    (!trn_rdst_rdy_n),
466
    .trn_rnp_ok      (!trn_rnp_ok_n),
467
    .fifo_wren       (snk_src_rdy),
468
    .fifo_data       (snk_d),
469
    .fifo_rem        (snk_rem),
470
    .fifo_sof        (snk_sof && snk_bar_ok),
471
    .fifo_preeof     (snk_preeof),
472
    .fifo_eof        (snk_eof),
473
    .fifo_dsc        (snk_src_dsc),
474
    .fifo_np         (snk_np_reg),
475
    .fifo_barenc     (snk_barenc),
476
    .fifo_np_req     (fifo_np_req),
477
    .fifo_pcpl_req   (fifo_pcpl_req),
478
    .fifo_np_abort   (abort_np),
479
    .fifo_pcpl_abort (abort_pcpl)
480
  );
481
  // Invert outputs for user logic
482
  assign trn_rsrc_rdy_n = !trn_rsrc_rdy;
483
  assign trn_rrem_n     = ~trn_rrem;
484
  assign trn_rsof_n     = !trn_rsof;
485
  assign trn_reof_n     = !trn_reof;
486
  assign trn_rerrfwd_n  = !trn_rerrfwd;
487
  assign trn_rbar_hit_n = ~trn_rbar_hit;
488
  // FIXME add trn_tsrc_dsc_n
489
 
490
  // Instantiate the arbiter, which determines which of the Block's FIFOs
491
  // to read from next.
492
  pcie_blk_ll_arb #(.CPL_STREAMING_PRIORITIZE_P_NP(CPL_STREAMING_PRIORITIZE_P_NP))
493
  arb_inst (
494
    .clk              (clk),
495
    .rst_n            (rst_n),
496
    .llk_rx_dst_req_n (llk_rx_dst_req_n),
497
    .llk_rx_dst_cont_req_n (llk_rx_dst_cont_req_n),
498
    .llk_rx_ch_tc     (llk_rx_ch_tc),
499
    .llk_rx_ch_fifo   (llk_rx_ch_fifo),
500
    .fifo_np_req      (fifo_np_req),
501
    .fifo_pcpl_req    (fifo_pcpl_req),
502
    .fifo_np_ok       (fifo_np_ok),
503
    .fifo_pcpl_ok     (fifo_pcpl_ok),
504
    .trn_rnp_ok_n     (trn_rnp_ok_n),
505
    .llk_rx_src_last_req_n            (llk_rx_src_last_req_n),
506
    .llk_rx_ch_posted_available_n     (llk_rx_ch_posted_available_n),
507
    .llk_rx_ch_non_posted_available_n (llk_rx_ch_non_posted_available_n),
508
    .llk_rx_ch_completion_available_n (llk_rx_ch_completion_available_n),
509
    .llk_rx_preferred_type            (llk_rx_preferred_type),
510
    .trn_rcpl_streaming_n             (trn_rcpl_streaming_n),
511
    .cpl_tlp_cntr     (rx_ch_credits_received),
512
    .cpl_tlp_cntr_inc (rx_ch_credits_received_inc)
513
  );
514
 
515
//ASSERTIONS
516
//synthesis translate_off
517
always @(posedge clk) begin
518
  if (!llk_rx_sof_n && !llk_rx_eof_n)
519
     $display("FAIL: Simultaneous assertion of Llk Rx SOF/EOF ");
520
end
521
//synthesis translate_on
522
 
523
`ifdef SV
524
  //synthesis translate_off
525
  ASSERT_STALL_NP2:      assert property (@(posedge clk)
526
    fifo_inst.bq_full || fifo_inst.oq_full |-> !(!llk_rx_sof_n && !llk_rx_src_rdy_n &&
527
                                                 ((llk_rx_data[63:56]==8'h00) ||
528
                                                  (llk_rx_data[63:56]==8'h20) ||
529
                                                  (llk_rx_data[63:56]==8'h01) ||
530
                                                  (llk_rx_data[63:56]==8'h21)
531
                                                 ))
532
                                         ) else $fatal;
533
  ASSERT_STALL_PCPL2:    assert property (@(posedge clk)
534
    fifo_inst.oq_full                      |-> !(!llk_rx_sof_n && !llk_rx_src_rdy_n)
535
                                         ) else $fatal;
536
//synthesis translate_on
537
`endif
538
 
539
 
540
endmodule // pcie_blk_plus_ll_rx
541
 

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