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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : pcie_blk_plus_ll_tx.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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/*****************************************************************************
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* Description : PCIe Block Plus Tx Bridge - instantiates the primary
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* LocalLink bridge (which translates between Soft-macro
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* LocalLink and the Hard-Block interface) and the TX Mux/arb
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* module (which muxes in input from the config module)
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*
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* NOTE: Search for "FIXME" tags for high-priority changes to be made
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****************************************************************************/
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`timescale 1ns/1ns
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`ifndef TCQ
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`define TCQ 1
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`endif
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module pcie_blk_plus_ll_tx #
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( parameter TX_CPL_STALL_THRESHOLD = 6,
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parameter TX_DATACREDIT_FIX_EN = 1,
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parameter TX_DATACREDIT_FIX_1DWONLY= 1,
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parameter TX_DATACREDIT_FIX_MARGIN = 6,
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parameter MPS = 0,
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parameter LEGACY_EP = 1'b0 // Legacy PCI endpoint?
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)
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(
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// Clock and reset
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input clk,
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input rst_n,
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// Transaction Link Up
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input trn_lnk_up_n,
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// PCIe Block Tx Ports
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output [63:0] llk_tx_data,
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output llk_tx_src_rdy_n,
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output llk_tx_src_dsc_n,
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output llk_tx_sof_n,
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output llk_tx_eof_n,
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output llk_tx_sop_n,
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output llk_tx_eop_n,
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output [1:0] llk_tx_enable_n,
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output [2:0] llk_tx_ch_tc,
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output [1:0] llk_tx_ch_fifo,
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input llk_tx_dst_rdy_n,
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input [9:0] llk_tx_chan_space, // ignored input
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input [7:0] llk_tx_ch_posted_ready_n, // ignored input
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input [7:0] llk_tx_ch_non_posted_ready_n, // ignored input
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input [7:0] llk_tx_ch_completion_ready_n, // ignored input
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// LocalLink Tx Ports from userapp
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input [63:0] trn_td,
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input [7:0] trn_trem_n,
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input trn_tsof_n,
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input trn_teof_n,
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input trn_tsrc_rdy_n,
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input trn_tsrc_dsc_n, // NOTE: may not be supported by Block
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input trn_terrfwd_n, // NOTE: not supported by bridge/Block
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output trn_tdst_rdy_n,
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output trn_tdst_dsc_n,
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output reg [3:0] trn_tbuf_av,
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// LocalLink TX Ports from cfg/mgmt logic
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input [63:0] cfg_tx_td,
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input cfg_tx_rem_n,
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input cfg_tx_sof_n,
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input cfg_tx_eof_n,
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input cfg_tx_src_rdy_n,
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output cfg_tx_dst_rdy_n,
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// Status output to config-bridge
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output reg tx_err_wr_ep_n = 1'b1,
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input wire [7:0] tx_ch_credits_consumed,
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input wire [11:0] tx_pd_credits_available,
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input wire [11:0] tx_pd_credits_consumed,
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input wire [11:0] tx_npd_credits_available,
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input wire [11:0] tx_npd_credits_consumed,
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input wire [11:0] tx_cd_credits_available,
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input wire [11:0] tx_cd_credits_consumed,
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input wire pd_credit_limited,
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input wire npd_credit_limited,
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input wire cd_credit_limited,
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output wire clear_cpl_count,
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input wire [7:0] trn_pfc_cplh_cl,
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input wire trn_pfc_cplh_cl_upd,
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input wire l0_stats_cfg_transmitted
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);
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wire [63:0] tx_td;
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wire tx_sof_n;
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wire tx_eof_n;
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wire [7:0] tx_rem_n;
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wire tx_src_dsc_n;
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wire tx_src_rdy_n;
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wire tx_dst_rdy_n;
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reg [2:0] trn_tbuf_av_int;
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pcie_blk_ll_tx_arb tx_arb
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(
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.clk( clk ), // I
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.rst_n( rst_n ), // I
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// Outputs to original TX Bridge
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.tx_td( tx_td ), // O[63:0]
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.tx_sof_n( tx_sof_n ), // O
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.tx_eof_n( tx_eof_n ), // O
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.tx_rem_n( tx_rem_n ), // O
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.tx_src_dsc_n( tx_src_dsc_n ), // O
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.tx_src_rdy_n( tx_src_rdy_n ), // O
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.tx_dst_rdy_n( tx_dst_rdy_n ), // I
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// User (TRN) Tx Ports
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.trn_td( trn_td ), // I[63:0]
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.trn_trem_n( trn_trem_n ), // I[7:0]
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.trn_tsof_n( trn_tsof_n ), // I
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.trn_teof_n( trn_teof_n ), // I
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.trn_tsrc_rdy_n( trn_tsrc_rdy_n ), // I
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.trn_tsrc_dsc_n( trn_tsrc_dsc_n ), // I
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.trn_tdst_rdy_n( trn_tdst_rdy_n ), // O
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.trn_tdst_dsc_n( trn_tdst_dsc_n ), // O
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// Config Tx Ports
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.cfg_tx_td( cfg_tx_td ), // I[63:0]
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.cfg_tx_rem_n( cfg_tx_rem_n ), // I
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.cfg_tx_sof_n( cfg_tx_sof_n ), // I
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.cfg_tx_eof_n( cfg_tx_eof_n ), // I
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.cfg_tx_src_rdy_n( cfg_tx_src_rdy_n ), // I
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.cfg_tx_dst_rdy_n( cfg_tx_dst_rdy_n ) // O
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);
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always @(posedge clk) begin
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// Pulse tx_err_wr_ep_n output when a packet with the EP
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// bit set is transmitted
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tx_err_wr_ep_n <= #`TCQ !(!tx_sof_n && !tx_src_rdy_n &&
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!tx_dst_rdy_n && tx_td[46]);
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end
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pcie_blk_ll_tx #
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( .TX_CPL_STALL_THRESHOLD ( TX_CPL_STALL_THRESHOLD ),
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.TX_DATACREDIT_FIX_EN ( TX_DATACREDIT_FIX_EN ),
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.TX_DATACREDIT_FIX_1DWONLY( TX_DATACREDIT_FIX_1DWONLY ),
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.TX_DATACREDIT_FIX_MARGIN ( TX_DATACREDIT_FIX_MARGIN ),
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.MPS ( MPS ),
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.LEGACY_EP ( LEGACY_EP )
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)
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tx_bridge
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(
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// Clock & Reset
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.clk( clk ), // I
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.rst_n( rst_n ), // I
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// Transaction Link Up
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.trn_lnk_up_n (trn_lnk_up_n), // I
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// PCIe Block Tx Ports
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.llk_tx_data( llk_tx_data ), // O[63:0]
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.llk_tx_src_rdy_n( llk_tx_src_rdy_n ), // O
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.llk_tx_src_dsc_n( llk_tx_src_dsc_n ), // O
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.llk_tx_sof_n( llk_tx_sof_n ), // O
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.llk_tx_eof_n( llk_tx_eof_n ), // O
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.llk_tx_sop_n( llk_tx_sop_n ), // O
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.llk_tx_eop_n( llk_tx_eop_n ), // O
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.llk_tx_enable_n( llk_tx_enable_n ), // O[1:0]
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.llk_tx_ch_tc( llk_tx_ch_tc ), // O[2:0]
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.llk_tx_ch_fifo( llk_tx_ch_fifo ), // O[1:0]
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.llk_tx_dst_rdy_n( llk_tx_dst_rdy_n ), // I
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.llk_tx_chan_space( llk_tx_chan_space ), // I[9:0]
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.llk_tx_ch_posted_ready_n( llk_tx_ch_posted_ready_n ), // I[7:0]
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.llk_tx_ch_non_posted_ready_n( llk_tx_ch_non_posted_ready_n ), // I[7:0]
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.llk_tx_ch_completion_ready_n( llk_tx_ch_completion_ready_n ), // I[7:0]
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// LocalLink Tx Ports (from arbiter/mux)
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.trn_td( tx_td ), // I[63:0]
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.trn_trem_n( tx_rem_n ), // I[7:0]
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.trn_tsof_n( tx_sof_n ), // I
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.trn_teof_n( tx_eof_n ), // I
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.trn_tsrc_rdy_n( tx_src_rdy_n ), // I
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.trn_tsrc_dsc_n( tx_src_dsc_n ), // I
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.trn_terrfwd_n( 1'b1 ), // Unused input // I
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.trn_tdst_rdy_n( tx_dst_rdy_n ), // O
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.trn_tdst_dsc_n( tx_dst_dsc_n ), // O
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.trn_tbuf_av_cpl( trn_tbuf_av_cpl ),
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.tx_ch_credits_consumed ( tx_ch_credits_consumed ),
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.tx_pd_credits_available ( tx_pd_credits_available ),
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.tx_pd_credits_consumed ( tx_pd_credits_consumed ),
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.tx_npd_credits_available ( tx_npd_credits_available ),
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.tx_npd_credits_consumed ( tx_npd_credits_consumed ),
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.tx_cd_credits_available ( tx_cd_credits_available ),
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.tx_cd_credits_consumed ( tx_cd_credits_consumed ),
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.clear_cpl_count ( clear_cpl_count ),
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.pd_credit_limited ( pd_credit_limited ),
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.npd_credit_limited ( npd_credit_limited ),
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.cd_credit_limited ( cd_credit_limited ),
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.trn_pfc_cplh_cl ( trn_pfc_cplh_cl ),
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.trn_pfc_cplh_cl_upd ( trn_pfc_cplh_cl_upd ),
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.l0_stats_cfg_transmitted ( l0_stats_cfg_transmitted )
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);
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// trn_tbuf_av output -
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// Each bit corresponds to one payload type:
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// 0: non-posted
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// 1: posted
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// 2: completion
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// When all FIFOs of that type have room, the corresponding bit of
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// trn_tbuf_av is asserted, indicating that the Block can definitely
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// accept a packet of that type.
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always @(posedge clk) begin
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if (!rst_n) begin
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trn_tbuf_av_int <= #`TCQ 3'b000;
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end else begin
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trn_tbuf_av_int[0] <= &(~llk_tx_ch_non_posted_ready_n);
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trn_tbuf_av_int[1] <= &(~llk_tx_ch_posted_ready_n);
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trn_tbuf_av_int[2] <= &(~llk_tx_ch_completion_ready_n);
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end
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end
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always @* begin
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trn_tbuf_av[2:0] = trn_tbuf_av_int[2:0];
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trn_tbuf_av[3] = trn_tbuf_av_cpl;
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end
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endmodule // pcie_blk_plus_ll_tx
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