Subversion Repositories pcie_ds_dma

//-----------------------------------------------------------------------------

//

// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.

//

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//-----------------------------------------------------------------------------

// Project    : V5-Block Plus for PCI Express

// File       : pcie_ep.v

//--------------------------------------------------------------------------------

//--------------------------------------------------------------------------------

//--

//-- Description: PCIe Endpoint Wrapper

//--

//--

//--

//--------------------------------------------------------------------------------

`timescale 1 ns/1 ns

`define BAR_MASK_WIDTH_CALC(BAR)   BAR[63] ? (6'h3f) : \

                                   BAR[62] ? (6'h3e) : \

                                   BAR[61] ? (6'h3d) : \

                                   BAR[60] ? (6'h3c) : \

                                   BAR[59] ? (6'h3b) : \

                                   BAR[58] ? (6'h3a) : \

                                   BAR[57] ? (6'h39) : \

                                   BAR[56] ? (6'h38) : \

                                   BAR[55] ? (6'h37) : \

                                   BAR[54] ? (6'h36) : \

                                   BAR[53] ? (6'h35) : \

                                   BAR[52] ? (6'h34) : \

                                   BAR[51] ? (6'h33) : \

                                   BAR[50] ? (6'h32) : \

                                   BAR[49] ? (6'h31) : \

                                   BAR[48] ? (6'h30) : \

                                   BAR[47] ? (6'h2f) : \

                                   BAR[46] ? (6'h2e) : \

                                   BAR[45] ? (6'h2d) : \

                                   BAR[44] ? (6'h2c) : \

                                   BAR[43] ? (6'h2b) : \

                                   BAR[42] ? (6'h2a) : \

                                   BAR[41] ? (6'h29) : \

                                   BAR[40] ? (6'h28) : \

                                   BAR[39] ? (6'h27) : \

                                   BAR[38] ? (6'h26) : \

                                   BAR[37] ? (6'h25) : \

                                   BAR[36] ? (6'h24) : \

                                   BAR[35] ? (6'h23) : \

                                   BAR[34] ? (6'h22) : \

                                   BAR[33] ? (6'h21) : \

                                   BAR[32] ? (6'h20) : \

                                   BAR[31] ? (6'h1f) : \

                                   BAR[30] ? (6'h1e) : \

                                   BAR[29] ? (6'h1d) : \

                                   BAR[28] ? (6'h1c) : \

                                   BAR[27] ? (6'h1b) : \

                                   BAR[26] ? (6'h1a) : \

                                   BAR[25] ? (6'h19) : \

                                   BAR[24] ? (6'h18) : \

                                   BAR[23] ? (6'h17) : \

                                   BAR[22] ? (6'h16) : \

                                   BAR[21] ? (6'h15) : \

                                   BAR[20] ? (6'h14) : \

                                   BAR[19] ? (6'h13) : \

                                   BAR[18] ? (6'h12) : \

                                   BAR[17] ? (6'h11) : \

                                   BAR[16] ? (6'h10) : \

                                   BAR[15] ? (6'h0f) : \

                                   BAR[14] ? (6'h0e) : \

                                   BAR[13] ? (6'h0d) : \

                                   BAR[12] ? (6'h0c) : \

                                   BAR[11] ? (6'h0b) : \

                                   BAR[10] ? (6'h0a) : \

                                   BAR[9]  ? (6'h09) : \

                                   BAR[8]  ? (6'h08) : \

                                   BAR[7]  ? (6'h07) : \

                                   BAR[6]  ? (6'h06) : \

                                   BAR[5]  ? (6'h05) : (6'h04)

module   pcie_ep_top #

(

   parameter   G_USER_RESETS = 0,

   parameter   G_SIM = 0,                          // This is for simulation (1) or not (0)

   parameter   G_CHIPSCOPE = 0,                    // Use Chipscope (1) or not (0)

   parameter   INTF_CLK_FREQ = 0,                  // interface clock frequency (0=62.5, 1=100, 2=250)

   parameter   REF_CLK_FREQ = 1,                   // reference clock frequency (0=100, 1=250)

   parameter   USE_V5FXT = 0,                      // V5FXT Product (0=V5LXT/V5SXT, 1=V5FXT)

   parameter   VEN_ID = 16'h10ee,                  // vendor id                                      cfg[ 15:  0]

   parameter   DEV_ID = 16'h0007,                  // device id                                      cfg[ 31: 16]

   parameter   REV_ID = 8'h00,                     // revision id                                    cfg[ 39: 32]

   parameter   CLASS_CODE = 24'h00_00_00,          // class code                                     cfg[ 63: 40]

   parameter   BAR0 = 32'hffff_0001,               // base address                                   cfg[ 95: 64]

   parameter   BAR1 = 32'hffff_0000,               // base address                                   cfg[127: 96]

   parameter   BAR2 = 32'hffff_0004,               // base address                                   cfg[159:128]

   parameter   BAR3 = 32'hffff_ffff,               // base address                                   cfg[191:160]

   parameter   BAR4 = 32'h0000_0000,               // base address                                   cfg[223:192]

   parameter   BAR5 = 32'h0000_0000,               // base address                                   cfg[255:224]

   parameter   CARDBUS_CIS_PTR = 32'h0000_0000,    // cardbus cis pointer                            cfg[287:256]

   parameter   SUBSYS_VEN_ID = 16'h10ee,           // subsystem vendor id                            cfg[303:288]

   parameter   SUBSYS_ID = 16'h0007,               // subsystem id                                   cfg[319:304]

   parameter   XROM_BAR = 32'hfff0_0001,           // expansion rom bar                              cfg[351:320]

   // Express Capabilities (byte offset 03H-02H), cfg[367:352]

   parameter   INTR_MSG_NUM = 5'b00000,           // Interrupt Msg No.                              cfg[365:361]

   parameter   SLT_IMPL = 1'b0,                   // Slot Implemented                               cfg[360:360]

   parameter   DEV_PORT_TYPE = 4'b0000,           // Dev/Port Type                                  cfg[359:356]

   parameter   CAP_VER = 4'b0001,                 // Capability Version                             cfg[355:352]

   // Express Device Capabilities (byte offset 07H-04H), cfg[399:368]

   parameter   CAPT_SLT_PWR_LIM_SC = 2'b00,      // Capt Slt Pwr Lim Sc                            cfg[395:394]

   parameter   CAPT_SLT_PWR_LIM_VA = 8'h00,      // Capt Slt Pwr Lim Va                            cfg[393:386]

   parameter   PWR_INDI_PRSNT = 1'b0,            // Power Indi Prsnt                               cfg[382:382]

   parameter   ATTN_INDI_PRSNT = 1'b0,           // Attn Indi Prsnt                                cfg[381:381]

   parameter   ATTN_BUTN_PRSNT = 1'b0,           // Attn Butn Prsnt                                cfg[380:380]

   parameter   EP_L1_ACCPT_LAT = 3'b111,         // EP L1 Accpt Lat                                cfg[379:377]

   parameter   EP_L0s_ACCPT_LAT = 3'b111,        // EP L0s Accpt Lat                               cfg[376:374]

   parameter   EXT_TAG_FLD_SUP = 1'b0,           // Ext Tag Fld Sup                                cfg[373:373]

   parameter   PHANTM_FUNC_SUP = 2'b00,          // Phantm Func Sup                                cfg[372:371]

   parameter   MPS = 3'b101,                     // Max Payload Size                               cfg[370:368]

   // Express Link Capabilities (byte offset 00H && 0CH-0FH), cfg[431:400]

   parameter   L1_EXIT_LAT = 3'b111,             // L1 Exit Lat                                    cfg[417:415]

   parameter   L0s_EXIT_LAT = 3'b111,            // L0s Exit Lat                                   cfg[414:412]

   parameter   ASPM_SUP = 2'b01,                 // ASPM Supported                                 cfg[411:410]

   parameter   MAX_LNK_WDT = 6'b000001,          // Max Link Width                                 cfg[409:404]

   parameter   MAX_LNK_SPD = 4'b0001,            // Max Link Speed                                 cfg[403:400]

   parameter   TRM_TLP_DGST_ECRC = 1'b0,         // Trim ECRC                                      cfg[508]

   parameter   FRCE_NOSCRMBL = 1'b0,             // Force No Scrambling                            cfg[510]

   parameter   INFINITECOMPLETIONS = "TRUE",     // Completion credits are infinite

   parameter   VC0_CREDITS_PH = 8,               // Num Posted Headers

   parameter   VC0_CREDITS_NPH = 8,              // Num Non-Posted Headers

   parameter   CPL_STREAMING_PRIORITIZE_P_NP = 0,// arb priority to P/NP during cpl stream

   parameter   SLOT_CLOCK_CONFIG = "FALSE",

   parameter   C_CALENDAR_LEN     = (DEV_PORT_TYPE==4'b0000)? 16: 15,

                                                                // RSt Tc  RSt TP1 RSt Tc  RSt TC1 RSt TP2 RSt Tc  Rst TC2 RSt  F

   parameter   C_CALENDAR_SEQ     = (DEV_PORT_TYPE==4'b0000)? 128'h68__08__68__2C__68__08__68__34__68__0C__68__08__68__14__68__FF:

                                                                // RSt Tc  TP1 RSt TN1 Tc  RSt TC1 TP2 RSt TN2 Tc  RSt TC2  X

                                                              120'h68__08__2C__68__30__08__68__34__0C__68__10__08__68__14__FF,

   parameter   C_CALENDAR_SUB_LEN = 12,

                                     // PHal PHco NPHal NPHco   PDal  PDco PHli  NPHli CHli  PDli  PHli  CDli

   parameter   C_CALENDAR_SUB_SEQ = 96'h40____60____44____64____4C____6C____20____24____28____2C____30____34,

   parameter   TX_DATACREDIT_FIX_EN     = 1,

   parameter   TX_DATACREDIT_FIX_1DWONLY= 1,

   parameter   TX_DATACREDIT_FIX_MARGIN = 6,

   parameter   TX_CPL_STALL_THRESHOLD   = 6,

   // PM CAP REGISTER  (byte offset 03-02H), cfg[527:512]

   parameter   PME_SUP = 5'b01111,               // PME Support                                    cfg[527:523]

   parameter   D2_SUP = 1'b1,                    // D2 Support                                     cfg[522:522]

   parameter   D1_SUP = 1'b1,                    // D1 Support                                     cfg[521:521]

   parameter   AUX_CT = 3'b000,                  // AUX Current                                    cfg[520:518]

   parameter   DSI = 1'b0,                       // Dev Specific Initialisation                    cfg[517:517]

   parameter   PME_CLK = 1'b0,                   // PME Clock                                      cfg[515:515]

   parameter   PM_CAP_VER = 3'b010,              // Version                                        cfg[514:512]

   parameter   MSI_VECTOR = 3'b000,                     // MSI Vector Capability

   parameter   MSI_8BIT_EN = 1'b0,                     // Enable 8-bit MSI Vectors

   parameter   PWR_CON_D0_STATE = 8'h1E,        // Power consumed in D0 state                     cfg[535:528]

   parameter   CON_SCL_FCTR_D0_STATE = 8'h01,   // Scale Factor for power consumed in D0 state    cfg[543:536]

   parameter   PWR_CON_D1_STATE = 8'h1E,        // Power consumed in D1 state                     cfg[551:544]

   parameter   CON_SCL_FCTR_D1_STATE = 8'h01,   // Scale Factor for power consumed in D1 state    cfg[559:552]

   parameter   PWR_CON_D2_STATE = 8'h1E,        // Power consumed in D2 state                     cfg[567:560]

   parameter   CON_SCL_FCTR_D2_STATE = 8'h01,   // Scale Factor for power consumed in D2 state    cfg[575:568]

   parameter   PWR_CON_D3_STATE = 8'h1E,        // Power consumed in D3 state                     cfg[583:576]

   parameter   CON_SCL_FCTR_D3_STATE = 8'h01,   // Scale Factor for power consumed in D3 state    cfg[591:584]

   parameter   PWR_DIS_D0_STATE = 8'h1E,        // Power dissipated in D0 state                   cfg[599:592]

   parameter   DIS_SCL_FCTR_D0_STATE = 8'h01,   // Scale Factor for power dissipated in D0 state  cfg[607:600]

   parameter   PWR_DIS_D1_STATE = 8'h1E,        // Power dissipated in D1 state                   cfg[615:608]

   parameter   DIS_SCL_FCTR_D1_STATE = 8'h01,   // Scale Factor for power dissipated in D1 state  cfg[623:616]

   parameter   PWR_DIS_D2_STATE = 8'h1E,        // Power dissipated in D2 state                   cfg[631:624]

   parameter   DIS_SCL_FCTR_D2_STATE = 8'h01,   // Scale Factor for power dissipated in D2 state  cfg[639:632]

   parameter   PWR_DIS_D3_STATE = 8'h1E,        // Power dissipated in D3 state                   cfg[647:640]

   parameter   DIS_SCL_FCTR_D3_STATE = 8'h01,   // Scale Factor for power dissipated in D3 state  cfg[655:648]

   parameter   TXDIFFBOOST = "FALSE",

   parameter   GTDEBUGPORTS = 0

)

(

  // System Interface

  input wire          sys_clk,

  input wire          sys_reset_n,

  // PCIe Interface

  input  wire  [MAX_LNK_WDT - 1: 0] pci_exp_rxn,

  input  wire  [MAX_LNK_WDT - 1: 0] pci_exp_rxp,

  output wire  [MAX_LNK_WDT - 1: 0] pci_exp_txn,

  output wire  [MAX_LNK_WDT - 1: 0] pci_exp_txp,

  // Configuration Interface

  output      [31:0] cfg_do,

  input wire  [31:0] cfg_di,

  input wire   [3:0] cfg_byte_en_n,

  input wire   [9:0] cfg_dwaddr,

  output             cfg_rd_wr_done_n,

  input wire         cfg_wr_en_n,

  input wire         cfg_rd_en_n,

  input wire         cfg_err_cor_n,

  input wire         cfg_err_ur_n,

  input wire         cfg_err_ecrc_n,

  input wire         cfg_err_cpl_timeout_n,

  input wire         cfg_err_cpl_abort_n,

  input wire         cfg_err_cpl_unexpect_n,

  input wire         cfg_err_posted_n,

  input wire         cfg_err_locked_n,

  input wire         cfg_interrupt_n,

  output             cfg_interrupt_rdy_n,

   input wire                                  cfg_interrupt_assert_n,

   input         [7:0]                         cfg_interrupt_di,

   output    [7:0]                             cfg_interrupt_do,

   output    [2:0]                             cfg_interrupt_mmenable,

   output                                      cfg_interrupt_msienable,

  input wire         cfg_turnoff_ok_n,

  output             cfg_to_turnoff_n,

  input wire         cfg_pm_wake_n,

  input wire  [47:0] cfg_err_tlp_cpl_header,

  output             cfg_err_cpl_rdy_n,

  input       [63:0] cfg_dsn,

  input wire         cfg_trn_pending_n,

  output      [15:0] cfg_status,

  output      [15:0] cfg_command,

  output      [15:0] cfg_dstatus,

  output      [15:0] cfg_dcommand,

  output      [15:0] cfg_lstatus,

  output      [15:0] cfg_lcommand,

  output       [7:0] cfg_bus_number,

  output       [4:0] cfg_device_number,

  output       [2:0] cfg_function_number,

  output       [2:0] cfg_pcie_link_state_n,

  // Transaction Tx Interface

  input  wire [63:0] trn_td,

  input  wire [7:0]  trn_trem_n,

  input  wire        trn_tsof_n,

  input              trn_teof_n,

  input              trn_tsrc_rdy_n,

  input              trn_tsrc_dsc_n,

  input              trn_terrfwd_n,

  output             trn_tdst_rdy_n,

  output             trn_tdst_dsc_n,

  output      [3:0]  trn_tbuf_av,

 `ifdef PFC_CISCO_DEBUG

  output      [7:0]  trn_pfc_nph_cl,

  output      [11:0] trn_pfc_npd_cl,

  output      [7:0]  trn_pfc_ph_cl,

  output      [11:0] trn_pfc_pd_cl,

  output      [7:0]  trn_pfc_cplh_cl,

  output      [11:0] trn_pfc_cpld_cl,

 `endif

   // Transaction Rx Interface

  input  wire        trn_rnp_ok_n,

  input  wire        trn_rdst_rdy_n,

  output      [63:0] trn_rd,

  output      [7:0]  trn_rrem_n,

  output             trn_rsof_n,

  output             trn_reof_n,

  output             trn_rsrc_rdy_n,

  output             trn_rsrc_dsc_n,

  output             trn_rerrfwd_n,

  output      [6:0]  trn_rbar_hit_n,

  output      [7:0]  trn_rfc_nph_av,

  output      [11:0] trn_rfc_npd_av,

  output      [7:0]  trn_rfc_ph_av,

  output      [11:0] trn_rfc_pd_av,

  output      [7:0]  trn_rfc_cplh_av,

  output      [11:0] trn_rfc_cpld_av,

  input              trn_rcpl_streaming_n,

`ifdef GTP_DEBUG

  //Debugging Ports

  output             GTPCLK_bufg,

  output             REFCLK_OUT_bufg,

  output             LINK_UP,

  output             clock_lock,

  output             pll_lock,

  output             core_clk,

  output             user_clk,

`endif

  output             refclkout,

  input                            gt_dclk,

  input     [MAX_LNK_WDT*7-1:0]    gt_daddr,

  input     [MAX_LNK_WDT-1:0]      gt_den,

  input     [MAX_LNK_WDT-1:0]      gt_dwen,

  input     [MAX_LNK_WDT*16-1:0]   gt_di,

  output    [MAX_LNK_WDT*16-1:0]   gt_do,

  output    [MAX_LNK_WDT-1:0]      gt_drdy,

  input     [2:0]                  gt_txdiffctrl_0,

  input     [2:0]                  gt_txdiffctrl_1,

  input     [2:0]                  gt_txbuffctrl_0,

  input     [2:0]                  gt_txbuffctrl_1,

  input     [2:0]                  gt_txpreemphesis_0,

  input     [2:0]                  gt_txpreemphesis_1,

   // Transaction Common Interface

  output             trn_clk,

  output             trn_reset_n,

  output             trn_lnk_up_n,

  input              fast_train_simulation_only

);

  // Reset wire

  wire fe_fundamental_reset_n;

// Inputs to the pcie core

  wire         fe_compliance_avoid = 1'b0;

  wire         fe_l0_cfg_loopback_master = 1'b0;

  wire         fe_l0_transactions_pending;

  wire         fe_l0_set_completer_abort_error = 1'b0;

  wire         fe_l0_set_detected_corr_error;

  wire         fe_l0_set_detected_fatal_error;

  wire         fe_l0_set_detected_nonfatal_error;

  wire         fe_l0_set_link_detected_parity_error = 1'b0;

  wire         fe_l0_set_link_master_data_parity = 1'b0;

  wire         fe_l0_set_link_received_master_abort = 1'b0;

  wire         fe_l0_set_link_received_target_abort = 1'b0;

  wire         fe_l0_set_link_system_error = 1'b0;

  wire         fe_l0_set_link_signalled_target_abort = 1'b0;

  wire         fe_l0_set_user_detected_parity_error;

  wire         fe_l0_set_user_master_data_parity;

  wire         fe_l0_set_user_received_master_abort;

  wire         fe_l0_set_user_received_target_abort;

  wire         fe_l0_set_user_system_error;

  wire         fe_l0_set_user_signalled_target_abort;

  wire         fe_l0_set_unexpected_completion_uncorr_error = 1'b0;

  wire         fe_l0_set_unexpected_completion_corr_error = 1'b0;

  wire         fe_l0_set_unsupported_request_nonposted_error = 1'b0;

  wire         fe_l0_set_unsupported_request_other_error;

  wire [127:0] fe_l0_packet_header_from_user = 128'b0;

  wire         fe_main_power = 1'b1;

  wire         fe_l0_set_completion_timeout_uncorr_error = 1'b0;

  wire         fe_l0_set_completion_timeout_corr_error = 1'b0;

  wire [3:0]   fe_l0_msi_request0; // = 4'h0;

  wire         fe_l0_legacy_int_funct0; // = 1'b0;

  wire [10:0]  mgmt_addr;

  wire         mgmt_rden;

  // Outputs from the pcie core

  wire [12:0]  fe_l0_completer_id;

  wire [2:0]   maxp;

  wire         fe_l0_rx_dll_tlp_ecrc_ok;

  wire         fe_l0_dll_tx_pm_dllp_outstanding;

  wire         fe_l0_first_cfg_write_occurred;

  wire         fe_l0_cfg_loopback_ack;

  wire         fe_l0_mac_upstream_downstream;

  wire [1:0]   fe_l0_rx_mac_link_error;

  wire [1:0]   fe_l0_rx_mac_link_error_ext;

  wire         fe_l0_mac_link_up;

  wire [3:0]   fe_l0_mac_negotiated_link_width;

  wire         fe_l0_mac_link_training;

  wire [3:0]   fe_l0_ltssm_state;

  wire [7:0]   fe_l0_dll_vc_status;

  wire [7:0]   fe_l0_dl_up_down;

  wire [6:0]   fe_l0_dll_error_vector;

  wire [6:0]   fe_l0_dll_error_vector_ext;

  wire [1:0]   fe_l0_dll_as_rx_state;

  wire         fe_l0_dll_as_tx_state;

  wire         fe_l0_as_autonomous_init_completed;

  wire         fe_l0_unlock_received;

  wire         fe_l0_corr_err_msg_rcvd;

  wire         fe_l0_fatal_err_msg_rcvd;

  wire         fe_l0_nonfatal_err_msg_rcvd;

  wire [15:0]  fe_l0_err_msg_req_id;

  wire         fe_l0_fwd_corr_err_out;

  wire         fe_l0_fwd_fatal_err_out;

  wire         fe_l0_fwd_nonfatal_err_out;

  wire         fe_l0_received_assert_inta_legacy_int;

  wire         fe_l0_received_assert_intb_legacy_int;

  wire         fe_l0_received_assert_intc_legacy_int;

  wire         fe_l0_received_assert_intd_legacy_int;

  wire         fe_l0_received_deassert_inta_legacy_int;

  wire         fe_l0_received_deassert_intb_legacy_int;

  wire         fe_l0_received_deassert_intc_legacy_int;

  wire         fe_l0_received_deassert_intd_legacy_int;

  wire         fe_l0_msi_enable0;

  wire [2:0]   fe_l0_multi_msg_en0;

  wire         fe_l0_stats_dllp_received;

  wire         fe_l0_stats_dllp_transmitted;

  wire         fe_l0_stats_os_received;

  wire         fe_l0_stats_os_transmitted;

  wire         fe_l0_stats_tlp_received;

  wire         fe_l0_stats_tlp_transmitted;

  wire         fe_l0_stats_cfg_received;

  wire         fe_l0_stats_cfg_transmitted;

  wire         fe_l0_stats_cfg_other_received;

  wire         fe_l0_stats_cfg_other_transmitted;

  wire [1:0]   fe_l0_attention_indicator_control;

  wire [1:0]   fe_l0_power_indicator_control;

  wire         fe_l0_power_controller_control;

  wire         fe_l0_toggle_electromechanical_interlock;

  wire         fe_l0_rx_beacon;

  wire [1:0]   fe_l0_pwr_state0;

  wire         fe_l0_pme_req_in;

  wire         fe_l0_pme_ack;

  wire         fe_l0_pme_req_out;

  wire         fe_l0_pme_en;

  wire         fe_l0_pwr_inhibit_transfers;

  wire         fe_l0_pwr_l1_state;

  wire         fe_l0_pwr_l23_ready_device;

  wire         fe_l0_pwr_l23_ready_state;

  wire         fe_l0_pwr_tx_l0s_state;

  wire         fe_l0_pwr_turn_off_req;

  wire         fe_l0_rx_dll_pm;

  wire [2:0]   fe_l0_rx_dll_pm_type;

  wire         fe_l0_tx_dll_pm_updated;

  wire         fe_l0_mac_new_state_ack;

  wire         fe_l0_mac_rx_l0s_state;

  wire         fe_l0_mac_entered_l0;

  wire         fe_l0_dll_rx_ack_outstanding;

  wire         fe_l0_dll_tx_outstanding;

  wire         fe_l0_dll_tx_non_fc_outstanding;

  wire [1:0]   fe_l0_rx_dll_tlp_end;

  wire         fe_l0_tx_dll_sbfc_updated;

  wire [18:0]  fe_l0_rx_dll_sbfc_data;

  wire         fe_l0_rx_dll_sbfc_update;

  wire [7:0]   fe_l0_tx_dll_fc_npost_byp_updated;

  wire [7:0]   fe_l0_tx_dll_fc_post_ord_updated;

  wire [7:0]   fe_l0_tx_dll_fc_cmpl_mc_updated;

  wire [19:0]  fe_l0_rx_dll_fc_npost_byp_cred;

  wire [7:0]   fe_l0_rx_dll_fc_npost_byp_update;

  wire [23:0]  fe_l0_rx_dll_fc_post_ord_cred;

  wire [7:0]   fe_l0_rx_dll_fc_post_ord_update;

  wire [23:0]  fe_l0_rx_dll_fc_cmpl_mc_cred;

  wire [7:0]   fe_l0_rx_dll_fc_cmpl_mc_update;

  wire [3:0]   fe_l0_uc_byp_found;

  wire [3:0]   fe_l0_uc_ord_found;

  wire [2:0]   fe_l0_mc_found;

  wire [2:0]   fe_l0_transformed_vc;

  wire [2:0]  mem_tx_tc_select;

  wire [1:0]  mem_tx_fifo_select;

  wire [1:0]  mem_tx_enable;

  wire        mem_tx_header;

  wire        mem_tx_first;

  wire        mem_tx_last;

  wire        mem_tx_discard;

  wire [63:0] mem_tx_data;

  wire        mem_tx_complete;

  wire [2:0]  mem_rx_tc_select;

  wire [1:0]  mem_rx_fifo_select;

  wire        mem_rx_request;

  wire [31:0] mem_debug;

  wire [7:0]  fe_rx_posted_available;

  wire [7:0]  fe_rx_non_posted_available;

  wire [7:0]  fe_rx_completion_available;

  wire        fe_rx_config_available;

  wire [7:0]  fe_rx_posted_partial;

  wire [7:0]  fe_rx_non_posted_partial;

  wire [7:0]  fe_rx_completion_partial;

  wire        fe_rx_config_partial;

  wire        fe_rx_request_end;

  wire [1:0]  fe_rx_valid;

  wire        fe_rx_header;

  wire        fe_rx_first;

  wire        fe_rx_last;

  wire        fe_rx_discard;

  wire [63:0] fe_rx_data;

  wire [7:0]  fe_tc_status;

  wire [7:0]  fe_tx_posted_ready;

  wire [7:0]  fe_tx_non_posted_ready;

  wire [7:0]  fe_tx_completion_ready;

  wire        fe_tx_config_ready;

  wire [7:0]  fe_leds_out;

  wire        fe_io_space_enable;

  wire        fe_mem_space_enable;

  wire        fe_bus_master_enable;

  wire        fe_parity_error_response;

  wire        fe_serr_enable;

  wire        fe_interrupt_disable;

  wire        fe_ur_reporting_enable;

  wire [2:0]  fe_max_payload_size;

  wire [2:0]  fe_max_read_request_size;

  wire [31:0] mgmt_rdata;

  wire [31:0] mgmt_wdata;

  wire [3:0]  mgmt_bwren;

  wire [16:0] mgmt_pso;

  wire [6:0]  mgmt_stats_credit_sel;

  wire [11:0] mgmt_stats_credit;

  // Local Link Transmit

  wire [7:0]  llk_tc_status;

  wire [63:0] llk_tx_data;

  wire [9:0]  llk_tx_chan_space;

  wire [1:0]  llk_tx_enable_n;

  wire [2:0]  llk_tx_ch_tc;

  wire [1:0]  llk_tx_ch_fifo;

  wire [7:0]  llk_tx_ch_posted_ready_n;

  wire [7:0]  llk_tx_ch_non_posted_ready_n;

  wire [7:0]  llk_tx_ch_completion_ready_n;

  wire        llk_rx_src_last_req_n;

  wire        llk_rx_dst_req_n;

  wire        llk_rx_dst_cont_req_n;

  // Local Link Receive

  wire [63:0] llk_rx_data;

  wire [1:0]  llk_rx_valid_n;

  wire [2:0]  llk_rx_ch_tc;

  wire [1:0]  llk_rx_ch_fifo;

  wire [15:0] llk_rx_preferred_type;

  wire [7:0]  llk_rx_ch_posted_available_n;

  wire [7:0]  llk_rx_ch_non_posted_available_n;

  wire [7:0]  llk_rx_ch_completion_available_n;

  wire [7:0]  llk_rx_ch_posted_partial_n;