OpenCores
URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [pcie_gt_wrapper.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dsmv 
 
2 
//-----------------------------------------------------------------------------
3 
//
4 
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
5 
//
6 
// This file contains confidential and proprietary information
7 
// of Xilinx, Inc. and is protected under U.S. and
8 
// international copyright and other intellectual property
9 
// laws.
10 
//
11 
// DISCLAIMER
12 
// This disclaimer is not a license and does not grant any
13 
// rights to the materials distributed herewith. Except as
14 
// otherwise provided in a valid license issued to you by
15 
// Xilinx, and to the maximum extent permitted by applicable
16 
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
17 
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
18 
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
19 
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
20 
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
21 
// (2) Xilinx shall not be liable (whether in contract or tort,
22 
// including negligence, or under any other theory of
23 
// liability) for any loss or damage of any kind or nature
24 
// related to, arising under or in connection with these
25 
// materials, including for any direct, or any indirect,
26 
// special, incidental, or consequential loss or damage
27 
// (including loss of data, profits, goodwill, or any type of
28 
// loss or damage suffered as a result of any action brought
29 
// by a third party) even if such damage or loss was
30 
// reasonably foreseeable or Xilinx had been advised of the
31 
// possibility of the same.
32 
//
33 
// CRITICAL APPLICATIONS
34 
// Xilinx products are not designed or intended to be fail-
35 
// safe, or for use in any application requiring fail-safe
36 
// performance, such as life-support or safety devices or
37 
// systems, Class III medical devices, nuclear facilities,
38 
// applications related to the deployment of airbags, or any
39 
// other applications that could lead to death, personal
40 
// injury, or severe property or environmental damage
41 
// (individually and collectively, "Critical
42 
// Applications"). Customer assumes the sole risk and
43 
// liability of any use of Xilinx products in Critical
44 
// Applications, subject only to applicable laws and
45 
// regulations governing limitations on product liability.
46 
//
47 
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
48 
// PART OF THIS FILE AT ALL TIMES.
49 
//
50 
//-----------------------------------------------------------------------------
51 
// Project    : V5-Block Plus for PCI Express
52 
// File       : pcie_gt_wrapper.v
53 
//--------------------------------------------------------------------------------
54 
//--------------------------------------------------------------------------------
55 
//
56 
//   ____  ____
57 
//  /   /\/   /
58 
// /___/  \  /    Vendor      : Xilinx
59 
// \   \   \/     Version     : 1.6
60 
//  \   \         Application : Generated by Xilinx PCI Express Wizard
61 
//  /   /         Filename    : pcie_gt_wrapper.v
62 
// /___/   /\     Module      : pcie_gt_wrapper
63 
// \   \  /  \
64 
//  \___\/\___\
65 
//
66 
//------------------------------------------------------------------------------
67 
//
68 
//  Description : Wrapper for Rocket IO GTP Transceivers
69 
//
70 
//-----------------------------------------------------------------------------
71 
 
72 
module pcie_gt_wrapper #
73 
   (
74 
     parameter NO_OF_LANES = 8,
75 
     parameter SIM = 0,
76 
     parameter PLL_DIVSEL_FB = 5,
77 
     parameter PLL_DIVSEL_REF = 2,
78 
     parameter CLK25_DIVIDER = 4,
79 
     parameter TXDIFFBOOST = "TRUE"
80 
   )
81 
   (
82 
      //RX signals
83 
      output  wire   [7:0]                gt_rx_elec_idle,
84 
      output  wire   [23:0]               gt_rx_status,
85 
      output  wire   [63:0]               gt_rx_data,
86 
      output  wire   [7:0]                gt_rx_phy_status,
87 
      output  wire   [7:0]                gt_rx_data_k,
88 
      output  wire   [7:0]                gt_rx_valid,
89 
      output  wire   [7:0]                gt_rx_chanisaligned,
90 
      input   wire   [NO_OF_LANES-1:0]    gt_rx_n,
91 
      input   wire   [NO_OF_LANES-1:0]    gt_rx_p,
92 
 
93 
      //TX signals
94 
      output  wire   [NO_OF_LANES-1:0]    gt_tx_n,
95 
      output  wire   [NO_OF_LANES-1:0]    gt_tx_p,
96 
      input   wire   [63:0]               gt_tx_data,
97 
      input   wire   [7:0]                gt_tx_data_k,
98 
      input   wire   [7:0]                gt_tx_elec_idle,
99 
      input   wire   [7:0]                gt_tx_detect_rx_loopback,
100 
      input   wire   [7:0]                gt_tx_compliance,
101 
      input   wire   [7:0]                gt_rx_polarity,
102 
      input   wire   [15:0]               gt_power_down,
103 
      input   wire   [7:0]                gt_deskew_lanes,
104 
      input   wire   [7:0]                gt_pipe_reset,
105 
      input   wire   [7:0]                gt_rx_present,
106 
 
107 
      //Reset signals
108 
      input   wire                        gsr,
109 
      input   wire                        gtreset,
110 
      input   wire                        clock_lock,
111 
      //Refclk signals
112 
      input   wire                        refclk,
113 
      output  wire                        refclkout_bufg,
114 
      output  wire                        gtclk_bufg,
115 
      output  wire  [7:0]                 resetdone,
116 
      output  wire  [3:0]                 plllkdet_out,
117 
      input   wire                        gt_usrclk,
118 
      output  wire  [7:0]                 rxbyteisaligned,
119 
      output  wire  [7:0]                 rxchanbondseq,
120 
 
121 
      output  wire                        pcie_reset,
122 
 
123 
      //Dynamic reconfiguration port (DRP)
124 
      input   wire                        gt_dclk,
125 
      input   wire   [NO_OF_LANES*7-1:0]  gt_daddr,
126 
      input   wire   [NO_OF_LANES-1:0]    gt_den,
127 
      input   wire   [NO_OF_LANES-1:0]    gt_dwen,
128 
      input   wire   [NO_OF_LANES*16-1:0] gt_di,
129 
      output  wire   [NO_OF_LANES*16-1:0] gt_do,
130 
      output  wire   [NO_OF_LANES-1:0]    gt_drdy,
131 
 
132 
      input   wire   [2:0]                gt_txdiffctrl_0,
133 
      input   wire   [2:0]                gt_txdiffctrl_1,
134 
      input   wire   [2:0]                gt_txbuffctrl_0,
135 
      input   wire   [2:0]                gt_txbuffctrl_1,
136 
      input   wire   [2:0]                gt_txpreemphesis_0,
137 
      input   wire   [2:0]                gt_txpreemphesis_1
138 
   );
139 
 
140 
 
141 
/************************** Start of GT instantiation *************************/
142 
 
143 
     //Signal declaration
144 
     wire [NO_OF_LANES-1:0] gt_clk;
145 
     wire [NO_OF_LANES-1:0] gt_refclk_out;
146 
     wire [7:0] gt_rx_enchansync  = 8'h01;
147 
 
148 
 
149 
     wire [2:0] gt_rx_chbond_i [8:0];
150 
     wire [2:0] gt_rx_chbond_o [8:0];
151 
 
152 
     wire [7:0] float_rx_data_k = 8'b0;
153 
     wire [63:0] float_rx_data = 64'b0;
154 
 
155 
 
156 
     wire [7:0] GT_TXN,GT_RXN;
157 
     wire [7:0] GT_TXP,GT_RXP;
158 
     wire [7:0] rTXN;
159 
     wire [7:0] rTXP;
160 
 
161 
     wire [7:0] gt_rx_elec_idle_reset;
162 
     wire [3:0] gt_rx_en_elec_idle_resetb;
163 
 
164 
     wire [63:0]   gt_rx_data_reg;
165 
     wire [7:0]    gt_rx_data_k_reg;
166 
     wire [7:0]    gt_rx_valid_reg;
167 
     wire [7:0]    gt_rx_elec_idle_reg;
168 
     wire [23:0]   gt_rx_status_reg;
169 
     wire [7:0]    gt_rx_phy_status_reg;
170 
     wire [7:0]    gt_rx_chanisaligned_reg;
171 
     wire  [7:0]    gt_pipe_reset_reg;
172 
     wire  [15:0]   gt_rx_power_down_reg;
173 
     wire  [7:0]    gt_rx_polarity_reg;
174 
     wire [63:0]   gt_tx_data_reg;
175 
     wire [7:0]    gt_tx_data_k_reg;
176 
     wire [7:0]    gt_tx_elec_idle_reg;
177 
     wire [7:0]    gt_tx_detect_rx_loopback_reg;
178 
     wire [7:0]    gt_tx_compliance_reg;
179 
     wire [15:0]   gt_tx_power_down_reg;
180 
 
181 
     reg [7:0]     one  = 8'hff;
182 
     reg [63:0]    zero = 63'h0000000000000000;
183 
 
184 
     wire rst_init = gt_pipe_reset_reg[0];
185 
     wire  rxreset_i; // connect to RXRESET of the GT inputs
186 
     reg  rxreset;
187 
     reg  m1_delayed_elec_idle_reset;
188 
     reg  m2_delayed_elec_idle_reset;
189 
     reg  delayed_elec_idle_reset;
190 
 
191 
 
192 
//////////////////////////////////////////////////////////
193 
// Flop Locations for GT TX signals
194 
// Registering TX side signals
195 
/////////////////////////////////////////////////////////
196 
 
197 
     genvar a;
198 
     generate
199 
     for ( a=0; a < NO_OF_LANES ; a=a+1)
200 
     begin: flop
201 
 
202 
     FD tx_data0 ( .Q (gt_tx_data_reg[8*a+0]), .D (gt_tx_data[8*a+0]), .C(gt_usrclk));
203 
     FD tx_data1 ( .Q (gt_tx_data_reg[8*a+1]), .D (gt_tx_data[8*a+1]), .C(gt_usrclk));
204 
     FD tx_data2 ( .Q (gt_tx_data_reg[8*a+2]), .D (gt_tx_data[8*a+2]), .C(gt_usrclk));
205 
     FD tx_data3 ( .Q (gt_tx_data_reg[8*a+3]), .D (gt_tx_data[8*a+3]), .C(gt_usrclk));
206 
     FD tx_data4 ( .Q (gt_tx_data_reg[8*a+4]), .D (gt_tx_data[8*a+4]), .C(gt_usrclk));
207 
     FD tx_data5 ( .Q (gt_tx_data_reg[8*a+5]), .D (gt_tx_data[8*a+5]), .C(gt_usrclk));
208 
     FD tx_data6 ( .Q (gt_tx_data_reg[8*a+6]), .D (gt_tx_data[8*a+6]), .C(gt_usrclk));
209 
     FD tx_data7 ( .Q (gt_tx_data_reg[8*a+7]), .D (gt_tx_data[8*a+7]), .C(gt_usrclk));
210 
 
211 
     FD tx_data_k    ( .Q (gt_tx_data_k_reg[a]),     .D (gt_tx_data_k[a]),     .C(gt_usrclk));
212 
 
213 
     FDCP #(.INIT(1'b1)) tx_elec_idle  ( .Q (gt_tx_elec_idle_reg[a]),  .D (gt_tx_elec_idle[a]),  .C(gt_usrclk), .CLR(1'b0), .PRE(~clock_lock));
214 
 
215 
     FD tx_compliance( .Q (gt_tx_compliance_reg[a]), .D (gt_tx_compliance[a]), .C(gt_usrclk));
216 
 
217 
     FD tx_detect_rx_loopback ( .Q (gt_tx_detect_rx_loopback_reg[a]), .D (gt_tx_detect_rx_loopback[a]), .C(gt_usrclk));
218 
 
219 
     FDCP #(.INIT(1'b1)) tx_power_down0 ( .Q (gt_tx_power_down_reg[2*a+0]),  .D (gt_power_down[2*a+0]),  .C(gt_usrclk), .CLR(1'b0), .PRE(~clock_lock));
220 
     FDCP #(.INIT(1'b0)) tx_power_down1 ( .Q (gt_tx_power_down_reg[2*a+1]),  .D (gt_power_down[2*a+1]),  .C(gt_usrclk), .CLR(~clock_lock), .PRE(1'b0));
221 
 
222 
     FDCP #(.INIT(1'b1)) rx_power_down0 ( .Q (gt_rx_power_down_reg[2*a+0]),  .D (gt_power_down[2*a+0]),  .C(gt_usrclk), .CLR(1'b0), .PRE(~clock_lock));
223 
     FDCP #(.INIT(1'b0)) rx_power_down1 ( .Q (gt_rx_power_down_reg[2*a+1]),  .D (gt_power_down[2*a+1]),  .C(gt_usrclk), .CLR(~clock_lock), .PRE(1'b0));
224 
 
225 
     FD rx_polarity      ( .Q (gt_rx_polarity_reg[a]),   .D (gt_rx_polarity[a]),   .C(gt_usrclk));
226 
 
227 
     FDCP #(.INIT(1'b1)) reset          ( .Q (gt_pipe_reset_reg[a]),    .D (gt_pipe_reset[a]),    .C(gt_usrclk), .CLR(1'b0), .PRE(~clock_lock));
228 
 
229 
     FD rx_data_0        ( .Q (gt_rx_data[8*a+0]),    .D (gt_rx_data_reg[8*a+0]),     .C(gt_usrclk));
230 
     FD rx_data_1        ( .Q (gt_rx_data[8*a+1]),    .D (gt_rx_data_reg[8*a+1]),     .C(gt_usrclk));
231 
     FD rx_data_2        ( .Q (gt_rx_data[8*a+2]),    .D (gt_rx_data_reg[8*a+2]),     .C(gt_usrclk));
232 
     FD rx_data_3        ( .Q (gt_rx_data[8*a+3]),    .D (gt_rx_data_reg[8*a+3]),     .C(gt_usrclk));
233 
     FD rx_data_4        ( .Q (gt_rx_data[8*a+4]),    .D (gt_rx_data_reg[8*a+4]),     .C(gt_usrclk));
234 
     FD rx_data_5        ( .Q (gt_rx_data[8*a+5]),    .D (gt_rx_data_reg[8*a+5]),     .C(gt_usrclk));
235 
     FD rx_data_6        ( .Q (gt_rx_data[8*a+6]),    .D (gt_rx_data_reg[8*a+6]),     .C(gt_usrclk));
236 
     FD rx_data_7        ( .Q (gt_rx_data[8*a+7]),    .D (gt_rx_data_reg[8*a+7]),     .C(gt_usrclk));
237 
 
238 
     FD rx_data_k        ( .Q (gt_rx_data_k[a]),      .D (gt_rx_data_k_reg[a]),       .C(gt_usrclk));
239 
 
240 
     FDCP #(.INIT(1'b1)) rx_elec_idle   ( .Q (gt_rx_elec_idle[a]),   .D (gt_rx_elec_idle_reg[a]),    .C(gt_usrclk), .CLR(1'b0), .PRE(~clock_lock));
241 
     FD rx_valid         ( .Q (gt_rx_valid[a]),       .D (gt_rx_valid_reg[a]),        .C(gt_usrclk));
242 
 
243 
     FDCP #(.INIT(1'b1)) rx_phy_status  ( .Q (gt_rx_phy_status[a]),    .D (gt_rx_phy_status_reg[a]),      .C(gt_usrclk), .CLR(1'b0), .PRE(~clock_lock));
244 
     FD rx_chanisaligned ( .Q (gt_rx_chanisaligned[a]), .D (gt_rx_chanisaligned_reg[a]),   .C(gt_usrclk));
245 
 
246 
     FD rx_status_0      ( .Q (gt_rx_status[3*a+0]),  .D (gt_rx_status_reg[3*a+0]),   .C(gt_usrclk));
247 
     FD rx_status_1      ( .Q (gt_rx_status[3*a+1]),  .D (gt_rx_status_reg[3*a+1]),   .C(gt_usrclk));
248 
     FD rx_status_2      ( .Q (gt_rx_status[3*a+2]),  .D (gt_rx_status_reg[3*a+2]),   .C(gt_usrclk));
249 
 
250 
 
251 
    end
252 
    endgenerate
253 
 
254 
    genvar b;
255 
    generate
256 
    for (b=NO_OF_LANES; b < 8; b=b+1)
257 
    begin: tied_off
258 
        assign gt_tx_data_reg[8*b+7:8*b+0]          = 8'b0;
259 
        assign gt_tx_data_k_reg[b]                  = 1'b0;
260 
        assign gt_tx_elec_idle_reg[b]               = 1'b1;
261 
        assign gt_tx_detect_rx_loopback_reg[b]      = 1'b0;
262 
        assign gt_tx_compliance_reg[b]              = 1'b0;
263 
        assign gt_tx_power_down_reg[2*b+1:2*b+0]    = 2'b0;
264 
        assign gt_rx_power_down_reg[2*b+1:2*b+0]    = 2'b0;
265 
        assign gt_pipe_reset_reg[b]                 = 1'b0;
266 
        assign gt_rx_polarity_reg[b]                = 1'b0;
267 
 
268 
        assign gt_rx_data[8*b+7:8*b+0]              = 8'b0;
269 
        assign gt_rx_data_k[b]                      = 1'b0;
270 
        assign gt_rx_valid[b]                       = 1'b0;
271 
        assign gt_rx_elec_idle[b]                   = 1'b1;
272 
        assign gt_rx_status[3*b+2:3*b]              = 3'b0;
273 
        assign gt_rx_phy_status[b]                  = 1'b0;
274 
        assign gt_rx_chanisaligned[b]               = 1'b0;
275 
 
276 
    end
277 
    endgenerate
278 
 
279 
 
280 
 
281 
     assign rTXN = GT_TXN;
282 
     assign rTXP = GT_TXP;
283 
 
284 
     assign gt_tx_n = rTXN[(NO_OF_LANES-1):0];
285 
     assign gt_tx_p = rTXP[(NO_OF_LANES-1):0];
286 
 
287 
     assign GT_RXN[(NO_OF_LANES-1):0] = gt_rx_n;
288 
     assign GT_RXP[(NO_OF_LANES-1):0] = gt_rx_p;
289 
 
290 
     BUFG bufg1 (.I(gt_clk[0]),        .O(gtclk_bufg));
291 
     BUFG bufg2 (.I(gt_refclk_out[0]), .O(refclkout_bufg));
292 
 
293 
 
294 
// Channel bonding settings. These settings should be changed
295 
// based on how the GTs are daisy chained. For more imformation on channel
296 
// bonding please refer to the V5 Rocket I/O Transceiver User Guide
297 
 
298 
     assign gt_rx_chbond_i[0] = 3'b0;
299 
 
300 
     genvar c;
301 
     generate
302 
     for ( c=0; c <= NO_OF_LANES-1 ; c=c+1)
303 
     begin:  ch_bond
304 
          assign gt_rx_chbond_i[c+1] = (NO_OF_LANES == 1)? 3'b0 : gt_rx_chbond_o[c];
305 
     end
306 
     endgenerate
307 
 
308 
 
309 
wire TXENPMAPHASEALIGN;
310 
wire TXPMASETPHASE;
311 
reg  ignore_resetdone = 1'b0;
312 
wire tx_sync_reset;
313 
reg  resetdone_reg = 1'b0;
314 
wire sync_done;
315 
reg rst_pcie = 1'b1;
316 
reg [2:0] rstdone_cnt = 3'b000;
317 
reg       mgt_txreset;
318 
reg [1:0] mgt_txreset_cnt;
319 
 
320 
     genvar i;
321 
     generate
322 
        for (i=0; i < NO_OF_LANES; i= i+2)
323 
           begin: GTD
324 
              GTP_DUAL #
325 
 
326 
               (
327 
                  .SIM_MODE                   ("FAST"                  ),
328 
                  .SIM_RECEIVER_DETECT_PASS0  ("TRUE"                  ),
329 
                  .SIM_RECEIVER_DETECT_PASS1  ("TRUE"                  ),
330 
                  .SIM_GTPRESET_SPEEDUP       (1                       ),
331 
                  .AC_CAP_DIS_0               ("FALSE"                 ),
332 
                  .AC_CAP_DIS_1               ("FALSE"                 ),
333 
                  .ALIGN_COMMA_WORD_0         (1                       ),
334 
                  .ALIGN_COMMA_WORD_1         (1                       ),
335 
                  .CHAN_BOND_1_MAX_SKEW_0     (7                       ),
336 
                  .CHAN_BOND_1_MAX_SKEW_1     (7                       ),
337 
                  .CHAN_BOND_2_MAX_SKEW_0     (7                       ),
338 
                  .CHAN_BOND_2_MAX_SKEW_1     (7                       ),
339 
                  .CHAN_BOND_LEVEL_0          (NO_OF_LANES==1?0:NO_OF_LANES-(i+1)),
340 
                  .CHAN_BOND_LEVEL_1          (NO_OF_LANES==1?0:NO_OF_LANES-(i+2)),
341 
                  .CHAN_BOND_MODE_0           (NO_OF_LANES==1?"OFF":(i==0)?"MASTER":"SLAVE"),
342 
                  .CHAN_BOND_MODE_1           (NO_OF_LANES==1?"OFF":"SLAVE"),
343 
                  .CHAN_BOND_SEQ_2_USE_0      ("TRUE"                  ),
344 
                  .CHAN_BOND_SEQ_2_USE_1      ("TRUE"                  ),
345 
                  .CHAN_BOND_SEQ_LEN_0        (4                       ),
346 
                  .CHAN_BOND_SEQ_LEN_1        (4                       ),
347 
                  .CLK25_DIVIDER              (CLK25_DIVIDER           ),
348 
                  .CLKINDC_B                  ("TRUE"                  ),
349 
                  .CLK_CORRECT_USE_0          ("TRUE"                  ),
350 
                  .CLK_CORRECT_USE_1          ("TRUE"                  ),
351 
                  .CLK_COR_ADJ_LEN_0          (1                       ),
352 
                  .CLK_COR_ADJ_LEN_1          (1                       ),
353 
                  .CLK_COR_DET_LEN_0          (1                       ),
354 
                  .CLK_COR_DET_LEN_1          (1                       ),
355 
                  .CLK_COR_INSERT_IDLE_FLAG_0 ("FALSE"                 ),
356 
                  .CLK_COR_INSERT_IDLE_FLAG_1 ("FALSE"                 ),
357 
                  .CLK_COR_KEEP_IDLE_0        ("FALSE"                 ),
358 
                  .CLK_COR_KEEP_IDLE_1        ("FALSE"                 ),
359 
                  .CLK_COR_MAX_LAT_0          (18                      ),
360 
                  .CLK_COR_MAX_LAT_1          (18                      ),
361 
                  .CLK_COR_MIN_LAT_0          (16                      ),
362 
                  .CLK_COR_MIN_LAT_1          (16                      ),
363 
                  .CLK_COR_PRECEDENCE_0       ("TRUE"                  ),
364 
                  .CLK_COR_PRECEDENCE_1       ("TRUE"                  ),
365 
                  .CLK_COR_REPEAT_WAIT_0      (5                       ),
366 
                  .CLK_COR_REPEAT_WAIT_1      (5                       ),
367 
                  .CLK_COR_SEQ_2_USE_0        ("FALSE"                 ),
368 
                  .CLK_COR_SEQ_2_USE_1        ("FALSE"                 ),
369 
                  .COMMA_DOUBLE_0             ("FALSE"                 ),
370 
                  .COMMA_DOUBLE_1             ("FALSE"                 ),
371 
                  .DEC_MCOMMA_DETECT_0        ("TRUE"                  ),
372 
                  .DEC_MCOMMA_DETECT_1        ("TRUE"                  ),
373 
                  .DEC_PCOMMA_DETECT_0        ("TRUE"                  ),
374 
                  .DEC_PCOMMA_DETECT_1        ("TRUE"                  ),
375 
                  .DEC_VALID_COMMA_ONLY_0     ("TRUE"                  ),
376 
                  .DEC_VALID_COMMA_ONLY_1     ("TRUE"                  ),
377 
                  .MCOMMA_DETECT_0            ("TRUE"                  ),
378 
                  .MCOMMA_DETECT_1            ("TRUE"                  ),
379 
                  .OOB_CLK_DIVIDER            (4                       ),
380 
                  .OVERSAMPLE_MODE            ("FALSE"                 ),
381 
                  .PCI_EXPRESS_MODE_0         ("TRUE"                  ),
382 
                  .PCI_EXPRESS_MODE_1         ("TRUE"                  ),
383 
                  .PCOMMA_DETECT_0            ("TRUE"                  ),
384 
                  .PCOMMA_DETECT_1            ("TRUE"                  ),
385 
                  .PLL_DIVSEL_FB              (PLL_DIVSEL_FB           ),
386 
                  .PLL_DIVSEL_REF             (PLL_DIVSEL_REF          ),
387 
                  .PLL_RXDIVSEL_OUT_0         (1                       ),
388 
                  .PLL_RXDIVSEL_OUT_1         (1                       ),
389 
                  .PLL_SATA_0                 ("FALSE"                 ),
390 
                  .PLL_SATA_1                 ("FALSE"                 ),
391 
                  .PLL_TXDIVSEL_COMM_OUT      (1                       ),
392 
                  .PLL_TXDIVSEL_OUT_0         (1                       ),
393 
                  .PLL_TXDIVSEL_OUT_1         (1                       ),
394 
 
395 
                  .RCV_TERM_GND_0             ("TRUE"                  ),
396 
                  .RCV_TERM_GND_1             ("TRUE"                  ),
397 
                  .RCV_TERM_MID_0             ("TRUE"                  ),
398 
                  .RCV_TERM_MID_1             ("TRUE"                  ),
399 
                  .RCV_TERM_VTTRX_0           ("FALSE"                 ),
400 
                  .RCV_TERM_VTTRX_1           ("FALSE"                 ),
401 
                  .RX_BUFFER_USE_0            ("TRUE"                  ),
402 
                  .RX_BUFFER_USE_1            ("TRUE"                  ),
403 
                  .RX_DECODE_SEQ_MATCH_0      ("TRUE"                  ),
404 
                  .RX_DECODE_SEQ_MATCH_1      ("TRUE"                  ),
405 
                  .RX_LOSS_OF_SYNC_FSM_0      ("FALSE"                 ),
406 
                  .RX_LOSS_OF_SYNC_FSM_1      ("FALSE"                 ),
407 
                  .RX_LOS_INVALID_INCR_0      (8                       ),
408 
                  .RX_LOS_INVALID_INCR_1      (8                       ),
409 
                  .RX_LOS_THRESHOLD_0         (128                     ),
410 
                  .RX_LOS_THRESHOLD_1         (128                     ),
411 
                  .RX_SLIDE_MODE_0            ("PCS"                   ),
412 
                  .RX_SLIDE_MODE_1            ("PCS"                   ),
413 
                  .RX_STATUS_FMT_0            ("PCIE"                  ),
414 
                  .RX_STATUS_FMT_1            ("PCIE"                  ),
415 
                  .RX_XCLK_SEL_0              ("RXREC"                 ),
416 
                  .RX_XCLK_SEL_1              ("RXREC"                 ),
417 
                  .SATA_MAX_BURST_0           (7                       ),
418 
                  .SATA_MAX_BURST_1           (7                       ),
419 
                  .SATA_MAX_INIT_0            (22                      ),
420 
                  .SATA_MAX_INIT_1            (22                      ),
421 
                  .SATA_MAX_WAKE_0            (7                       ),
422 
                  .SATA_MAX_WAKE_1            (7                       ),
423 
                  .SATA_MIN_BURST_0           (4                       ),
424 
                  .SATA_MIN_BURST_1           (4                       ),
425 
                  .SATA_MIN_INIT_0            (12                      ),
426 
                  .SATA_MIN_INIT_1            (12                      ),
427 
                  .SATA_MIN_WAKE_0            (4                       ),
428 
                  .SATA_MIN_WAKE_1            (4                       ),
429 
                  .TERMINATION_IMP_0          (50                      ),
430 
                  .TERMINATION_IMP_1          (50                      ),
431 
                  .TERMINATION_OVRD           ("FALSE"                 ),
432 
                  .TX_BUFFER_USE_0            ("TRUE"                 ),
433 
                  .TX_BUFFER_USE_1            ("TRUE"                 ),
434 
                  .TX_DIFF_BOOST_0            (TXDIFFBOOST             ), //TRUE
435 
                  .TX_DIFF_BOOST_1            (TXDIFFBOOST             ), //TRUE
436 
                  .TX_SYNC_FILTERB            (1                       ),
437 
                  .TX_XCLK_SEL_0              ("TXOUT"                 ),
438 
                  .TX_XCLK_SEL_1              ("TXOUT"                 ),
439 
                  .CHAN_BOND_SEQ_1_1_0        (10'b0001001010          ), //D10.2 (end TS1)
440 
                  .CHAN_BOND_SEQ_1_1_1        (10'b0001001010          ), //D10.2 (end TS1)
441 
                  .CHAN_BOND_SEQ_1_2_0        (10'b0001001010          ), //D10.2 (end TS1)
442 
                  .CHAN_BOND_SEQ_1_2_1        (10'b0001001010          ), //D10.2 (end TS1)
443 
                  .CHAN_BOND_SEQ_1_3_0        (10'b0001001010          ), //D10.2 (end TS1)
444 
                  .CHAN_BOND_SEQ_1_3_1        (10'b0001001010          ), //D10.2 (end TS1)
445 
                  .CHAN_BOND_SEQ_1_4_0        (10'b0110111100          ), //K28.5 (COM)
446 
                  .CHAN_BOND_SEQ_1_4_1        (10'b0110111100          ), //K28.5 (COM)
447 
                  .CHAN_BOND_SEQ_1_ENABLE_0   (4'b1111                 ), //Look for 4 byte seq
448 
                  .CHAN_BOND_SEQ_1_ENABLE_1   (4'b1111                 ), //Look for 4 byte seq
449 
                  .CHAN_BOND_SEQ_2_1_0        (10'b0100111100          ), //K28.1 (FTS)
450 
                  .CHAN_BOND_SEQ_2_1_1        (10'b0100111100          ), //K28.1 (FTS)
451 
                  .CHAN_BOND_SEQ_2_2_0        (10'b0100111100          ), //K28.1 (FTS)
452 
                  .CHAN_BOND_SEQ_2_2_1        (10'b0100111100          ), //K28.1 (FTS)
453 
                  .CHAN_BOND_SEQ_2_3_0        (10'b0110111100          ), //K28.5 (COM)
454 
                  .CHAN_BOND_SEQ_2_3_1        (10'b0110111100          ), //K28.5 (COM)
455 
                  .CHAN_BOND_SEQ_2_4_0        (10'b0100011100          ), //K28.0 (SKP)
456 
                  .CHAN_BOND_SEQ_2_4_1        (10'b0100011100          ), //K28.0 (SKP)
457 
                  .CHAN_BOND_SEQ_2_ENABLE_0   (4'b1111                 ), //Look for 4 byte seq
458 
                  .CHAN_BOND_SEQ_2_ENABLE_1   (4'b1111                 ), //Look for 4 byte seq
459 
                  .CLK_COR_SEQ_1_1_0          (10'b0100011100          ), //K28.0 (SKP)
460 
                  .CLK_COR_SEQ_1_1_1          (10'b0100011100          ), //K28.0 (SKP)
461 
                  .CLK_COR_SEQ_1_2_0          (10'b0000000000          ),
462 
                  .CLK_COR_SEQ_1_2_1          (10'b0000000000          ),
463 
                  .CLK_COR_SEQ_1_3_0          (10'b0000000000          ),
464 
                  .CLK_COR_SEQ_1_3_1          (10'b0000000000          ),
465 
                  .CLK_COR_SEQ_1_4_0          (10'b0000000000          ),
466 
                  .CLK_COR_SEQ_1_4_1          (10'b0000000000          ),
467 
                  .CLK_COR_SEQ_1_ENABLE_0     (4'b1111                 ),
468 
                  .CLK_COR_SEQ_1_ENABLE_1     (4'b1111                 ),
469 
                  .CLK_COR_SEQ_2_1_0          (10'b0000000000          ),
470 
                  .CLK_COR_SEQ_2_1_1          (10'b0000000000          ),
471 
                  .CLK_COR_SEQ_2_2_0          (10'b0000000000          ),
472 
                  .CLK_COR_SEQ_2_2_1          (10'b0000000000          ),
473 
                  .CLK_COR_SEQ_2_3_0          (10'b0000000000          ),
474 
                  .CLK_COR_SEQ_2_3_1          (10'b0000000000          ),
475 
                  .CLK_COR_SEQ_2_4_0          (10'b0000000000          ),
476 
                  .CLK_COR_SEQ_2_4_1          (10'b0000000000          ),
477 
                  .CLK_COR_SEQ_2_ENABLE_0     (4'b1111                 ),
478 
                  .CLK_COR_SEQ_2_ENABLE_1     (4'b1111                 ),
479 
                  .COMMA_10B_ENABLE_0         (10'b1111111111          ),
480 
                  .COMMA_10B_ENABLE_1         (10'b1111111111          ),
481 
                  .COM_BURST_VAL_0            (4'b1111                 ),
482 
                  .COM_BURST_VAL_1            (4'b1111                 ),
483 
                  .MCOMMA_10B_VALUE_0         (10'b1010000011          ),
484 
                  .MCOMMA_10B_VALUE_1         (10'b1010000011          ),
485 
                  .OOBDETECT_THRESHOLD_0      (3'b010                  ),
486 
                  .OOBDETECT_THRESHOLD_1      (3'b010                  ),
487 
                  .PCOMMA_10B_VALUE_0         (10'b0101111100          ),
488 
                  .PCOMMA_10B_VALUE_1         (10'b0101111100          ),
489 
                  .PCS_COM_CFG                ( (PLL_DIVSEL_FB == 1)? 28'h1680a07 : 28'h1680a0e ),
490 
                  .PMA_CDR_SCAN_0             (27'h6C07640             ),
491 
                  .PMA_CDR_SCAN_1             (27'h6C07640             ),
492 
                  .PMA_RX_CFG_0               (25'h09F0089             ),
493 
                  .PMA_RX_CFG_1               (25'h09F0089             ),
494 
                  .PRBS_ERR_THRESHOLD_0       (32'h00000001            ),
495 
                  .PRBS_ERR_THRESHOLD_1       (32'h00000001            ),
496 
                  .SATA_BURST_VAL_0           (3'b100                  ),
497 
                  .SATA_BURST_VAL_1           (3'b100                  ),
498 
                  .SATA_IDLE_VAL_0            (3'b011                  ),
499 
                  .SATA_IDLE_VAL_1            (3'b011                  ),
500 
                  .TERMINATION_CTRL           (5'b10100                ),
501 
                  .TRANS_TIME_FROM_P2_0       (16'h003C                ),
502 
                  .TRANS_TIME_FROM_P2_1       (16'h003C                ),
503 
                  .TRANS_TIME_NON_P2_0        (16'h0019                ),
504 
                  .TRANS_TIME_NON_P2_1        (16'h0019                ),
505 
                  .TRANS_TIME_TO_P2_0         (16'h0064                ),
506 
                  .TRANS_TIME_TO_P2_1         (16'h0064                ),
507 
                  .TXRX_INVERT_0              (5'b00000                ),
508 
                  .TXRX_INVERT_1              (5'b00000                )
509 
 
510 
 
511 
              )
512 
 
513 
              GT_i(
514 
              // GT_DUAL outputs
515 
              .DO(gt_do[16*i+15:16*i]),
516 
              .DRDY(gt_drdy[i]),
517 
              .PHYSTATUS0(gt_rx_phy_status_reg[i+0]),
518 
              .PHYSTATUS1(gt_rx_phy_status_reg[i+1]),
519 
              .PLLLKDET(plllkdet_out[i/2]),
520 
              .REFCLKOUT(gt_refclk_out[i]),
521 
              .RESETDONE0(resetdone[i]),
522 
              .RESETDONE1(resetdone[i+1]),
523 
              .RXBUFSTATUS0(),
524 
              .RXBUFSTATUS1(),
525 
              .RXBYTEISALIGNED0(rxbyteisaligned[i]),
526 
              .RXBYTEISALIGNED1(rxbyteisaligned[i+1]),
527 
              .RXBYTEREALIGN0(),
528 
              .RXBYTEREALIGN1(),
529 
              .RXCHANBONDSEQ0(rxchanbondseq[i]),
530 
              .RXCHANBONDSEQ1(rxchanbondseq[i+1]),
531 
              .RXCHANISALIGNED0(gt_rx_chanisaligned_reg[i+0]),
532 
              .RXCHANISALIGNED1(gt_rx_chanisaligned_reg[i+1]),
533 
              .RXCHANREALIGN0(),
534 
              .RXCHANREALIGN1(),
535 
              .RXCHARISCOMMA0(),
536 
              .RXCHARISCOMMA1(),
537 
              .RXCHARISK0({float_rx_data_k[i+0],gt_rx_data_k_reg[i+0]}),
538 
              .RXCHARISK1({float_rx_data_k[i+1],gt_rx_data_k_reg[i+1]}),
539 
              .RXCHBONDO0(gt_rx_chbond_o[i]),
540 
              .RXCHBONDO1(gt_rx_chbond_o[i+1]),
541 
              .RXCLKCORCNT0(),
542 
              .RXCLKCORCNT1(),
543 
              .RXCOMMADET0(),
544 
              .RXCOMMADET1(),
545 
              .RXDATA0({float_rx_data[8*i+7:8*i],gt_rx_data_reg[8*i+7:8*i]}),
546 
              .RXDATA1({float_rx_data[8*i+15:8*i+8],gt_rx_data_reg[8*i+15:8*i+8]}),
547 
              .RXDISPERR0(),
548 
              .RXDISPERR1(),
549 
              .RXELECIDLE0(gt_rx_elec_idle_reg[i+0]),
550 
              .RXELECIDLE1(gt_rx_elec_idle_reg[i+1]),
551 
              .RXLOSSOFSYNC0(),
552 
              .RXLOSSOFSYNC1(),
553 
              .RXNOTINTABLE0(),
554 
              .RXNOTINTABLE1(),
555 
              .RXOVERSAMPLEERR0(),
556 
              .RXOVERSAMPLEERR1(),
557 
              .RXPRBSERR0(),
558 
              .RXPRBSERR1(),
559 
              .RXRECCLK0(),
560 
              .RXRECCLK1(),
561 
              .RXRUNDISP0(),
562 
              .RXRUNDISP1(),
563 
              .RXSTATUS0(gt_rx_status_reg[3*i+2:3*i]),
564 
              .RXSTATUS1(gt_rx_status_reg[3*i+5:3*i+3]),
565 
              .RXVALID0(gt_rx_valid_reg[i+0]),
566 
              .RXVALID1(gt_rx_valid_reg[i+1]),
567 
              .TXBUFSTATUS0(),
568 
              .TXBUFSTATUS1(),
569 
              .TXKERR0(),
570 
              .TXKERR1(),
571 
              .TXN0(GT_TXN[i+0]),
572 
              .TXN1(GT_TXN[i+1]),
573 
              .TXOUTCLK0(gt_clk[i]),
574 
              .TXOUTCLK1(),
575 
              .TXP0(GT_TXP[i+0]),
576 
              .TXP1(GT_TXP[i+1]),
577 
              .TXRUNDISP0(),
578 
              .TXRUNDISP1(),
579 
              // GT_DUAL inputs
580 
              .CLKIN(refclk),
581 
              .DADDR(gt_daddr[7*i+6:7*i]),
582 
              .DCLK(gt_dclk),
583 
              .DEN(gt_den[i]),
584 
              .DI(gt_di[16*i+15:16*i]),
585 
              .DWE(gt_dwen[i]),
586 
              .GTPRESET(gtreset),
587 
              .INTDATAWIDTH(1'b1),
588 
              .LOOPBACK0(3'b000),
589 
              .LOOPBACK1( (NO_OF_LANES == 1) ?  3'b010 : 3'b000),
590 
              .PLLLKDETEN(1'b1),
591 
              .PLLPOWERDOWN(1'b0),
592 
              .PRBSCNTRESET0(1'b0),
593 
              .PRBSCNTRESET1(1'b0),
594 
              .REFCLKPWRDNB(1'b1),
595 
              .RXBUFRESET0(1'b0),
596 
              .RXBUFRESET1(1'b0),
597 
              .RXCDRRESET0(gt_pipe_reset_reg[i+0] & ~rst_pcie),
598 
              .RXCDRRESET1(gt_pipe_reset_reg[i+1] & ~rst_pcie),
599 
              .RXCHBONDI0(gt_rx_chbond_i[i]),
600 
              .RXCHBONDI1(gt_rx_chbond_i[i+1]),
601 
              .RXCOMMADETUSE0(1'b1),
602 
              .RXCOMMADETUSE1(1'b1),
603 
              .RXDATAWIDTH0(1'b0),
604 
              .RXDATAWIDTH1(1'b0),
605 
              .RXDEC8B10BUSE0(1'b1),
606 
              .RXDEC8B10BUSE1(1'b1),
607 
              .RXENCHANSYNC0(gt_rx_enchansync[i]),
608 
              .RXENCHANSYNC1(gt_rx_enchansync[i+1]),
609 
              .RXENEQB0(1'b1),
610 
              .RXENEQB1(1'b1),
611 
              .RXENMCOMMAALIGN0(1'b1),
612 
              .RXENMCOMMAALIGN1(1'b1),
613 
              .RXENPCOMMAALIGN0(1'b1),
614 
              .RXENPCOMMAALIGN1(1'b1),
615 
              .RXENPRBSTST0(2'b00),
616 
              .RXENPRBSTST1(2'b00),
617 
              .RXENSAMPLEALIGN0(1'b0),
618 
              .RXENSAMPLEALIGN1(1'b0),
619 
              .RXEQMIX0(2'b01),
620 
              .RXEQMIX1(2'b01),
621 
              .RXEQPOLE0(4'b0000),
622 
              .RXEQPOLE1(4'b0000),
623 
              .RXN0(GT_RXN[i+0]),
624 
              .RXN1(GT_RXN[i+1]),
625 
              .RXP0(GT_RXP[i+0]),
626 
              .RXP1(GT_RXP[i+1]),
627 
              .RXPMASETPHASE0(1'b0),
628 
              .RXPMASETPHASE1(1'b0),
629 
              .RXPOLARITY0(gt_rx_polarity_reg[i+0]),
630 
              .RXPOLARITY1(gt_rx_polarity_reg[i+1]),
631 
              .RXPOWERDOWN0(gt_rx_power_down_reg[2*i+1:2*i]),
632 
              .RXPOWERDOWN1(gt_rx_power_down_reg[2*i+3:2*i+2]),
633 
              .RXRESET0(rxreset_i & ~rst_pcie),
634 
              .RXRESET1(rxreset_i & ~rst_pcie),
635 
              .RXSLIDE0(1'b0),
636 
              .RXSLIDE1(1'b0),
637 
              .RXUSRCLK0(gt_usrclk),
638 
              .RXUSRCLK1(gt_usrclk),
639 
              .RXUSRCLK20(gt_usrclk),
640 
              .RXUSRCLK21(gt_usrclk),
641 
 
642 
              .RXELECIDLERESET0(gt_rx_elec_idle_reset[i]),
643 
              .RXELECIDLERESET1(gt_rx_elec_idle_reset[i+1]),
644 
              .RXENELECIDLERESETB(gt_rx_en_elec_idle_resetb[i/2]),
645 
 
646 
 
647 
              .TXBUFDIFFCTRL0(gt_txbuffctrl_0), //3'b100
648 
              .TXBUFDIFFCTRL1(gt_txbuffctrl_1), //3'b100
649 
              .TXBYPASS8B10B0(2'b00),
650 
              .TXBYPASS8B10B1(2'b00),
651 
              .TXCHARDISPMODE0({1'b0,gt_tx_compliance_reg[i+0]}),
652 
              .TXCHARDISPMODE1({1'b0,gt_tx_compliance_reg[i+1]}),
653 
              .TXCHARDISPVAL0(2'b00),
654 
              .TXCHARDISPVAL1(2'b00),
655 
              .TXCHARISK0({1'b0,gt_tx_data_k_reg[i+0]}),
656 
              .TXCHARISK1({1'b0,gt_tx_data_k_reg[i+1]}),
657 
              .TXCOMSTART0(1'b0),
658 
              .TXCOMSTART1(1'b0),
659 
              .TXCOMTYPE0(1'b0),
660 
              .TXCOMTYPE1(1'b0),
661 
              .TXDATA0({8'b0,gt_tx_data_reg[8*i+7:8*i]}),
662 
              .TXDATA1({8'b0,gt_tx_data_reg[8*i+15:8*i+8]}),
663 
              .TXDATAWIDTH0(1'b0),
664 
              .TXDATAWIDTH1(1'b0),
665 
              .TXDETECTRX0(gt_tx_detect_rx_loopback_reg[i+0]),
666 
              .TXDETECTRX1(gt_tx_detect_rx_loopback_reg[i+1]),
667 
              .TXDIFFCTRL0(gt_txdiffctrl_0), //3'b100
668 
              .TXDIFFCTRL1(gt_txdiffctrl_1), //3'b100
669 
              .TXELECIDLE0(gt_tx_elec_idle_reg[i+0]),
670 
              .TXELECIDLE1(gt_tx_elec_idle_reg[i+1]),
671 
              .TXENC8B10BUSE0(1'b1),
672 
              .TXENC8B10BUSE1(1'b1),
673 
              .TXENPMAPHASEALIGN(TXENPMAPHASEALIGN),
674 
              .TXENPRBSTST0(2'b00),
675 
              .TXENPRBSTST1(2'b00),
676 
              .TXINHIBIT0(1'b0),
677 
              .TXINHIBIT1(1'b0),
678 
              .TXPMASETPHASE(TXPMASETPHASE),
679 
              .TXPOLARITY0(1'b0),
680 
              .TXPOLARITY1(1'b0),
681 
              .TXPOWERDOWN0(gt_tx_power_down_reg[2*i+1:2*i]),
682 
              .TXPOWERDOWN1(gt_tx_power_down_reg[2*i+3:2*i+2]),
683 
              .TXPREEMPHASIS0(gt_txpreemphesis_0), //3'b111
684 
              .TXPREEMPHASIS1(gt_txpreemphesis_1), //3'b111
685 
              .TXRESET0(mgt_txreset & ~rst_pcie),
686 
              .TXRESET1(mgt_txreset & ~rst_pcie),
687 
              .TXUSRCLK0(gt_usrclk),
688 
              .TXUSRCLK1(gt_usrclk),
689 
              .TXUSRCLK20(gt_usrclk),
690 
              .TXUSRCLK21(gt_usrclk),
691 
 
692 
              .GTPTEST(4'b0)
693 
              );
694 
 
695 
           end
696 
     endgenerate
697 
 
698 
 
699 
   //---------------------------- TOGGLE TXRESET ------------------------------
700 
   always @(posedge gt_usrclk)
701 
   begin
702 
      if (sync_done)
703 
      begin
704 
         if (mgt_txreset_cnt < 2'b11)
705 
         begin
706 
            mgt_txreset      <= 1'b1;
707 
            mgt_txreset_cnt  <= mgt_txreset_cnt + 1;
708 
         end
709 
         else
710 
            mgt_txreset      <= 1'b0;
711 
      end
712 
      else
713 
      begin
714 
         mgt_txreset         <= 1'b0;
715 
         mgt_txreset_cnt     <= 2'b0;
716 
      end
717 
   end
718 
 
719 
 
720 
 
721 
 
722 
 
723 
    //---------------------------- TXSYNC module ------------------------------
724 
    // The TXSYNC module performs phase synchronization for all the active TX datapaths. It
725 
    // waits for the user clocks to be stable, then drives the phase align signals on each
726 
    // GTP. When phase synchronization is complete, it asserts SYNC_DONE
727 
 
728 
    // Include the TX_SYNC module in your own design to perform phase synchronization if
729 
    // your protocol bypasses the TX Buffers
730 
 
731 
    TX_SYNC_GTP tile0_txsync_i
732 
    (
733 
        .TXENPMAPHASEALIGN(TXENPMAPHASEALIGN),
734 
        .TXPMASETPHASE(TXPMASETPHASE),
735 
        .SYNC_DONE(sync_done),
736 
        .USER_CLK(gt_usrclk),
737 
        .RESET(tx_sync_reset)
738 
        //.RESET(~resetdone[0])
739 
 
740 
    );
741 
 
742 
 
743 
    always @ (posedge gt_usrclk or posedge gtreset) begin
744 
        if (gtreset === 1'b1 ) begin
745 
            rst_pcie <=  1'b1;
746 
        end else if (sync_done === 1'b1) begin
747 
            rst_pcie <=  1'b0;
748 
        end else begin
749 
            rst_pcie <=  1'b1;
750 
        end
751 
    end
752 
 
753 
    assign tx_sync_reset = (pcie_reset == 1'b1) ? (~clock_lock) : 1'b0;
754 
    assign pcie_reset = rst_pcie;
755 
 
756 
 
757 
///////////////////////////////////////////////////////////////////////////////////////////
758 
// Logic for enabling L0s state
759 
///////////////////////////////////////////////////////////////////////////////////////////
760 
 
761 
 
762 
    always @(posedge gt_usrclk or posedge rst_init) begin
763 
        if (rst_init) begin
764 
          m1_delayed_elec_idle_reset <= 1'b0;
765 
          m2_delayed_elec_idle_reset <= 1'b0;
766 
          delayed_elec_idle_reset    <= 1'b0;
767 
          rxreset <= 1'b0;
768 
        end else begin
769 
          // synchronize elec_idle_reset
770 
          m1_delayed_elec_idle_reset <= gt_rx_elec_idle_reset[0];
771 
          m2_delayed_elec_idle_reset <= m1_delayed_elec_idle_reset;
772 
          delayed_elec_idle_reset    <= m2_delayed_elec_idle_reset;
773 
          // create a one-cycle pulse on rxreset
774 
          rxreset <= ~m2_delayed_elec_idle_reset & delayed_elec_idle_reset;
775 
        end
776 
    end
777 
 
778 
    assign rxreset_i = rxreset;
779 
 
780 
// Latch for CDRRESET for L0s
781 
     wire [7:0]        icdrreset;
782 
     reg  [7:0]        cdrreset = 0;
783 
 
784 
     generate
785 
        genvar j;
786 
          for (j=0; j < 8; j= j+1)
787 
             begin: gen_cdrreset
788 
 
789 
                if (j < NO_OF_LANES) begin: for_GT
790 
                   assign icdrreset[j] = resetdone[j] & gt_rx_elec_idle_reg[j];
791 
 
792 
                   always @( icdrreset or gt_rx_valid_reg) begin : yes_latch
793 
                       if ( icdrreset[j] & ~ gt_rx_valid_reg[j] ) begin
794 
                           cdrreset[j] <= #50 1'b1;
795 
                       end else if ( ~ icdrreset[j] ) begin
796 
                           cdrreset[j] <= #50 1'b0;
797 
                       end
798 
                   end
799 
 
800 
                   assign gt_rx_elec_idle_reset[j] = cdrreset[j];
801 
 
802 
                end else begin : for_tieoff
803 
                   assign icdrreset[j] = 1'b0;
804 
 
805 
                   //synthesis translate_off
806 
                   initial cdrreset[j] <= 1'b0;
807 
                   //synthesis translate_on
808 
 
809 
                   assign gt_rx_elec_idle_reset[j] = 1'b0;
810 
                end
811 
             end
812 
     endgenerate
813 
 
814 
     generate
815 
        genvar k;
816 
          for (k=0; k < 8; k= k+2)
817 
             begin: gen_resetb
818 
                assign gt_rx_en_elec_idle_resetb[k/2] = ~ ( cdrreset[k] | cdrreset[k+1]);
819 
             end
820 
     endgenerate
821 
 
822 
///////////////////////////////////////////////////////////////////////////////////////////
823 
// Tying off signals on unused lanes
824 
///////////////////////////////////////////////////////////////////////////////////////////
825 
 
826 
     generate
827 
         if (NO_OF_LANES == 1 || NO_OF_LANES == 2) begin : laneslt4
828 
           assign plllkdet_out[3:1] = 3'b0;
829 
         end else if (NO_OF_LANES == 4) begin : laneseq4
830 
           assign plllkdet_out[3:2] = 2'b0;
831 
         end
832 
      endgenerate
833 
 
834 
 
835 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.