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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : pcie_gt_wrapper_top.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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// Description : Top-level wrapper for Rocket IO Transceivers that
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// instantiates GTP/GTX transceivers based upon the Virtex-5 family chosen
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//
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//-----------------------------------------------------------------------------
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module pcie_gt_wrapper_top #
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(
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parameter NO_OF_LANES = 1,
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parameter SIM = 0,
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parameter USE_V5FXT = 0,
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parameter REF_CLK_FREQ = 1, // use 0 or 1
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parameter TXDIFFBOOST = "FALSE",
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parameter GTDEBUGPORTS = 0
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)
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(
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output wire [7:0] gt_rx_elec_idle,
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output wire [23:0] gt_rx_status,
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output wire [63:0] gt_rx_data,
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output wire [7:0] gt_rx_phy_status,
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output wire [7:0] gt_rx_data_k,
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output wire [7:0] gt_rx_valid,
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output wire [7:0] gt_rx_chanisaligned,
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input wire [NO_OF_LANES-1:0] gt_rx_n,
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input wire [NO_OF_LANES-1:0] gt_rx_p,
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output wire [NO_OF_LANES-1:0] gt_tx_n,
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output wire [NO_OF_LANES-1:0] gt_tx_p,
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input wire [63:0] gt_tx_data,
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input wire [7:0] gt_tx_data_k,
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input wire [7:0] gt_tx_elec_idle,
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input wire [7:0] gt_tx_detect_rx_loopback,
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input wire [7:0] gt_tx_compliance,
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input wire [7:0] gt_rx_polarity,
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input wire [15:0] gt_power_down,
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input wire [7:0] gt_deskew_lanes,
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input wire [7:0] gt_pipe_reset,
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input wire [7:0] gt_rx_present,
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input wire gsr,
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input wire gtreset,
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input wire refclk,
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output wire refclkout_bufg,
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output wire gtclk_bufg,
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output wire [7:0] resetdone,
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output wire [3:0] plllkdet_out,
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input wire gt_usrclk,
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input wire gt_usrclk2,
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input wire txsync_clk,
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output wire [7:0] rxbyteisaligned,
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output wire [7:0] rxchanbondseq,
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output wire pcie_reset,
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input wire clock_lock,
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input wire trn_lnk_up_n,
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// GTP register ports
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input wire gt_dclk,
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input wire [NO_OF_LANES*7-1:0] gt_daddr,
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input wire [NO_OF_LANES-1:0] gt_den,
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input wire [NO_OF_LANES-1:0] gt_dwen,
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input wire [NO_OF_LANES*16-1:0] gt_di,
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output wire [NO_OF_LANES*16-1:0] gt_do,
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output wire [NO_OF_LANES-1:0] gt_drdy,
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input wire [2:0] gt_txdiffctrl_0,
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input wire [2:0] gt_txdiffctrl_1,
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input wire [2:0] gt_txbuffctrl_0,
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input wire [2:0] gt_txbuffctrl_1,
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input wire [2:0] gt_txpreemphesis_0,
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input wire [2:0] gt_txpreemphesis_1
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);
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generate
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// Instantiate wrapper for Rocket IO GTX transceivers if V5 FXT is used,
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// else instantiate wrapper for Rocket IO GTP transceivers
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if (USE_V5FXT == 0) begin
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pcie_gt_wrapper#
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(
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.NO_OF_LANES(NO_OF_LANES),
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.SIM(SIM),
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// REF_CLK_FREQ is 0 for 100 MHz, 1 for 250 MHz
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.PLL_DIVSEL_FB(REF_CLK_FREQ ? 1 : 5),
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.PLL_DIVSEL_REF(REF_CLK_FREQ ? 1 : 2),
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.CLK25_DIVIDER(REF_CLK_FREQ ? 10 : 4),
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.TXDIFFBOOST(TXDIFFBOOST)
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)
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pcie_gt_wrapper_i
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(
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.gt_rx_elec_idle (gt_rx_elec_idle),
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.gt_rx_status (gt_rx_status),
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.gt_rx_data (gt_rx_data),
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.gt_rx_phy_status (gt_rx_phy_status),
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.gt_rx_data_k (gt_rx_data_k),
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.gt_rx_valid (gt_rx_valid),
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.gt_rx_chanisaligned (gt_rx_chanisaligned),
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.gt_rx_n (gt_rx_n),
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.gt_rx_p (gt_rx_p),
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.gt_tx_n (gt_tx_n),
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.gt_tx_p (gt_tx_p),
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.gt_tx_data (gt_tx_data),
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.gt_tx_data_k (gt_tx_data_k),
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.gt_tx_elec_idle (gt_tx_elec_idle),
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.gt_tx_detect_rx_loopback(gt_tx_detect_rx_loopback),
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.gt_tx_compliance (gt_tx_compliance),
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.gt_rx_polarity (gt_rx_polarity),
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.gt_power_down (gt_power_down),
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.gt_deskew_lanes (gt_deskew_lanes),
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.gt_pipe_reset (gt_pipe_reset),
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.gt_rx_present (gt_rx_present),
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.gsr (gsr),
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.gtreset (gtreset),
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.refclk (refclk),
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.refclkout_bufg (refclkout_bufg),
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.gtclk_bufg (gtclk_bufg),
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.plllkdet_out (plllkdet_out),
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.resetdone (resetdone),
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.gt_usrclk (gt_usrclk2),
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.rxbyteisaligned (rxbyteisaligned),
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.rxchanbondseq (rxchanbondseq),
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.pcie_reset (pcie_reset),
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.clock_lock (clock_lock),
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// GTP register ports
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.gt_dclk (gt_dclk),
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.gt_daddr (gt_daddr),
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.gt_den (gt_den),
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.gt_dwen (gt_dwen),
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.gt_di (gt_di),
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.gt_do (gt_do),
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.gt_drdy (gt_drdy),
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.gt_txdiffctrl_0 (gt_txdiffctrl_0),
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.gt_txdiffctrl_1 (gt_txdiffctrl_1),
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.gt_txbuffctrl_0 (gt_txbuffctrl_0),
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.gt_txbuffctrl_1 (gt_txbuffctrl_1),
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.gt_txpreemphesis_0 (gt_txpreemphesis_0),
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.gt_txpreemphesis_1 (gt_txpreemphesis_1)
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);
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end else begin
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pcie_gtx_wrapper#
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(
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.NO_OF_LANES(NO_OF_LANES),
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.SIM(SIM),
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.PLL_DIVSEL_FB(REF_CLK_FREQ ? 2 : 5), // REF_CLK_FREQ is 0 for 100 MHz, 1 for 250 MHz
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.PLL_DIVSEL_REF(REF_CLK_FREQ ? 1 : 1),
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.CLK25_DIVIDER(REF_CLK_FREQ ? 10 : 4),
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.TXDIFFBOOST(TXDIFFBOOST),
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.GTDEBUGPORTS(GTDEBUGPORTS)
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)
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pcie_gt_wrapper_i
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(
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.gt_rx_elec_idle (gt_rx_elec_idle),
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.gt_rx_status (gt_rx_status),
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.gt_rx_data (gt_rx_data),
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.gt_rx_phy_status (gt_rx_phy_status),
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.gt_rx_data_k (gt_rx_data_k),
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.gt_rx_valid (gt_rx_valid),
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.gt_rx_chanisaligned (gt_rx_chanisaligned),
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.gt_rx_n (gt_rx_n),
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.gt_rx_p (gt_rx_p),
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.gt_tx_n (gt_tx_n),
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.gt_tx_p (gt_tx_p),
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.gt_tx_data (gt_tx_data),
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.gt_tx_data_k (gt_tx_data_k),
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.gt_tx_elec_idle (gt_tx_elec_idle),
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| 241 |
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.gt_tx_detect_rx_loopback(gt_tx_detect_rx_loopback),
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| 242 |
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.gt_tx_compliance (gt_tx_compliance),
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| 243 |
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.gt_rx_polarity (gt_rx_polarity),
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| 244 |
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.gt_power_down (gt_power_down),
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| 245 |
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.gt_deskew_lanes (gt_deskew_lanes),
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| 246 |
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.gt_pipe_reset (gt_pipe_reset),
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| 247 |
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.gt_rx_present (gt_rx_present),
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| 248 |
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| 249 |
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.gsr (gsr),
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| 250 |
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.gtreset (gtreset),
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| 251 |
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.refclk (refclk),
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| 252 |
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.refclkout_bufg (refclkout_bufg),
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| 253 |
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.gtclk_bufg (gtclk_bufg),
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| 254 |
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.plllkdet_out (plllkdet_out),
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| 255 |
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.resetdone (resetdone),
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| 256 |
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.gt_usrclk (gt_usrclk),
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| 257 |
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.gt_usrclk2 (gt_usrclk2),
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| 258 |
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.txsync_clk (txsync_clk),
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| 259 |
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.rxbyteisaligned (rxbyteisaligned),
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| 260 |
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.rxchanbondseq (rxchanbondseq),
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| 261 |
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| 262 |
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.pcie_reset (pcie_reset),
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| 263 |
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.clock_lock (clock_lock),
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| 264 |
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.trn_lnk_up_n (trn_lnk_up_n),
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| 265 |
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// GTP register ports
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| 267 |
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.gt_dclk (gt_dclk),
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| 268 |
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.gt_daddr (gt_daddr),
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| 269 |
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.gt_den (gt_den),
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| 270 |
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.gt_dwen (gt_dwen),
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| 271 |
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.gt_di (gt_di),
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| 272 |
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.gt_do (gt_do),
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| 273 |
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.gt_drdy (gt_drdy),
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| 274 |
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| 275 |
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.gt_txdiffctrl_0 (gt_txdiffctrl_0),
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| 276 |
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.gt_txdiffctrl_1 (gt_txdiffctrl_1),
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| 277 |
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.gt_txbuffctrl_0 (gt_txbuffctrl_0),
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| 278 |
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.gt_txbuffctrl_1 (gt_txbuffctrl_1),
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| 279 |
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.gt_txpreemphesis_0 (gt_txpreemphesis_0),
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| 280 |
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.gt_txpreemphesis_1 (gt_txpreemphesis_1)
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| 281 |
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| 282 |
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);
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end
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endgenerate
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endmodule
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